JPH07326983A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To dispense with the time measurement of an ON/OFF period of received data and an oscillation circuit required for it by checking the resonant state of a transmitting/receiving coil at timing synchronous with the transmission end timing of a data signal by a data carrier. CONSTITUTION:The transmission end timing of the data signal to be transmitted from an antenna 1 is made to be of a definite period. Further, its transmission start timing is changed to first timing before the transmission end timing of an answer signal S11 transmitted from the data carrier 2 or second timing after the transmission end timing in accordance with the contents of data. Thus, the resonant state of the transmitting/receiving coil L3 of the data carrier 2 can be changed in accordance with the contents of the data. The data carrier 2 can discriminate the contents of the received data signal by checking the resonant state of the coil L3 at the timing synchronous with the transmission end timing of the data signal. At the time of this discrimination, the duration of the same state of the received signal need not be measured, and a timing means including the oscillation circuit is dispensed with.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device for transmitting digital data from a transmission side device to a reception side device.

[0002]

2. Description of the Related Art For example, a data carrier system for transmitting and receiving data between a data carrier attached to an article conveyed on a conveyor and an antenna installed on a part of a conveyance path constituted by the conveyor. There is a data transmission device. In such a data transmission apparatus, as shown in FIG. 5, the transmission / reception circuit 5 of the antenna 50, which is the transmission side apparatus, is used.
Digital data S of a binary signal of "1" or "0" from 1 to a receiving side device 60 such as a data carrier.
21 is transmitted. The reception side device 60 receives the data signal S21 by the transmission / reception circuit 61 including a coil, and receives the reception signal S21.
22 is led to the control circuit 62, and the content of the transmitted data is determined.

In the data discriminating process in the receiving side device 60, as shown in FIG. 6, a biphase code containing a synchronous clock component or the like is used to separate each bit of the data, and a signal level is set. The content of the data is discriminated based on the temporal length of the change cycle of. For example, the bi-phase code has "Hi" to "L" depending on the contents of "1" or "0" at the center of each bit.
Although it is switched from “o” or “Lo” to “Hi”, the level does not always change at the bit boundary.
Therefore, by observing the level change cycles t1, t2, ..., tN of the bi-phase code at every bit cycle tA, it is possible to determine whether the pattern is a "1" pattern or a "0" pattern. Read the data. In this way, the receiving-side device 60 measures the temporal length of the received signal, and in order to discriminate the content of the data based on the length, the oscillation circuit 63.
The control circuit 62 counts the number of reference pulses output from the oscillation circuit 63 while the same level of the received signal continues.

[0004]

However, in the conventional data transmission apparatus, in order to measure the duration of the same level of the received signal, the receiving side apparatus must be provided with the clocking means including the oscillation circuit, and the circuit There is a problem that the device becomes large and the cost increases due to the complicated structure. In addition, when sufficient power is required to supply to the oscillation circuit of the timekeeping means, and when power is supplied from the transmission side device to the reception side device by electromagnetic induction, it is between the transmission side device and the reception side device. However, there is a problem that the time of data transmission must be strictly maintained in the transmission side device as well.

It is an object of the present invention to include a response signal transmitted in synchronization with a transmission start timing of a data signal transmitted from a transmission side apparatus to a reception side apparatus from a reception side apparatus. By switching to the first timing to be performed or the second timing not to be included, it is not necessary to distinguish the content of the data by the duration of the same level of the received signal, and the timing device including the transmission circuit can be omitted from the receiving side device, Provided is a data transmission device that can realize downsizing and cost reduction of a transmission side device, can increase the distance between a transmission side device and a reception side device, and does not need to maintain constant data timing in the transmission side device. To do.

[0006]

In a data transmission apparatus of the present invention, a reception side device is provided with a transmission / reception coil for transmitting and receiving a signal, and a response signal is synchronized with a transmission end timing of a data signal transmitted from the transmission side device. And a data discriminating unit that discriminates the content of the data signal based on a change in the resonance state of the transmission / reception coil in one cycle of the transmission end timing of the data signal. The transmission start timing of the data signal transmitted at the transmission end timing of the cycle is set to a first timing earlier than the transmission end timing of the response signal or a second timing later than the transmission end timing of the response signal depending on the content of the data. It is characterized in that a transmission start timing switching means for switching to either one is provided.

[0007]

According to the present invention, the receiving side device receives the data signal transmitted from the transmitting side device by the transmitting and receiving coil and transmits the response signal from the same transmitting and receiving coil in synchronization with the transmission end timing of the received data signal. To do. Therefore, the transmission / reception coil resonates when receiving the data signal and when transmitting the response signal. The transmission side device sets the transmission start timing of the data signal to a first timing earlier than the transmission end timing of the response signal or the second timing later than the transmission end timing of the response signal according to the content of data to be transmitted to the reception side device. Switch to one of.

When the data signal is transmitted from the transmission side device at the first timing, the data signal is transmitted from the transmission side device before the transmission of the response signal from the reception side device is stopped, and the reception side device is transmitted. The transmission / reception coil continuously resonates from the start of the response signal transmission to the end of the data signal reception, and from the non-resonant state to the resonance state from the start of the response signal transmission to the end of the next data signal reception. Never changes to.

On the other hand, when the data signal is transmitted from the transmission side device at the second timing, the transmission side device transmits the data signal after the transmission of the response signal from the reception side device is stopped, and the reception side device transmits the data signal. The transmission / reception coil of the device temporarily suspends resonance from the start of the response signal transmission to the end of the data signal reception, and from the non-resonant state to the resonance from the start of the response signal transmission to the end of the next data signal reception. Change to state.

Therefore, the receiving side device checks whether or not the resonance state of the transmission / reception coil changes from the non-resonance state to the resonance state from the start of the transmission of the response signal to the end of the reception of the next data signal. Thus, the content of the data signal transmitted from the transmitting side device can be determined. Since the reception side device transmits the response signal in synchronization with the transmission end timing of the received data signal, in one cycle of the data signal transmission end timing, the change of the data signal You can judge the contents.

[0011]

1 is a diagram showing a data carrier system which is a data transmission apparatus according to an embodiment of the present invention. The data carrier system includes a data carrier 2 attached to a moving body 3 conveyed on a conveyor 10 and an antenna 1 installed in a conveying path of the moving body 3 constituted by the conveyor 10. . Antenna 1
Is connected to a host device (not shown) by a data cable 4, and regardless of the presence or absence of the data carrier 2, the mobile unit 3
The data signal is transmitted to the communicable range 5 including a part of the carrier path. When the data carrier 2 enters the communicable range 5, the data carrier 2 receives the data signal transmitted from the antenna 1. Data carrier 2
Performs, for example, processing such as writing / reading of data indicating the characteristics of the moving body 3 according to the content of the data signal.

FIG. 2 is a diagram showing the configuration of the antenna of the data carrier system. The antenna 1 includes a transmitter circuit 11 including a transmitter coil L1 and a receiver circuit 12 including a receiver coil L2. In the transmission circuit 11, a clock signal S1 and data S2 having a constant cycle output from a control circuit (not shown) are supplied to the AND gate 14 and the OR gate 15.
Entered via. The data S2 is a binarized signal indicating the content of data to be transmitted from the antenna 1 to the data carrier 2. For example, the data S2 represents “1” when the data S2 is at a high level and “0” when the data S2 is at a low level. Represents Further, the antenna 1 has a flip-flop 13 to which the reception signal S3 of the reception circuit 12 is input together with the clock signal S1.
Is equipped with.

With the above structure, the clock signal S1 and the data S2 shown in FIG. 4 are supplied to the antenna 1 from the control unit (not shown). When the receiving coil L2 receives the external signal in the state shown in the figure, the receiving circuit 12 detects the receiving level of the receiving coil L2 at the reference level Va and outputs the receiving signal S3 shown in the figure. The reception signal S3 is input to the set terminal of the flip-flop 13, and the clock signal S1 is input to the reset terminal of the flip-flop 13. As a result, the Q output S of the flip-flop 13
4 is input to the AND gate 14 together with the data S2 in the state shown in FIG.

The AND gate 14 takes the logical product of the data S2 and the Q output S4 of the flip-flop 13 and outputs the signal S5 shown in the figure. The output signal S5 of the AND gate 14 is input to the OR gate 15 together with the clock signal S1. The OR gate 15 receives the clock signals S1 and AN.
The logical sum of the output signal S5 of the D gate 14 and the drive signal S6 is supplied to the transmission circuit 11. As a result, the transmission coil L1 resonates in the state shown in the figure and transmits the data signal SL1.

As described above, the waveform of the data signal transmitted from the transmission coil L1 is determined. The drive signal S6 falls in a constant cycle in agreement with the clock signal S1 regardless of the content of the data S2, and rises at the first or second timing according to the content of the data S2. The first timing at which the drive signal S6 rises when the data S2 is at a high level matches the rising timing of the reception signal S3, and is earlier than the second timing at which the drive signal S6 rises when the data S2 is at a low level.

For example, the clock signal S at time td
When the data S2 rises after the fall of 1, the drive signal S6 rises in synchronization with the rise of the reception signal S3 at time tp, and the data signal SL1 is transmitted earlier than the fall of the reception signal S3 at time tq. On the other hand, when the data S2 is at low level, the time t
At a, tc, or tg, the drive signal S6 rises in synchronization with the clock signal S1 and the reception signal S3 falls, and then the transmission of the data signal SL1 is started.

FIG. 3 is a diagram showing a structure of a data carrier of the above data carrier system. Data carrier 2
Includes a transmission / reception circuit 21 including a transmission / reception coil L3 and modulation / demodulation circuits 22 and 23. An edge detection circuit 24, a self-signal cutoff circuit 25, a one-shot circuit 26, a flip-flop 27 and an inverter 28 are connected to the subsequent stage of the demodulation circuit 23. The modulation circuit 22 modulates the response signal S11 output from the control unit (not shown) to transmit / receive the circuit 21.
Supply to. The demodulation circuit 23 demodulates the resonance signal output from the transmission / reception circuit 21 and supplies it to the edge detection circuit 24 as a demodulation signal S12. The edge detection circuit 24 detects the falling and rising timings of the demodulated signal S12 and supplies it to the self-signal cutoff circuit 25.

The self-signal cutoff circuit 25 is provided with a response signal S11.
Disconnects the edge detection circuit 24 from the one-shot circuit 26 and the flip-flop 27 during the period when is high level. The one-shot circuit 26 outputs a negative rectangular wave having a predetermined pulse width as the reception clock signal D1 when the falling signal S13 output from the self-signal interruption circuit 25 switches from high level to low level. The flip-flop 27 includes the rising signal S14 output from the self-signal cutoff circuit 25 and the one-shot circuit 2
The reception data signal D2 is output based on the reception clock signal D1 output from the control circuit 6.

With the above configuration, when the data signal SL1 is transmitted from the transmitting coil L1 of the antenna 1 in the state shown in FIG. 4, the transmitting / receiving coil L3 of the data carrier 2 resonates in the state shown in FIG. From resonance signal SL3
Is output. The demodulation circuit 23 detects the resonance signal SL3 with the reference voltage Vb and outputs the demodulation signal S12 shown in FIG. The demodulated signal S12 is input to the edge detection circuit 24, and the edge detection circuit 24 outputs a pulse wave at the falling timing and the rising timing of the demodulated signal S12 and inputs the pulse wave to the self-signal cutoff circuit 25.

The self-signal cutoff circuit 25 operates in response to the response signal S11.
Since the output of the edge detection circuit 24 is invalidated during the high level period of, the self-signal cutoff circuit 25 outputs the falling signal S13 and the rising signal S14 as shown in FIG. Therefore, as shown in the figure,
The rising and falling edges of the demodulated signal S12 at time t2 are excluded from the rising edge signal S14 and the falling edge signal S13. The falling signal S13 is supplied to the one-shot circuit 26, and the one-shot circuit outputs the reception clock signal D1 shown in FIG. The reception clock signal D1 is supplied to a control circuit (not shown) and serves as a reference for determining the output timing of the response signal S11. That is, the response signal S11 is the time t from the reception clock signal D1.
It is set to the high level in the period of time t2 with a delay of 1.

The reception clock signal D1 is input to the reset terminal of the flip-flop 27. On the other hand, the rising signal S14 is input from the self-signal cutoff circuit 25 to the set terminal of the flip-flop 27. As a result, the Q output of the flip-flop 27 has a waveform that rises at the rising timing of the rising signal S14 and falls at the rising timing of the reception clock signal D1 as shown in FIG. This Q output is the inverter 2
The signal is inverted by 8 and the received data signal D2 shown in the figure is output to the control circuit.

The received data signal D2 shows the content of the data signal SL1 received by the transmission / reception coil L3.
For example, when the data signal SL1 rises at the first timing at the time tp, the transmission / reception coil L3 moves at the time t.
The data signal SL1 is received before the resonance state by the response signal S11 of its own which started transmission at r is stopped, and the resonance state is continued until the data signal SL1 falls at the time tf. Therefore, the rising signal S14 is not output during the period of one cycle of the falling timing of the reception clock signal D1 between the times tk and tm, and the rising signal S14 is not output.
During the period of one cycle of the response signal S11 that is output subsequent to the reception clock signal D1 at the time tm and the time tm, the reception data signal D2 remains at the high level.

On the other hand, when the data signal SL1 rises at the second timing at the time ta, tc or tg,
The transmission / reception coil L3 has a resonance signal SL3a based on its own response signal S11 transmitted in synchronization with the reception clock signal D1.
Receives the data signal SL1 after being in a non-resonant state,
For example, the rising signal S14 is output during the period of one cycle of the falling timing of the reception clock signal D1 between the time ti and the time tk, and the reception data signal D2 changes from the high level to the low level at the time tj.

Therefore, each falling timing of the received clock signal D1 (for example, time ti, tk or t)
In m), the content of the data signal SL1 transmitted from the antenna 1 can be determined by checking the level of the received data signal D2. That is, the control circuit (not shown)
The state of the received data signal D2 is determined at the falling timing of the received clock signal D1, and when the received data signal D2 is in the low level state, the content of the data transmitted from the antenna 1 is "0". If the state of the received data signal D2 is high level, it is determined that the content of the transmitted data is "1".

As described above, according to this embodiment, the transmission end timing of the data signal SL1 transmitted from the antenna 1 is set to a fixed period, and the transmission start timing is set to the response signal S1 transmitted from the data carrier 2.
The resonance state in the transmission / reception coil L3 of the data carrier 2 is changed by switching to the first timing before the transmission end timing of 1 or the second timing after the transmission end timing of the response signal S11 according to the content of the data S2. It can be changed according to the content of the data S2. The data carrier 2 can determine the content of the received data signal SL1 by checking the resonance state of the transmission / reception coil L3 at the timing synchronized with the transmission end timing of the data signal SL1.

As described above, the data carrier 2 does not need to measure the duration of the same state of the received signal when determining the content of the data signal SL1, and the time measuring means including the oscillation circuit is unnecessary. Further, since the reception clock signal D1 and the reception data signal D2 used for determining the content of the transmission data in the data carrier 2 are created based on the transmission signal SL1 transmitted from the antenna 1, the processing timing of the data carrier 2 is set. It is possible to reliably synchronize with the processing timing of the antenna 1. Therefore, it is not necessary to strictly maintain the processing speed including data timing in the antenna 1, and there is an advantage that the configuration of the antenna 1 can be simplified.

[0027]

According to the present invention, the reading timing of data in the receiving side device can be set by the transmitting side device, and the content of the transmitted data signal can be accurately determined according to the state of the received signal at the reading timing. It is not necessary to provide the receiving side device with the transmitting circuit and the power supply circuit that are required to measure the duration of the same state of the received signal, and the structure of the receiving side device can be simplified and downsized. There is an advantage that can be. Also,
Since the power consumption of the receiving side device can be reduced, there is an advantage that the communicable distance between the receiving side device and the transmitting side device of the external power feeding method can be lengthened. Further, since the processing timing of the receiving side device is determined based on the data signal transmitted from the transmitting side device, the processing timing of the receiving side device is always synchronized with the processing timing of the transmitting side device, and the processing timing of the transmitting side device is There is an advantage that it is not necessary to strictly maintain the accuracy of the transmission circuit that determines the value, and the configuration of the transmission side device can be simplified.

[Brief description of drawings]

FIG. 1 is a diagram showing a data carrier system to which a data transmission device of the present invention is applied.

FIG. 2 is a block diagram of an antenna that constitutes the same data carrier system.

FIG. 3 is a block diagram of a data carrier forming the same data carrier system.

FIG. 4 is a timing chart showing a signal state in each part of the antenna and the data carrier.

FIG. 5 is a diagram showing a configuration of a conventional data transmission device.

FIG. 6 is a diagram showing waveforms of a transmission signal and reception data in the conventional data transmission device.

[Explanation of symbols]

 1-antenna (transmitting device) 2-data carrier (receiving device) L3-transmission / reception coil

Claims (1)

[Claims] 1. A response side signal transmission means for transmitting / receiving a signal to / from a reception side device, the response side signal transmitting means transmitting a response signal in synchronization with a transmission end timing of a data signal transmitted from the transmission side device; A data discriminating means for discriminating the content of the data signal based on a change in the resonance state of the transmission / reception coil in one cycle of the transmission end timing, and the transmission side device transmits the data signal to be transmitted at the transmission end timing of a constant cycle. The start timing is earlier than the transmission end timing of the response signal according to the content of the data.
And a transmission start timing switching means for switching to either of the second timing or the second timing which is later than the transmission end timing of the response signal.