JPH07326741A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to contrive the stabilization of a gate oxide film on the corner parts of a groove. CONSTITUTION:A semiconductor substrate 20 is constituted of an n<+> substrate 21 and an n<-> epitaxial layer 22 and a rectangle-shaped and U-shaped groove 23 is formed in the surface of this substrate 20 in a plane pattern. A p-type base layer 24 and an n<+> source layer 25, which are formed by superposing, are exposed in the side surface 232 of this groove 23, a gate electrode film 27 is provided on the inner periphery of the groove 23 via a gate oxide film 26 and a channel is formed. Here, the film 27 is formed in such a way as to avoid specially the square parts of the groove and a semiconductor device is constituted so that the reliability of the performance characteristics of the device are effectively ensured along with the stabilization of the life of the film 27 on these square parts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device effectively constituted as a vertical MOS transistor used for electric power, a vertical IGBT or the like.

[0002]

2. Description of the Related Art Vertical MOS transistors and vertical IGBTs
The vertical insulated gate semiconductor device as described above has a feature that it can be driven by low power. Such a vertical MOS transistor is used as a high-speed switching element, and a vertical IGBT is widely known as a high-power switching element. And such vertical MOS transistors and vertical IGBTs
In the above, both low loss and low on-resistance are required.

FIG. 10 shows a conventional vertical MOS.
1 shows a cross-sectional structure of a transistor, which is manufactured by a planar process. That is, an n ⁻ semiconductor layer 12 is formed on the surface of an n ⁺ type semiconductor wafer 11 by epitaxial growth to form a semiconductor substrate 13, and a p region 14 is formed on the surface of the semiconductor substrate 13.
And n ⁺ region 15 are formed in an overlapping manner. This semiconductor substrate 13
The gate electrode 17 is formed on the surface of the gate insulating film 16 and the source electrode 18 is further formed, and the channel region C is formed corresponding to the p region 14. A drain electrode 19 is formed on this. In the vertical MOS transistor having such a configuration, the channel width per area is increased by reducing the cell size in order to reduce the loss.

However, the reduction of the on-voltage due to the reduction of the cell size is approaching the limit, and the cause thereof is the increase of the voltage drop in the equivalent JFET section due to the reduction of the cell size. As a means for reducing the cell size while suppressing an increase in voltage drop in such an equivalent JFET portion, for example, Japanese Patent Laid-Open No. 4-229662 proposes a trench gate type MOS transistor, and further, its trench structure. As JP-A-56
The U-shaped groove structure disclosed in Japanese Patent Laid-Open No. 58267,
A V-groove structure disclosed in JP-A-55-133573 has been proposed. That is, the channel is formed on the side surface of the groove structure portion, and even if the cell size is reduced by adopting such a channel structure, the voltage drop in the equivalent JFET portion is suppressed. The low on-voltage can be achieved.

In such a trench gate type MOS transistor or U-shaped groove or V-shaped groove type MOS transistor which is effective for reducing the on-state voltage, for example, in the trench gate type MOS transistor, Japanese Patent Laid-Open No. 4-1625 is available.
As disclosed in Japanese Patent Laid-Open No. 72-72, the thickness and film quality of the gate oxide film at the corner portion on the side surface of the trench groove are different from those of the other portions, but in order to secure further reliability in characteristics. It becomes a problem. Therefore, in the technique disclosed in JP-A-4-162257, the transistor operation is suppressed especially in the corner portion on the side surface of the trench groove in order to uniformize the characteristics in the channel portion. Specifically, the source region is not formed in the corner portion on the side surface of the trench groove.

However, even in such a structure, the gate electrode film is formed together with the gate oxide film in the corner portion of the trench groove. Therefore, a high electric field is applied to the gate oxide film, and the gate oxidation film is formed. The life of the gate oxide film at the corner portion on the side surface of the trench groove in which the film quality is different from that of the other portion is different from that of the other portion. In particular, in the corner portion on the side surface of the trench groove, the properties of the gate oxide film at the uppermost portion and the lowermost portion are largely different from those of the other portions, so that the life of the gate oxide film is also different.

[0007]

The present invention has been made in view of the above points, and is provided with a groove structure such as a trench groove, a U-shaped groove and a V-shaped groove, and corresponds to the side surface of this groove structure. In a vertical transistor such as a vertical MOS transistor or a vertical IGBT in which a channel is formed, the life of the gate oxide film in the corner portion on the side surface of the groove structure portion is stabilized, An object of the present invention is to provide a semiconductor device in which reliability of operating characteristics is effectively ensured.

[0008]

In a semiconductor device according to the present invention, a groove having a side surface intersecting with the surface is formed on the surface of a semiconductor substrate of a first conductivity type, and the groove is in contact with the side surface of the groove. A second conductivity type layer and a first conductivity type layer are formed over the semiconductor substrate, and a gate electrode film is formed on a side surface of the groove through a gate oxide film. In a type transistor, a gate electrode film is formed to overlap a side edge formed by a line where there is no corner portion of the groove formed in the semiconductor substrate, and the gate electrode film is formed avoiding the corner portion where the side edge intersects. I chose

[0009]

In the semiconductor device having such a structure, the gate electrode film does not exist at the corners of the side surface of the groove structure portion, and therefore a high electric field is applied to the gate oxide film at this corner portion. Is not applied, and the withstand voltage characteristic and life characteristic of the gate oxide film are improved particularly in this corner portion. The breakdown voltage characteristics and life characteristics of the gate oxide film are determined by the portion of the gate oxide film having the poorest characteristics, but in this semiconductor device, the gate electrode film is formed only in the portion where the characteristics of the gate oxide film are uniform. Therefore, there is no portion having poor characteristics in the portion to which the electric field is applied in the gate oxide film, and the withstand voltage characteristic and the life characteristic of the gate oxide film are improved. Also,
The gate electrode film is formed only in a portion where the characteristics of the gate oxide film are made uniform, and the channel is formed, so that the electric characteristics can be effectively made uniform.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a vertical MOS transistor as an example. An n ⁻ semiconductor layer is formed as an epitaxial growth layer 22 on the surface of an n ⁺ type substrate 21, and a semiconductor substrate 20 is formed.
Is configured. On the surface of the n ⁻ type epitaxial layer 22 which constitutes such a semiconductor substrate 20, a rectangular groove 23 having a plane pattern, that is, a rectangular groove 23 in which four straight side edges are continuous is formed. This groove 23 is used for the substrate 20.
A groove bottom portion 231 parallel to the surface of the groove and a rising groove side surface 232 inclined at the side edge thereof. Then, the side surface 232 of this groove 23
An n ⁺ type source layer 25 is formed on the substrate surface side of the base layer 24 so as to be exposed to the substrate.

Inside the groove 23, a gate electrode film 27 is formed through the gate oxide film 26 corresponding to the groove bottom surface 231 and the groove side surface 232.
It is formed to extend from 23 to the surface of the semiconductor substrate 20 and to the surface of the n ⁺ type source layer 25. In this case, on the surface of the semiconductor substrate 20, the gate is formed at the corner (corner) portion where the extending direction of the straight side edge forming the groove 23 is different, as shown by the hatched area in FIG. Electrode film 27
Is not formed.

Here, when a plurality of vertical MOS transistors are arranged and formed on one semiconductor substrate 20, each MO
The S transistors are arranged in a matrix on the surface of the semiconductor substrate 20 so as to extend in the column and row directions, and the rectangular grooves on the surface of the semiconductor substrate 20 are also arranged in a matrix. In this case, the gate electrode films respectively corresponding to the respective MOS transistors are formed so as to exclude the corner portions of the side surfaces thereof corresponding to the respective groove portions. For example, the short side portion of this rectangular pattern is formed. The gate electrode of each of the groove structure portions adjacent to each other is connected by an electrode strip 271 extending so as to intersect the short side portion of the side surface of the groove 23, and is common to the gate electrodes of the MOS transistors. Voltage is applied.

An n ⁺ type source layer is formed on the surface of the semiconductor substrate 20.
A source electrode 28 is formed so as to be in contact with 25, and a drain electrode 29 is formed on the back surface of the n ⁺ -type substrate 21 corresponding to the back surface of the substrate 20 to set the source potential and the drain potential, respectively. To do so. Although not shown in the figure, a gate electrode is formed and formed on the gate electrode film 27, and a gate voltage is applied.

FIG. 2 shows a manufacturing process of the vertical MOS transistor thus constructed. First, as shown in FIG. 2A, an n ⁻ semiconductor layer is formed as an epitaxial growth layer 22 on an n ⁺ substrate 21. Then, the semiconductor substrate 20 is obtained. Then, by thermally oxidizing the surface of the semiconductor substrate 20, S
A field oxide film 31 of iO ₂ is formed. A resist film 32 is deposited on the field oxide film 31, and is patterned by a photolithography process into a pattern having an opening located on the side of the region where the groove 23 is formed. If the mask of the resist film 32 is formed in this way, boron (B
⁺ ) Is ion-implanted.

After that, as shown in FIG.
32 is removed, and the implanted ions are thermally diffused by heat treatment to form a p-type diffusion layer 33. This p-type diffusion layer 33 finally forms a part of the p-type base layer 24, and by allowing a breakdown to occur stably at the bottom of the p-type diffusion layer 33, Surge resistance is improved. Then, a silicon nitride film 34 is further deposited on the surface of the field oxide film 31, the silicon nitride film 34 is patterned, and openings 341 corresponding to the shape pattern (rectangle) of the groove 23 are formed by etching.

After the silicon nitride film 34 having the opening 341 formed in this way, the field oxide film 31 corresponding to the opening 341 is etched by using the silicon nitride film 34 as a mask as shown in FIG. Further, the surface of the epitaxial growth layer 22 corresponding to the etched portion is etched to form the initial groove 35.

Next, as shown in FIG.
The initial groove 35 is thermally oxidized by using the mask 34 as a mask. This thermal oxidation is known as the LOCOS method.
A LOCOS oxide film 36 is formed at the portion 35. This LO
The COS oxide film 36 has, for example, a width of 2 μm to 20 μm and a length of 2 μm.
It is composed of a rectangular pattern having a thickness of 1 μm to 20 μm. Then, a U-shaped groove 23 is formed on the surface of the n ^- epitaxial layer 22 eroded by the LOCOS oxide film 36 so that its shape is determined.
Horizontal groove bottom due to bird's beak due to OCOS oxidation
An inclined groove side surface 232 is formed together with 231.

In this way, the LOC is formed so that the groove 23 is formed.
After the OS oxide film 36 is formed, the silicon nitride film 34 on the surface is removed as shown in FIG. 3A, and then the remaining LOCOS oxide film 36 is used as a mask to transmit the thin field oxide film 31. Boron is ion-implanted to form the p-type base layer 24. At this time, the LOCOS oxide film 36
The boundary portion between the field oxide film 31 and the field oxide film 31 becomes a self-aligned position, and the region into which ions are implanted is accurately defined.

When boron is ion-implanted in a predetermined region in this way, it is thermally diffused to a predetermined depth as shown in FIG. Due to this thermal diffusion, the p-type diffusion layer 33 previously formed by the step of FIG. 2B and the thermal diffusion layer in FIG. 3B are integrated to form one p-type base layer 24.
Is formed. Here, both end faces of the region of the p-type base layer 24 are defined in the position of the side wall of the groove 23 in a self-aligned manner.

Next, as shown in FIG. 3C, a p-type base region is formed.
At the center of 24, the LOCO
A patterned resist film 37 is formed so as to surround the region of the S oxide film 36. Then, this resist film 37
Using as a mask, phosphorus is ion-implanted through the thin field oxide film 31. In this case, as in the case of boron ion implantation in FIG. 7A, the boundary portion between the LOCOS oxide film 36 and the field oxide film 31 becomes a self-aligned position, and the phosphorus ion-implanted region is accurately defined. It

When phosphorus is ion-implanted in this manner, the n ⁺ source layer 25 is formed by thermal diffusion as shown in FIG. 5D, and at the same time, the p-type base layer 24 becomes the LOCOS oxide film 36. A channel C is set at a portion of the groove 23 formed by the above which is in contact with the side surface 232. By such a thermal diffusion process, the side surface of the region of the n ⁺ source layer 25 in contact with the side surface 232 of the groove 23 is defined in the position of the side surface 232 of the groove 23 in a self-aligned manner.

In this way, the groove 23 corresponding to the LOCOS oxide film 36 is formed, and the groove 23 is formed around the groove 23 together with the p-type base layer 24.
^{After the +} type source layer 25 is formed, the LOCOS oxide film 36 and the field oxide film 31 are removed by wet etching to expose the inner wall of the groove 23, as shown in FIG. After that, a very thin gate oxide film 26 having a thickness of, for example, about 50 nm to 100 nm is formed on the inner wall surface of the groove 23 by thermal oxidation. Here, the inner wall of the groove 23 is formed with good flatness, and the film quality of the gate oxide film 26 formed by thermal oxidation on this surface is excellent.

After the groove 23 and the gate oxide film 26 are formed in this way, for example, a polysilicon film is deposited by the CVD method, and phosphorus is diffused to form an electrode film in order to increase the conductivity of the polysilicon film. Form. By coating a photoresist film on this electrode film, selectively removing this resist film by etching by photolithography technology, and etching the electrode film by dry etching,
A gate electrode film 27 is formed corresponding to the inner surface of the groove 23.

In this way, the vertical MO as shown in FIG.
The S-transistor is completed, but in this case, the gate electrode film 27 is formed in a plane pattern in a region overlapping a pair of long sides of the rectangular groove 23 so as to face the groove side surface 232. It is formed. In addition, this gate electrode film 27
Is formed so as not to overlap the pair of short sides of the groove 23, and the groove 23
Is formed in a range excluding the continuous corner portions of each side wall.

As described above, when a plurality of vertical MOS transistors are arranged and formed on one semiconductor substrate 20, each MOS transistor is arranged to extend in the column and row directions on the surface of the semiconductor substrate 20. They are arranged in a matrix. For example, as shown in FIG. 5, a plurality of vertical MOS transistors 411, 412, ... Are arranged in a matrix so as to extend in the column and row directions. These vertical MOS transistors 411, 412 ,. The gate electrode films 431, 432, ... (27) are formed corresponding to the groove structures 421, 422 ,.

These gate electrode films 431, 432, ...
As shown in FIGS. 4A and 4B, the gate electrode films (eg, gate electrode films 431 and 432) that are formed corresponding to the grooves that overlap the pair of long sides of the groove 23 and that are adjacent to the short sides thereof are
They are interconnected by electrode strips 271. That is, the common gate voltage is surely applied to the gate electrodes of the plurality of vertical MOS transistors 411, 412 ,.

FIG. 6 shows a second embodiment. In this embodiment, a groove 23 is formed on the surface of the semiconductor substrate 20 in the form of a mesh formed by a combination of lines extending vertically and horizontally. Has been formed. Then, for example, island-shaped portions 451, 452, ...
Are arranged in rows and columns, and are provided so as to project on the surface of the semiconductor substrate 20.

FIG. 7 shows one of the island-shaped portions 45 (451, 452, ...).
This island-shaped part is shown by taking out the part corresponding to one
The circumference of 45 is surrounded by the inclined side surface of the groove 23. That is, in the semiconductor device configured as described above, the LOCOS oxide film is formed in a mesh pattern on the surface of the semiconductor substrate 20 configured as shown in FIG. At the same time, boron and phosphorus are ion-implanted by using this LOCOS oxide film as a mask, and p type base layer 24 and n
^{A +} type source layer 25 is formed. And then LOCO
By removing the S oxide film, an island-shaped portion 45 protruding from the mesh is formed, and the p-type base layer 24 and the n ⁺ -type source layer 25 are exposed on the side surface of the island-shaped portion 45. Corresponding to the slope portion 45, a channel C is formed facing the gate electrode film 27 formed via the gate oxide film 26.

In this case, the gate electrode film 27 has a portion where straight line portions of the inclined rising side surfaces that define the groove 23 intersect,
That is, except for the four corners of the square island 45,
A gate electrode extending from four sides is formed on the quadrangular apex of the projected island-shaped portion 45 so as to cross the inclined side surface of the island-shaped portion 45 so as to avoid the corner portion of the groove 23. A contact area surrounded by the film 27 is set. The p-type base layer 24 is exposed at the center of the contact region, and the n ⁺ -type source layer 25 is formed so as to surround the p-type base layer 24.
Is exposed.

FIG. 8 shows a pattern of the gate electrode film 27 in the case where a plurality of projecting island-shaped portions 451, 452, ... Are arranged in rows and columns by the mesh-shaped grooves 23. In the figure, the region where the gate electrode film 27 is formed is shown by hatching for convenience. That is, the gate electrode film 27 formed so as to extend from the four sides of each of the island-shaped portions 451, 452, ... The common base potential is controlled to be applied.

In the embodiment of FIG. 1, trenches 23 having a rectangular pattern are formed on the surface of the semiconductor substrate 20, and the gate electrode film 25 is formed only on the side edges corresponding to the opposing long sides. Thus, the gate electrode film was formed on the side edge portion corresponding to the short side for connection with the adjacent cell.
In addition to the side edge portion corresponding to the long side, the gate electrode film 27 is formed so as to widely overlap the side edge portion corresponding to the short side as shown in, and the side surface of the groove corresponding to the long side and the short side portion is formed. And n ⁺
The channel may be formed on the groove side surfaces corresponding to the long side and the short side, respectively, by facing the type source layer 25 and the p-type base layer 24, respectively. In this case, the electrode strip 271 is formed so as to extend from the gate electrode film 27 portion extending to the side edge portion corresponding to this short side.

In the above embodiments, basically 4
Grooves 23 are formed by the straight side edges of the book, and islands
Although it is described that 45 is formed, this is not limited to the shape surrounded by the linear side edge in particular, and may be a groove structure of a shape surrounded by an arc-shaped side edge without being limited to the straight line. The same can be applied to a shape surrounded by a side edge of a circle or a polygonal structure such as a triangle or a hexagon.

In addition, when the groove 23 is formed on the surface of the semiconductor substrate 20 in a rectangular pattern, the groove 23 may be a linear groove 23 whose short side is extremely shorter than its long side. In this case, the portion corresponding to the short side of the rectangle is extremely short, and both ends of the pair of long sides are directly connected so as to be folded back. Therefore, the folded continuous portions at both ends of the pair of long sides are configured as folded corner portions without the straight portions corresponding to the short sides,
Therefore, the gate electrode film 27 is formed so as to overlap only with the pair of linear side edge portions, and is not formed at the folded continuous portion that is recognized as a corner portion.

In the above-described embodiments, the n ⁺ -type layer 25 formed on the p-type layer 24 is used as the source and the substrate 21 is used.
Is used as a drain to form a vertical MOS transistor. However, if the n ⁺ type layer 25 is used as the emitter and the n ⁺ type substrate 21 is used as the p ⁺ substrate and the collector, the vertical IGBT is constructed as it is. Even when the vertical IGBT is constructed, By configuring the gate electrode film as in the embodiment, the same effect can be obtained, and the reliability of its operation characteristics is secured. Further, the p and n conductivity type portions of this semiconductor device can also be configured to have opposite conductivity types.

[0035]

As described above, according to the semiconductor device of the present invention, the life characteristics of the gate oxide film can be surely improved, and the threshold voltages can be easily aligned. Vertical transistor is obtained.

[Brief description of drawings]

FIG. 1A is a diagram showing a pattern configuration seen from a plane for explaining a semiconductor device according to an embodiment of the present invention;
(B) is a cross-sectional configuration diagram corresponding to line bb in (A).

2A to 2D are views sequentially showing a process of manufacturing the semiconductor device.

3A to 3D are views sequentially showing a process of manufacturing a semiconductor device following FIG. 2D.

FIG. 4A is a diagram showing a plane pattern in which one transistor portion of the semiconductor device is taken out, and FIG. 4B is a sectional configuration diagram corresponding to line bb in FIG. 4A.

FIG. 5 is a diagram illustrating a gate electrode film pattern as seen from a plane of a semiconductor device in which a plurality of transistors are arranged.

FIG. 6 is a view for explaining a groove pattern which constitutes a semiconductor device according to a second embodiment of the present invention.

FIG. 7A is a pattern configuration diagram of the semiconductor device according to the embodiment as seen from a plane, and FIG. 7B is a sectional configuration diagram corresponding to the line bb in FIG. 7A.

FIG. 8 is a view for explaining the pattern of the gate electrode film of the semiconductor device according to this example.

FIG. 9 is a diagram showing a state of a plane pattern of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a cross-sectional configuration diagram illustrating a conventional MOS transistor.

[Explanation of symbols]

20 ... Semiconductor substrate, 21 ... N ⁺ substrate, 22 ... Epitaxial layer, 23 ... Groove, 231 ... Groove bottom surface, 232 ... Groove side surface, 24 ... P type base layer, 25 ... N ⁺ type source layer, 26 ... Gate oxide film , 27
... Gate electrode film, 28 ... Source electrode, 29 ... Drain electrode,
C ... Channel.

Claims (6)

[Claims] 1. A surface of a first conductivity type semiconductor substrate is formed with a groove having a side surface intersecting with the surface, and a second conductive layer is formed so as to overlap with the side surface of the groove so as to be in contact with the side surface of the semiconductor substrate. Type layer and a first conductivity type layer are formed, and a gate electrode film is formed on a side surface of the groove via a gate oxide film, wherein the gate electrode film is the semiconductor substrate. The semiconductor device is characterized in that the gate electrode film is formed so as to be overlapped with a side edge formed by a line having no corner portion of the groove formed in the above, and the gate electrode film is not formed at a corner portion where the side edge intersects. 2. The gate electrode film is formed in a rectangular shape on the surface of the semiconductor substrate, and the groove is formed so as to overlap a pair of opposing long sides of the rectangle in common and not to overlap the short sides thereof. The semiconductor device according to claim 1, wherein 3. The groove is formed in a polygonal shape formed by combining a plurality of line segments on the surface of the semiconductor substrate, overlaps with each line segment forming the polygonal shape, and the corner portion where each line segment is continuous has the above-mentioned shape. The semiconductor device according to claim 1, wherein the gate electrode film is not formed. 4. The groove is formed on the surface of the semiconductor substrate as a quadrilateral formed by a combination of four line segments, and the gate electrode film is formed in four directions so as to intersect each line segment. 4. The semiconductor device according to claim 3, wherein the gate electrode film is not formed at four continuous corner portions of each of the four line segments. 5. The grooves are formed in a rectangular shape on the surface of the semiconductor substrate, and a plurality of grooves are arranged in a matrix on the surface of the semiconductor substrate at predetermined intervals in the vertical and horizontal directions. The gate electrode film is formed so as to be commonly overlapped with a pair of long sides facing each other of a rectangle and not to be overlapped with the short sides thereof, and the short side portions are crossed to be connected to the gate electrodes of adjacent grooves. The semiconductor device according to claim 1, wherein a conductive piece is formed. 6. The groove is formed on the surface of the semiconductor substrate in the form of a mesh by linear portions extending in the vertical and horizontal directions, and the overlap is formed around a protruding island portion surrounded by the mesh of each mesh. The side portions of the second conductivity type layer and the first conductivity type layer are exposed, and an electrode film is formed on the exposed side surface with a gate via a gate oxide film. 2. The semiconductor device according to claim 1, wherein the gate electrode film is formed on the surface of the semiconductor substrate while avoiding the corners of the side edges of the groove.