JPH07326552A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07326552A JPH07326552A JP6117313A JP11731394A JPH07326552A JP H07326552 A JPH07326552 A JP H07326552A JP 6117313 A JP6117313 A JP 6117313A JP 11731394 A JP11731394 A JP 11731394A JP H07326552 A JPH07326552 A JP H07326552A
- Authority
- JP
- Japan
- Prior art keywords
- welded
- dummy electrodes
- semiconductor device
- wire
- lot number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ウエハーを分割して金
線等がワイヤボンディングされた半導体装置に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a wafer is divided and a gold wire or the like is wire-bonded.
【０００２】[0002]
【従来の技術】従来、この種の半導体装置として、図７
に示すものがある。このものは、ウエハーを分割した半
導体装置本体A にワイヤボンディングされたものであっ
て、このものの製造ロット番号はウエハーの表面にダイ
アモンド針により刻まれて表示されている。2. Description of the Related Art Conventionally, as a semiconductor device of this type, FIG.
There is one shown in. This is wire-bonded to a semiconductor device main body A obtained by dividing a wafer, and the manufacturing lot number of this is engraved on the surface of the wafer with a diamond needle.
【０００３】[0003]
【発明が解決しようとする課題】かかる従来の半導体装
置にあっては、ウエハーを分割する前はウエハーの表面
に表示された製造ロット番号を容易に確認することがで
きるが、ウエハーを分割した後では製造ロット番号を確
認することができないから、製造ロット番号を明記した
書面等で確認しなくてはならず、製造ロット番号を容易
に確認することができなかった。In such a conventional semiconductor device, the manufacturing lot number displayed on the surface of the wafer can be easily confirmed before dividing the wafer, but after dividing the wafer. However, since the production lot number cannot be confirmed, the production lot number must be confirmed in a document or the like, and the production lot number cannot be easily confirmed.
【０００４】本発明は、上記事由に鑑みてなしたもの
で、その目的とするところは、ウエハーを分割した後で
も容易に製造ロット番号を確認することができる半導体
装置を提供することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device in which a manufacturing lot number can be easily confirmed even after a wafer is divided.
【０００５】[0005]
【課題を解決するための手段】上記した課題を解決する
ために、請求項１記載のものは、ウエハーを分割してワ
イヤボンディングされた半導体装置において、前記ワイ
ヤボンディングの手段による金属の溶着の有無の状態が
識別符号となる識別部が設けられた構成としている。In order to solve the above-mentioned problems, according to a first aspect of the present invention, in a semiconductor device in which a wafer is divided and wire-bonded, whether or not metal is welded by the wire-bonding means. An identification unit whose state is the identification code is provided.
【０００６】また、請求項２記載のものは、請求項１記
載のものにおいて、前記識別部は、金属の溶着の有無の
状態を組み合わせた２進法で表示された構成としてい
る。According to a second aspect of the present invention, in the first aspect of the present invention, the identifying portion is configured to be displayed in a binary system in which the states of presence or absence of metal welding are combined.
【０００７】[0007]
【作用】請求項１記載のものによれば、製造ロット番号
は、ワイヤボンディングの手段によって、金属の溶着の
有無の状態が識別符号となる識別部に表示されるので、
ウエハーを分割した後でも容易に製造ロット番号を確認
することができる。According to the first aspect of the present invention, since the manufacturing lot number is displayed by the wire bonding means on the identification section, which indicates whether or not the metal is welded, as an identification code,
The manufacturing lot number can be easily confirmed even after dividing the wafer.
【０００８】請求項２記載のものによれば、識別部は、
金属の溶着の有無の状態を組み合わせた２進法で表示さ
れているから、請求項１記載のものよりもさらに容易に
製造ロット番号を確認することができる。According to the second aspect, the identification section is
The production lot number can be confirmed more easily than that of the first aspect because the binary display is used in which the states of whether or not the metal is welded are combined.
【０００９】[0009]
【実施例】本発明の一実施例を図１乃至図６に基づいて
以下に説明する。この半導体装置は、半導体装置本体1
、接続部2 、識別部3 で構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. This semiconductor device includes a semiconductor device body 1
, Connection part 2 and identification part 3.
【００１０】詳しくは、半導体装置本体1 は、シリコン
ウエハーを正方形状に分割したものであり、その表面の
四周縁に沿って金属材料よりなる正方形状をなした電極
部11が設けられ、その電極部11間の１つにダミー電極部
12が設けられている。そのダミー電極部12は、電極部11
よりも小さい正方形状の８個のダミー電極12a 乃至12h
で構成されており、４個ずつ２列に並んでいる。つまり
ダミー電極12a 乃至12d は、半導体装置本体の縁端部よ
りに１列に並び、ダミー電極12e 乃至12h は、ダミー電
極12a 乃至12d よりも中央部よりに１列に並んでいる。More specifically, the semiconductor device body 1 is formed by dividing a silicon wafer into squares, and square electrode portions 11 made of a metal material are provided along the four peripheral edges of the surface of the silicon wafer. Dummy electrode part in one of parts 11
Twelve are provided. The dummy electrode portion 12 is the electrode portion 11
Smaller than eight square dummy electrodes 12a to 12h
It is composed of 4 pieces, and 4 pieces are arranged in 2 rows. That is, the dummy electrodes 12a to 12d are arranged in a line from the edge portion of the semiconductor device body, and the dummy electrodes 12e to 12h are arranged in a line from the central portion rather than the dummy electrodes 12a to 12d.
【００１１】接続部2 は、半導体装置本体1 の電極部11
及び半導体装置本体1 を表面に配設した基板10等に設け
た電極部10a が金線20によりワイヤボンディングされて
形成される。詳しくは、金線20の一端部20a が初めに超
音波溶着等で半導体装置本体1 の電極部11に溶着され、
その金線20の他端部20b が同様に基板10等の電極部10a
に溶着して接続されて、接続部2 が形成される 識別部3 は、ダミー電極部12を構成するダミー電極12a
乃至12h のうち、ダミー電極12c,d,e,g,h のみに金線20
が溶着され、ダミー電極12c,d,e,g,h には金線20が溶着
されないことにより形成される。詳しくは、ワイヤボン
ディングする手段により、図４にダミー電極12c の場合
を例示するが、ダミー電極12c,d,e,g,hのそれぞれに金
線20の一端部20a が初めに超音波溶着等で溶着され、金
線20の他端部20b が一端部20a の溶着されたダミー電極
12c,d,e,g,h に再度溶着されると、金線20が溶着されて
いないダミー電極12a,b,f とともに、識別部3 が形成さ
れる。なお、図５に示すように、金線20の一端部20a が
初めに超音波溶着等で溶着されてから、クランパー等で
上方に強く引っ張って切断するマイクロバンプ法によ
り、他端部20b を溶着せずに金線20が溶着されても同様
に識別部3 が形成される。The connecting portion 2 is an electrode portion 11 of the semiconductor device body 1.
Also, the electrode portion 10a provided on the substrate 10 having the semiconductor device body 1 disposed on the surface thereof is formed by wire bonding with the gold wire 20. Specifically, one end 20a of the gold wire 20 is first welded to the electrode portion 11 of the semiconductor device body 1 by ultrasonic welding or the like,
The other end portion 20b of the gold wire 20 is also the electrode portion 10a of the substrate 10 or the like.
The connection part 2 is formed by welding and connecting the identification part 3 to the dummy electrode 12a forming the dummy electrode part 12.
20h to 12h, only the dummy electrodes 12c, d, e, g, and h
Is formed by welding, and the gold wire 20 is not welded to the dummy electrodes 12c, d, e, g, h. Specifically, the case of the dummy electrode 12c is illustrated in FIG. 4 by means of wire bonding, but one end 20a of the gold wire 20 is first ultrasonically welded to each of the dummy electrodes 12c, d, e, g, h. Dummy electrode with the other end 20b of the gold wire 20 welded at the other end 20a
When the gold wires 20 are welded again to 12c, d, e, g, and h, the identification portion 3 is formed together with the dummy electrodes 12a, b, f on which the gold wire 20 is not welded. As shown in FIG. 5, one end 20a of the gold wire 20 is first welded by ultrasonic welding or the like, and then the other end 20b is welded by a micro bump method in which a clamper or the like strongly pulls upward to cut. Even if the gold wire 20 is welded without it, the identifying portion 3 is similarly formed.
【００１２】次に、識別部3 による識別の仕方を説明す
る。識別部3 において、金線20が溶着されたダミー電極
12c,d,e,g,h に符号「１」を当て、金線20が溶着されて
いないダミー電極12c,d,e,g,h に符号「０」を当てる
と、ダミー電極a,b,c,d の配列により、「０」「０」
「１」「１」つまり１０進数では「３」を示す２進数
「００１１」が示されている。また、ダミー電極d,e,f,
g の配列により、「１」「０」「１」「１」つまり１０
進数では「１１」を示す２進数「１０１１」が示され
る。こうして、ダミー電極a,b,c,d の配列によりウエハ
ーの製造年「１９９３年」の下１桁の「３」が表示さ
れ、ダミー電極e,f,g,h の配列により、製造月「１１
月」の「１１」が表示される。Next, a method of identification by the identification unit 3 will be described. In the identification part 3, the dummy electrode with the gold wire 20 welded
If the reference numeral "1" is applied to 12c, d, e, g, h and the reference numeral "0" is applied to the dummy electrode 12c, d, e, g, h to which the gold wire 20 is not welded, the dummy electrodes a, b "0""0" depending on the array of, c, d
"1""1", that is, the binary number "0011" indicating "3" in decimal is shown. In addition, the dummy electrodes d, e, f,
Depending on the array of g, "1""0""1""1" that is, 10
The binary number "1011" indicating "11" is shown in the base number. Thus, the array of the dummy electrodes a, b, c, d indicates the last digit "3" of the wafer manufacturing year "1993", and the array of the dummy electrodes e, f, g, h indicates the manufacturing date " 11
"11" of "Month" is displayed.
【００１３】かかる半導体装置にあっては、上記したよ
うに、ダミー電極12a 乃至12h への金の溶着の有無の状
態の組み合わせた２進数を表示する識別部3 により、製
造年月を表示することができるので、容易に製造ロット
番号を確認することができる。In such a semiconductor device, as described above, the manufacturing date is displayed by the identification unit 3 which displays a binary number which is a combination of the states of whether or not the gold is welded to the dummy electrodes 12a to 12h. Therefore, the production lot number can be easily confirmed.
【００１４】なお、本実施例では、識別部3 は、金の溶
着の有無の状態を組み合わせた２進法で表示されている
が、製造年月をそれ程詳しく表示しなくてもよいとき
は、金の溶着の有無の状態のみで識別する識別符号とし
てもよく、そのときは識別部3を設ける手間を少なくす
ることができる。In the present embodiment, the identification portion 3 is displayed in a binary system in which the presence or absence of gold welding is combined, but when it is not necessary to display the manufacturing date in detail, The identification code may be identified only by the presence / absence of gold welding, in which case the labor of providing the identification unit 3 can be reduced.
【００１５】また、本実施例では、金の溶着の有無の状
態を表示するダミー電極12a 乃至12h は、電極部11間の
１つに集中して設けられているが、図６に示すように、
電極部11間に分散して設けられても同様の効果を奏する
ことができる。Further, in this embodiment, the dummy electrodes 12a to 12h for indicating the presence / absence of gold welding are concentrated on one electrode portion 11, but as shown in FIG. ,
Similar effects can be obtained even if they are provided dispersedly between the electrode parts 11.
【００１６】また、本実施例では、半導体装置にあって
はサイクル寿命が短く１０年前のものとは識別できるか
ら、製造年は、西暦の下１桁のみを記すようにしている
が、「１９９３」を２進数で表示できるようダミー電極
の数を増やしてもよく、そのときはサンプル等で１０年
を越える長期保存をするような場合でも、製造製造ロッ
ト番号を確認することができる。Further, in the present embodiment, since the semiconductor device has a short cycle life and can be distinguished from that of 10 years ago, only the last digit of the year is written as the manufacturing year. The number of dummy electrodes may be increased so that “1993” can be displayed in a binary number. At that time, even if a sample or the like is stored for a long period of more than 10 years, the manufacturing lot number can be confirmed.
【００１７】また、本実施例では、識別部3 は、１９９
３年１１月を表示しているが、ダミー電極12a 乃至12h
への金の溶着の有無の状態の組み合わせを変えることに
より、異なる年月も表示することができる。Further, in the present embodiment, the identification unit 3 has 199
3rd year of November is displayed, but dummy electrodes 12a to 12h
Different years and months can be displayed by changing the combination of the states of whether or not gold is welded to.
【００１８】[0018]
【発明の効果】請求項１記載のものは、製造ロット番号
は、ワイヤボンディングの手段によって、金属の溶着の
有無の状態が識別符号となる識別部に表示されるので、
ウエハーを分割した後でも容易に製造ロット番号を確認
することができる。According to the first aspect of the present invention, since the manufacturing lot number is displayed by the wire bonding means on the identification section, which indicates whether or not the metal is welded, as an identification code,
The manufacturing lot number can be easily confirmed even after dividing the wafer.
【００１９】請求項２記載のものは、識別部は、金属の
溶着の有無の状態を組み合わせた２進法で表示されてい
るから、請求項１記載のものよりもさらに容易に製造ロ
ット番号を確認することができる。According to the second aspect of the present invention, the identification portion is displayed in the binary system in which the state of the presence or absence of the metal welding is combined, so that the manufacturing lot number can be more easily than the first aspect. You can check.
【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図２】同上の識別部周辺を示す拡大平面図である。FIG. 2 is an enlarged plan view showing the periphery of the above identification unit.
【図３】同上の電極への金属の溶着状態を示す正面図で
ある。FIG. 3 is a front view showing a state in which a metal is welded to the above electrode.
【図４】同上のダミー電極への金属の溶着状態を示す正
面図である。FIG. 4 is a front view showing a state in which a metal is welded to the dummy electrode of the above.
【図５】同上のダミー電極へのマイクロバンプ法による
金属の溶着状態を示す正面図である。FIG. 5 is a front view showing a state in which a metal is welded to the dummy electrode by the micro bump method.
【図６】ダミー電極を分散させて設けた状態を示す平面
図である。FIG. 6 is a plan view showing a state in which dummy electrodes are dispersed and provided.
【図７】従来例の平面図である。FIG. 7 is a plan view of a conventional example.
3 識別部 3 Identification part
Claims (2)
された半導体装置において、 前記ワイヤボンディングの手段による金属の溶着の有無
の状態が識別符号となる識別部が設けられたことを特徴
とする半導体装置。1. A semiconductor device, in which a wafer is divided and wire-bonded, is provided with an identification portion whose identification code indicates whether or not a metal is welded by the wire-bonding means.
を組み合わせた２進法で表示されたことを特徴とする請
求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the identification portion is displayed in a binary system that combines the states of whether or not metal is welded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6117313A JPH07326552A (en) | 1994-05-31 | 1994-05-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6117313A JPH07326552A (en) | 1994-05-31 | 1994-05-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07326552A true JPH07326552A (en) | 1995-12-12 |
Family
ID=14708665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6117313A Withdrawn JPH07326552A (en) | 1994-05-31 | 1994-05-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07326552A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0896288A2 (en) * | 1997-08-05 | 1999-02-10 | Daimler-Benz Aktiengesellschaft | Identification of industrial products or their components |
| KR19990041909A (en) * | 1997-11-25 | 1999-06-15 | 윤종용 | Semiconductor chip |
-
1994
- 1994-05-31 JP JP6117313A patent/JPH07326552A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0896288A2 (en) * | 1997-08-05 | 1999-02-10 | Daimler-Benz Aktiengesellschaft | Identification of industrial products or their components |
| EP0896288A3 (en) * | 1997-08-05 | 2000-02-23 | DaimlerChrysler AG | Identification of industrial products or their components |
| US6087612A (en) * | 1997-08-05 | 2000-07-11 | Daimlerchrysler Ag | Process for marking industrial products or parts |
| KR19990041909A (en) * | 1997-11-25 | 1999-06-15 | 윤종용 | Semiconductor chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010731 |