JPH07321886A - Data reception controller - Google Patents

Abstract

PURPOSE:To speedily perform the echo back processing of received transmission data. CONSTITUTION:When an AT command is transmitted to a communication control part 10, respective character data are received by an AT command receiving part 12, and the data composed of an information bit and a parity bit sandwiched between a start bit and a stop bit are read by a control part 6 as data composed of the information bit. The data read as the information bit are stored in a data buffer after the bit corresponding to the parity bit is corrected to '0' and on the other hand, the start bit and stop bit are added to before and after these data and echoed back from a transmitting part 13 to the transmission source. Since the received transmission data can be transmitted to the transmission source as they are without being discriminated with its transmission format, speedy echo back processing is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reception control device for controlling reception of serial data transmitted by an asynchronous method, and more particularly to echo back control of received data.

[0002]

2. Description of the Related Art Conventionally, for example, in data transmission of an AT command, when a transmission source issues an echo back request for transmission data, the receiving side receives character data "A" and "T" of the AT command received. , The transmission speed and the transmission format are detected, and the received data (data in the area between the start bit and the stop bit) is echoed back according to the transmission speed and the transmission format.

The transmission data of the AT command includes start bit (first bit b0), information bit (second bit b1 to eighth bit b7), parity bit (9th bit b8) and stop bit (10th bit) from the beginning. b9) arranged in the order of 10 bits, and the parity bits are (1) even parity, (2) odd parity, (3)
By setting either "0 (space bit)" fixed or (4) "1 (mark bit) fixed", transmission by four types of transmission formats is possible.

The transmission speed is detected from the bit length of the start bit b0 of the character data "A", and the transmission format is a bit arrangement of the information bits and parity bits of the AT command character data "A" and "T". It is determined from the pattern. That is, the bit array of the information bit and the parity bit of the character data “A” is A (b1, b
2, b3, b4, b5, b6, b7, b8) and the bit array of information bits and parity bits of the character data "T" is T (b1, b2, b
3, b4, b5, b6, b7, b8), the transmission format is the bit array [A (b1, b2, b3, b4, b5, b6, b7, b8) | T
(B1, b2, b3, b4, b5, b6, b7, b8)].

When the transmission data is received, the transmission format is discriminated and the reception data (data composed of information bits) is extracted, and the data composed of the information bits is used for communication processing. Further, according to the determined transmission format, a parity bit is added to the data consisting of the information bits to generate data to be echoed back. Then, the data to be echoed back is transmitted to the transmission source with a start bit and a stop bit added before and after.

[0006]

In the above conventional AT command receiving apparatus, the transmission format is determined from the bit array pattern consisting of the information bits and the parity bits of the character data "A" and "T" of the AT command, Since parity bits are added to data consisting of information bits according to the transmission format to generate data to be echoed back, character data "A" and "T" are generated.
The echo back processing cannot be performed until after the reception of, and quick echo back processing is difficult.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a data reception control device capable of quick echo back processing.

[0008]

SUMMARY OF THE INVENTION The present invention receives transmission data of an asynchronous system in which a start bit and a stop bit are added before and after data consisting of an information bit and a parity bit, and the received data is received. In the data reception control device for performing echo back to the transmission source of the information bit, information bit capturing means for capturing the data as data consisting of information bits, and start bits before and after the data captured by the information bit capturing means. It is provided with an echo back data generating means for adding the stop bit to generate the echo back data and a transmitting means for transmitting the generated echo back data to the transmission source (claim 1).

Further, according to the present invention, in the above data reception control device, the bit corresponding to the parity bit of the data taken in by the information bit taking means is "0".
And a data decoding means for decoding the data modified by the data modifying means (claim 2).

The data reception control device may be applied to a data reception control device that receives an AT command (claim 3).

[0011]

According to the present invention, when the transmission data is received, the data consisting of the information bit and the parity bit sandwiched between the start bit and the stop bit is taken in as the data consisting of the information bit. Since the entire data transmitted by adding the parity bit to the data consisting of the information bit to be transmitted from the transmission source is taken in as the data consisting of the information bit transmitted without adding the parity bit, before and after the data. The start bit and the stop bit are directly added and transmitted (echo back) to the transmission source at a predetermined transmission rate.

According to the second aspect of the invention, the data D'acquired as data consisting of information bits.
Has a content different from that of the true data D to be received (data configured by the number of bits smaller by one bit than the data D '), and therefore the parity bit PA of the data D'.
After the bit corresponding to is modified to "0", its contents are decrypted. By correcting the bit corresponding to the parity bit PA to “0”, the decoding result of the data D ′ matches the decoding result of the data D including the information bit and the parity bit, and the information transmitted from the transmission source is normal. To be received.

According to the invention of claim 3, the AT
The command transmission data includes a start bit (first bit b0), an information bit (second bit b1 to eighth bit b7), a parity bit (9th bit b8), and a stop bit (10th bit b9) in this order from the beginning. Arranged one
It consists of 0-bit data. When the AT command is received, information bits (second bit b1 to eighth bit b7) +
Data composed of the parity bit (9th bit b8) is received as 8-bit data D'composed of information bits (2nd bit b1 to 9th bit b8).

The 8-bit data D'is echoed back to the transmission source by adding a start bit and a stop bit before and after it. Further, in the above 8-bit data D ', the bit b8 corresponding to the parity bit is corrected to "0", and the content is decoded. Since the bit b8 is modified to "0", the decoded contents of the 8-bit data D'composed of the bits b1 to b8 match the decoded contents of the 7-bit data D composed of the bits b1 to b7 and are transmitted from the transmission source. Information is received normally.

[0015]

1 is a block diagram of a facsimile apparatus equipped with a data reception control apparatus according to the present invention.

The facsimile device 1 is a G3 type facsimile device capable of transmitting and receiving encrypted data (hereinafter referred to as encrypted communication) and capable of high-speed transmission. Also,
The facsimile machine 1 is a personal computer PC
(Hereinafter referred to as personal computer PC) can be connected externally, and in addition to the normal facsimile function, the above personal computer PC
It is equipped with a personal computer communication function that performs communication processing according to the AT command transmitted from the computer. The facsimile device 1 is not limited to the G3 type, but the
It may be a facsimile of four types or a type corresponding to any standard.

The facsimile apparatus 1 includes a scanner unit 2 for reading an original to be transmitted to a destination facsimile FX, data read by the scanner unit 2 (hereinafter referred to as transmission data), and data transmitted from the facsimile FX (hereinafter referred to as "data").
A printer unit 3 for printing on a recording sheet data such as received data) and data transmitted from the personal computer PC (hereinafter referred to as transmission data), a data processing unit 4 for performing predetermined data processing on the transmission / reception data and transmission data, and a telephone. It is composed of a data transmission section 5 for transmitting the transmission / reception data via the line TC, and a control section 6 for controlling driving of the scanner section 2 to the data transmission section 5.

The control unit 6 includes a communication control unit (data reception control device) 10 having an interface of the RS-232C standard, and the personal computer PC is communicably connected to the facsimile device 1 via the communication control unit 10. It
The interface is not limited to the RS-232C standard interface as long as the personal computer PC is communicably connectable.

The control unit 6 has a data buffer 601 for receiving transmission data transmitted from the personal computer PC.
And a processing program for performing the above-mentioned facsimile function and personal computer communication function, and various processing data (for example, data relating to driving conditions such as the light emission amount of the light source of the scanner unit 2 and the development density of the printer unit 3, a warning). ,
A ROM (Read Only Memory) 602 in which data regarding messages such as operating procedures is recorded, and a RAM (Ra for performing predetermined arithmetic processing in accordance with the above processing program.
ndom Access Memory) 603 is built in.

A communication program capable of interpreting the AT command system is installed in the ROM 602, and the facsimile apparatus 1 is controlled by the AT command transmitted from the personal computer PC.

Further, the facsimile machine 1 includes a ten-key pad,
Operation unit 7 consisting of key switches such as one-touch keys, L
CD (Liquid Crystal Display) or LED (Light Em
It is provided with a display section 8 and a speaker 9 which are ited diodes.

The scanner unit 2 is a CCD (Charge Coupled Dev.
ice) A line image sensor is provided as an image pickup unit and an image processing unit, and the image pickup unit is scanned relative to a document to read the document image line by line in the transport direction (row direction of the document), and the read data Is subjected to predetermined image processing such as level correction, γ correction and A / D conversion, and then output to the data processing unit 4.

The printer unit 3 is irradiated with light from a light emitting unit which converts a modulation signal generated based on the constituent data of an image to be printed (hereinafter referred to as a print image) into laser light and outputs the laser light. A photosensitive section that forms a latent image of a print image by laser light, a developing section that visualizes the latent image of the print image formed on the photosensitive section, and a transfer that transfers the visualized print image to recording paper to form an image. And a fixing unit for fixing the print image transferred and formed on the recording paper.

The data processing unit 4 has a memory 401 for storing data, a compression / expansion circuit 402 for compressing and expanding data, an encryption / plain culture circuit 403 for encrypting transmission data and plain culture of received data. , And a data processing circuit 404 for controlling the above-mentioned compression / decompression of data and encryption / plain-text processing.

The memory 401 is a large-capacity memory capable of storing, for example, about 100 A4 size standard originals, and is for enabling proxy reception, confidential reception, reservation transmission, and the like.

The compression / expansion circuit 402 is a ITU-T (International Telegraph and Telecommunications Union) T.T. The transmission data is compressed and the reception data is decompressed based on the data compression method of the four recommendations. The compression / expansion circuit 402 is, for example, MMR (Modi
fied Modified READ (Relative Element Adress Designa
te)) The transmission and reception data are compressed and expanded by the encoding method. The transmission / reception data may be compressed and decompressed by the MH (Modified Huffman) encoding method or the MR (Modified READ) encoding method.

The encryption / plain culture circuit 403 performs data encryption and plain culture using a preset encryption key. The facsimile apparatus 1 has a cryptographic communication function of encrypting data in a substitutable encryption format and transmitting / receiving it. When the transmission / reception data and the encryption key are input from the data processing circuit 404 for cryptographic communication, the encryption / plaintext circuit 403 converts the transmission data into a code in word units using the encryption key, and Received data encrypted in units is converted to plain text. The encryption key is registered in the encryption key table provided in the RAM 603 in the control section 6 by the user.

The data processing circuit 404 performs predetermined data processing on the transmission / reception data and the transmission data based on the control signal of the control unit 6, and transmits the data or prints out on recording paper.

For example, when transmitting the contents of a document by facsimile, the data processing circuit 404 temporarily stores the data of the document image read by the scanner unit 2 in the memory 401. When the transmission start timing signal is input by the control unit 6, the data processing circuit 404 causes the memory 401
The transmission data is read from and is compressed by the compression / expansion circuit 402 at a predetermined compression rate. Then, the transmission data is encrypted / plain culture circuit 403 according to the encryption instruction from the control unit 6.
The data is encrypted by and output to the data transmission unit 5.

When transmitting the transmission data transmitted from the personal computer PC by facsimile, the transmission data is sent to the data processing circuit 404 via the control unit 6, and the data processing circuit 404 instructs the control unit 6 to perform the encryption. According to the above, the transmission data is encrypted by the encryption / plain culture circuit 403 and then output to the data transmission unit 5.

When performing facsimile reception, the data processing circuit 404 temporarily stores the data received by the data transmission section 5 in the memory 401. When the recording start timing signal is input by the control unit 6, the data processing circuit 404 reads the received data from the memory 401, and the received data is encrypted / plain culture circuit according to the plaintext instruction from the control unit 6. The data is flattened by 403, expanded by a compression / expansion circuit 402 at a predetermined expansion ratio, and then output to the printer unit 3.

When the transmission data transmitted from the personal computer PC is printed out on the recording paper, the transmission data is output to the printer unit 3 via the control unit 6 and the data processing circuit 404.

The data transmission section 5 is a modem (MODEM (mo) that converts digital data into analog data.
(dulator / demodulator)) 501 and an NCU (network control unit) 502 that selects a partner station and performs line connection and the like.

The operation unit 7 is a FAX No. of a transmission partner when performing facsimile transmission. Input, instruction to start / stop facsimile transmission, registration / change / deletion of the encryption key, one-touch key or abbreviated No. Is registered, confidential reception is set, and various other modes and conditions are set.

The display section 8 displays the name of the recipient in FAX transmission, FAX No. , With or without encrypted communication,
Information such as line connection status and transmission status, communication status with personal computer PC, etc. are displayed in textual information, and indicators such as the presence or absence of communication errors, setting mode, received image quality, memory proxy reception and maintenance are displayed. It is something to display. In addition, the speaker 9 gives an alarm and transmits a part of the character information by voice.

The communication control unit 10 controls communication of serial data with the personal computer PC by an asynchronous method.

FIG. 2 is a block diagram of the communication controller 10. The communication control unit 10 includes an RS-232C interface unit 11, an AT command receiving unit 12, and a transmitting unit 1.
3, an address record unit 14 and a reference oscillator 15. The above-mentioned components are driven by the reference clock RCLK (frequency f = 9.8) generated by the reference oscillator 15.
304 MHz).

The RS-232C interface section 1
1 performs level conversion between the signal level of transmission data and the signal level processed in the communication control unit 10.
The AT command receiving unit 12 receives an AT command transmitted from the personal computer PC. Transmitter 13
Is for transmitting predetermined data to the personal computer PC in response to the AT command. Address record section 14
Is an interface to the control unit 6, and transmits transmission data, address data,
Various control signals and interrupt signals are communicated.

The control signal is a data read signal CSD for instructing to read the received data, and a format read signal R for instructing to read the transmission format of the received data.
An FT, an overrun read signal ROR for instructing the reading of an overrun flag indicating the presence or absence of overrun of received data, and a chip select signal are transmitted from the control unit 6 to the communication control unit 10. Further, the interrupt signal INT is a signal indicating reception of the transmission data transmitted from the personal computer PC,
It is transmitted from the communication control unit 10 to the control unit 6.

The interrupt signal INT is transmitted to the control unit 6 each time each character data forming the AT command is received, and the control unit 6 notifies that the character data is received by the interrupt signal INT. Upon recognition, the data read signal CSD and predetermined address data are sent to the communication control unit 10 to read the character data. Each read character data is stored in a predetermined storage area of the data buffer 601.

FIG. 3 is a block diagram of the AT command receiving section. The AT command receiving unit 12 includes a shift register 16, a data latch circuit 17, a format detection circuit 18, a data rising / falling detection circuit 19, a transmission speed detection circuit 20, a sampling clock selection circuit 21, a sampling clock generation circuit 22, and a count. Range setting circuit 2
3, a character data end detection circuit 24, an overrun error detection circuit 25, and an interrupt signal generation circuit 26.

The shift register 16 is a personal computer PC.
The serial transmission data transmitted from is received in character units. The AT command has character data of 10
The start bit ST (first bit
Bit b0), information bit D (second bit b1 to eighth bit b7), parity bit PA (9th bit b8) and stop bit SP (10th bit b9) are arranged in this order (see FIG. 4). . Therefore, the shift register 1
Reference numeral 6 is composed of a 10-bit shift register.

The data latch circuit 17 latches the data DT each time one character of data DT is stored in the shift register 16 and reads it as character data. From the received data DT, the format detection circuit 18 outputs (information bit D + parity bit P
The bit configuration of A) (hereinafter referred to as a transmission format) is detected.

Of the data DT, the data consisting of the above (information bit D + parity bit PA) (hereinafter referred to as 8-bit data) is the data to be substantially transmitted, and the parity of the character data "A" and "T". Four types of transmission formats shown in Table 1 can be selected depending on how the bit PA is set.

[0045]

[Table 1]

Character data is ASCII (American Sta.
ndard Cord for Information Interchange) code, column number I (upper 3 bits) and row number J (lower 4)
It is designed to be specified by a code number (IJ) consisting of bits. The code numbers of the character data “A” and “T” are “A” = (41) and “T” = (54), and when displayed as 7-bit data, A (b1, b2, b3, b4, b5, b6 , b7) ＝ A
(1000001), T (b1, b2, b3, b4, b5, b6, b7) = T
It is (0010101).

Therefore, the 8-bit data is represented by the four types of transmission formats as shown in Table 2.

[0048]

[Table 2]

When the AT command is received, the format detection circuit 18 determines the transmission format F from the bit patterns (see Table 2) of the character data "A" and "T".
(i) Determine (i = 1,2,3,4).

When the interrupt signal INT is input, the control section 6 sends a format read signal RFT to the format detection circuit 18 to read the determination result of the transmission format, and to read the data DT following the character data "T". The data buffer 60 decodes the received information bit D and decodes it according to the transmission format F (i).
1 is stored in a predetermined storage area.

On the other hand, when the echo back of the data DT is requested from the personal computer PC, the control unit 6 does not discriminate the transmission format by the format detection circuit 18, but the above-mentioned data DT by the predetermined reception format described later. Is received and the data DT is echoed back to the personal computer PC as it is, and data equivalent to the data consisting of the information bit DT of the received data DT is stored in a predetermined storage area of the data buffer 601.

When there is a request for echo back, the transmission format F (i) of the received data DT is not discriminated in order to quickly echo back the data DT. As shown in Table 2 above, there are four types of transmission formats F (i), and the transmission format F of the received data DT is
To determine (i), it is necessary to receive character data of both "A" and "T" and determine the transmission format F (i) from the bit pattern of 8-bit data of both character data. Therefore, after receiving the data DT, the data D
It takes a relatively long time before the echo back of T becomes possible.

In this embodiment, the transmission format F (i) of the received data DT is not discriminated, and the data DT concerned is not discriminated.
Is transmitted to the personal computer PC as it is to speed up the echo back.

FIG. 5 is a flow chart of data reception control when echo back is requested.

When the communication control unit 10 receives the AT command, the interrupt signal generation circuit 26 sends an interrupt signal INT to the control unit 6 of the facsimile apparatus 1 (step S1). The control unit 6 recognizes the reception of the data DT from the personal computer PC by the interrupt signal INT, and the communication control unit 1
The data read signal CSD is sent to
Is read (step S2).

The reading of the data DT is performed based on the reception format shown in FIG. In this reception format, (information bit D + parity bit P of data DT)
The data composed of A) is treated as 8-bit data composed of information bits. By treating all 8 bits as information bits in this manner, the determination of the transmission format F (i) becomes unnecessary, and a start bit ST and a stop bit SP are directly added before and after the 8-bit data, and the personal computer P
It is possible to echo back to C.

Then, it is judged whether or not the data DT is the leading character data "A" (step S3), and if the data DT is the leading character data "A" (step S).
3), the transmission rate is determined by detecting the bit length of the start bit ST of the first character data "A" (step S4), and the determined transmission rate is transmitted as the transmission rate for echo back. It is set in the section 13 (step S5). The details of the method for determining the transmission rate will be described later.

Then, the transmission format is set in the transmission section 13 (step S6). The transmission format is the same as the reception format and is (start bit ST + 8 bit data + stop bit SP).

Subsequently, transmission data for echo back is set based on the transmission format, and the transmission data is transmitted (echo back) from the communication control unit 10 to the personal computer PC (step S7).

Subsequently, the last bit b8 of the 8-bit data (bit corresponding to the parity bit PA) is "0".
After being changed to (step S8), the data buffer 60
It is stored in the predetermined storage area 1 (step S9).

The ninth bit b8 of the data DT is set to "0".
The reason for changing to 8 is to correct the 8-bit data read by the reception format to the correct code number.

FIG. 7 is a diagram showing the bit configurations and code numbers of the character data "A" and "T" received in the reception format.

If there is no request for echo back, the character data "A" and "T" are received in accordance with the predetermined transmission format F (i), so the code number is "A" =
41, "T" = 54, but when there is a request for echo back, the column number of the information bit D is displayed in 4 bits, so the code number of the character data "A" or "T" is transmitted. Different from the case of format F (i).

For example, when the character data "A" and "T" transmitted in the transmission format F (1) are received by the receiving format, the code number of the character data "A" does not change, but the character data "T". Code number is (D4)
Becomes When the character data "A" and "T" transmitted in the transmission format F (2) are received by the receiving format, the code number of the character data "T" does not change, but the code of the character data "A". The number is (C1).

Therefore, by changing the 9th bit b8 to "0" so that the 9th bit b8 is not related to the column number I of the information bit D consisting of 7 bits, the contents of the 8-bit data are originally. It is adapted to match the contents of the 7-bit data.

Returning to FIG. 5, if the received data DT is not the first character data "A" (NO in step S3),
Since the transmission rate and the transmission format have already been set, the process proceeds to step S7 without performing the processes of steps S4 to S6, and the echo back of the data DT is performed.

Returning to FIG. 3, the data rising / falling detection circuit 1
Reference numeral 9 is a circuit for detecting the falling timing and rising timing of the signal level of the data DT.

FIG. 8 is a diagram showing an embodiment of the data fall / rise detection circuit. Data rising / falling detection circuit 19
Is composed of a falling / rising detection circuit 19A that detects the falling and rising timings of the data DT, and a hold circuit 19B that holds the falling and rising timing detection states until reset by the RESET signal. ing.

The rising / falling detection circuit 19A has two D terminals each having a set terminal / PRE and a reset terminal CLR.
-Flip-flop (hereinafter referred to as D-FF) 27, 2
8 and two NAND circuits 31 and 32.

The D-FFs 27 and 28 are connected in cascade, and the data DT received by the D terminal of the preceding D-FF 27 is received.
Is input, and the reference clock RCLK is input to the CLK terminal. Further, the output of the Q terminal of the D-FF 27 in the preceding stage is output to the D terminal of the D-FF 28 in the subsequent stage (hereinafter referred to as Q output).
Is input, and the reference clock RCLK is input to the CLK terminal. In addition, the NAND circuit 31 has a D-FF 28
Output of D-FF27 and the output of / Q terminal of D-FF27 (hereinafter, / Q
(Called output) is input to the NAND circuit 32 and DF
The / Q output of F28 and the Q output of D-FF27 are input.

The CLR terminals and / PRE terminals of the D-FFs 27 and 28 are set to the inactive state (high level).

Then, the NAND circuit 31 outputs a TRIG signal (falling detection pulse) which detects the falling timing of the data DT, and the NAND circuit 32 outputs a pulse signal which detects the rising timing of the data DT. It is like this.

The hold circuit 19B comprises a first hold circuit HD1 for holding the detection of the first falling timing of the data DT and a second hold circuit HD2 for holding the detection of the first rising timing of the data DT. The 1-hold circuit HD1 includes an AND circuit 33 and D-
The second hold circuit HD1 is composed of FF29
It is composed of the ND circuit 34 and the D-FF 30.

AND circuit 33 of the first hold circuit HD1
Output of the NAND circuit 31 (TRIG signal) and D
The Q output of the -FF 29 is input, and the output of the AND circuit 33 is input to the D terminal of the D-FF 29. The NAN of the AND circuit 34 of the second hold circuit HD2 is
The output of the D circuit 32 (rising detection pulse) and the Q output of the D-FF 30 are input, and the output of the AND circuit 34 is the D-FF.
It is input to the D terminal of 30.

UP which holds the detection of the first falling timing of the data DT from the / Q terminal of the D-FF 29
A signal is output, and data DT is output from the Q terminal of D-FF30.
The DOWN signal that holds the detection of the first rising timing of is output.

The CLR terminals of the D-FFs 29 and 30 are set in the inactive state (high level). Also,
The RESET signal is input to the / PRE terminals of the D-FFs 29 and 30, and the / Q of the D-FF 29 is received by the RESET signal.
The output and the Q output of the D-FF 30 are reset.

The RESET signal is a signal for initial resetting each circuit of the AT command receiving section 12, and is input from the control section 6. Since the AT command may have different transmission speed and transmission format for each command, the control unit 6 normally transmits a RESET signal each time the AT command is received, and resets each circuit of the AT command receiving unit 12. .

Next, the data rising / falling detection circuit 19 described above.
The operation will be described with reference to the time chart of FIG.

FIG. 16 shows data D when the first character data “A” and the second character data “T” of the AT command transmitted by the transmission format F (1) are received.
T, TRIG signal, sampling clock SCLK, U
It is a time chart of a P signal, a DOWN signal, a STON signal, a CLR-A signal, and the like.

The Q outputs of the D-FFs 27 and 28 are obtained by latching the D input at the rising edge of the reference clock RCLK, and are delayed from the D input by one pulse of the reference clock RCLK. The / Q output is an inverted signal of the Q output and is delayed from the D input by one pulse of the reference clock RCLK.

When the data DT is at the high level, NA
Since the / Q output of the low level D-FF 27 and the Q output of the high level D-FF 28 are input to the ND circuit 31, the output (TRIG signal) of the NAND circuit 31 is at the high level. In addition, D of the first hold circuit HD1
Since the D input of the -FF 29 is at the high level, the / Q output (UP signal) of the D-FF 29 is held at the low level.

On the other hand, the high level D is applied to the NAND circuit 32.
-Q output of FF27 and / Q of low level D-FF28
Since the output and the input are input, the output of the NAND circuit 32 is also at the high level. In addition, the second hold circuit HD2
Since the D input of the D-FF 30 is at the high level, the Q output (DOWN signal) of the D-FF 30 is held at the high level.

When the data DT falls from the high level to the low level (see FIG. 16), the / Q output of the D-FF 27 input to the NAND circuit 31 is inverted from the low level to the high level, and the D- The Q output of the D-FF 28 is inverted from the high level to the low level with a delay of one pulse of the reference clock RCLK from the inversion timing of the / Q output of the FF 27, whereby the low level pulse signal (TRIG signal) from the NAND circuit 31. ) Is output. The TRIG signal is output every time the data DT falls from the high level to the low level (FIG. 16, TR.
See IG signal).

Further, the TR is added to the first hold circuit HD1.
When the IG signal is input, the TRIG signal is input to the D terminal of the D-FF 29 via the AND circuit 33. TR
The low level of the IG signal is latched and the Q of the D-FF 29 is
When output from the terminal, this Q output is the AND circuit 3 described above.
Since it is fed back to the D terminal of D-FF29 via 3,
The output is held low.

Therefore, the Q output (UP signal) of the D-FF 29 rises from low level to high level in synchronization with the trailing edge of the data DT (see FIG. 16, UP signal). As a result, the UP signal holds this detection state when the falling timing of the start bit ST of the leading character data "A" is detected.

On the other hand, D- input to the NAND circuit 32
The Q output of the FF 27 and the / Q output of the D-FF 28 are inverted in level in synchronization with the falling edge of the data DT.
Since the timing at which the Q output of 27 changes from high level to low level is earlier than the timing at which the / Q output of the D-FF 28 changes from low level to high level, NAN
The output of the D circuit 32 does not change. Therefore, the DOWN signal of the second hold circuit HD2 does not change (FIG. 16, DO
WN signal).

When the data DT rises from the low level to the high level (see FIG. 16), the Q output of the D-FF 27 input to the NAND circuit 32 rises from the low level to the high level and the Q of the D-FF 27 increases. The / Q output of the D-FF 28 falls from the high level to the low level with a delay of one pulse of the reference clock RCLK from the output rising timing, whereby the NAND circuit 32 outputs the low level pulse signal (rising detection signal). Is output.

When the rising detection signal is input to the second hold circuit HD2, the rising detection signal is input to the D terminal of the D-FF 30 via the AND circuit 34. When the low level of the rising detection signal is latched and output from the Q terminal, the Q output (DOWN signal) is output from the AND circuit 3 described above.
Since it is fed back to the D terminal of D-FF30 via 4,
OWN is held low.

Therefore, the DOWN signal falls from the high level to the low level at the rising timing of the data DT (see FIG. 16, DOWN signal). This makes DOWN
The signal is the start bit ST of the first character data "A".
When the rising timing of is detected, this detection state is held.

On the other hand, D- input to the NAND circuit 31
The / Q output of the FF 27 and the Q output of the D-FF 28 are also inverted in level in synchronization with the rising edge of the data DT.
Since the timing at which the / Q output of 27 changes from the high level to the low level is earlier than the timing at which the Q output of the D-FF 28 changes from the low level to the high level, NAN
The output of the D circuit 31 does not change. Therefore, the UP signal of the first hold circuit HD1 does not change (see FIG. 16, UP signal).

Returning to FIG. 3, the transmission speed detection circuit 20 is described.
Is for detecting the transmission rate of the received data DT. Data DT is preset to 300 bps, 600 b
ps, 1200 bps, 2400 bps, 4800 bps, 960
The data is transmitted at any one of seven types of transmission rates of 0 bps and 19200 bps, and is determined by detecting the bit length of the start bit ST of the leading character data “A”.

The transmission rate detection circuit 20 detects the transmission rate by counting the number of clock pulses of the reference clock RCLK included in the start bit ST of the first character data "A".

Transmission speed is N (bps), reference clock RC
When the frequency of LK is f (Hz), the bit length τ of the start bit ST is 1 / N and the pulse width t of the clock pulse of the reference clock RCLK is 1 / f. Therefore,
When the number of clocks of the reference clock RCLK included in the bit length τ is C, C = f / N, so the transmission rate N is calculated by f / C.

The transmission rate N is 300 (bps) to 1920
The transmission speed detection circuit 20 sets the count value C of the clock pulse of the reference clock RCLK to the transmission speed N because the transmission speed is 0 (bps) which is discretely set in advance and corresponds to the count value C on a one-to-one basis. It is output as the detected value of.

FIG. 9 is a diagram showing an embodiment of the transmission rate detection circuit. The transmission speed detection circuit 20 is an IC (Integrat
ed Circuit) composed of 4 4-bit binaries (2
Evolution hexadecimal) The counters 36 to 39 are cascade-connected to form a counting circuit.

The transmission rate detection circuit 20 is a 16-digit binary counter, and the upper 10 digits of the count data are the QC and QD terminals of the counter 37 and the Q of the counters 38 and 39.
It is designed to be output from the A terminal to the QD terminal. The count value C is C = a15 × 2 ¹⁵ + a14 × 2 ¹⁴ + ... + a6
When expressed as x2 ⁶ + a5 x2 ⁵ + ... + a1 x2 ¹ + a0 x2 ⁰ , the QA output to the QD output of the binary counter 39 correspond to a15, a14, a13, and a12, respectively, and the QA output of the binary counter 38. ~ QD output is a11, a10, a
Corresponding to 9, a8, QC output of binary counter 37, Q
The D outputs correspond to a7 and a6, respectively. Therefore, the transmission rate detection circuit 20 outputs the count value C obtained by counting the clock pulses of the reference clock RCLK in units of 64 as count data.

The CLR terminals of the binary counters 36 to 39 are terminals for resetting all outputs, and when set to a low level, the RC terminals and the QA terminals to QD terminals are reset to a low level. The RESET signal sent from the control unit 6 is input to each CLR terminal.

The LOAD terminals of the binary counters 36 to 39 are terminals for controlling the output states of the QA terminal to QD terminal, and when set to a high level, the count data is output from the QA terminal to QD terminal. The LOAD terminal is set to high level.

The CLK terminals of the binary counters 36 to 39 are terminals to which clocks to be counted are input,
The reference clock RCLK is input. The ENT terminal and the ENP terminal of the binary counters 36 to 39 are
This is a terminal for controlling the counting operation of the reference clock RCLK.

When the ENT terminal and the ENP terminal are set to the high level, the counting becomes possible and the C
The count value of the clock pulse of the reference clock RCLK input from the LK terminal is output from the QA terminal to the QD terminal.

A logical product signal of the data DT, the UP signal output from the data rising / falling detection circuit 19 and the DOWN signal is input to the ENP terminal by the AND circuit 35. The AND circuit 35 detects the start bit ST of the character data "A" of the AT command and outputs the control signal ENP for counting the reference clock RCLK only during the period of the start bit ST.
Since the start bit ST is a low level signal, the data DT is inverted in level by the inverter 40 and input to the AND circuit 35.

The ENT terminal of the binary counter 36 is set to the high level, and the E of the binary counters 37 to 39 is set.
An output signal of the preceding RC terminal (hereinafter referred to as RC output) is input to the NT terminal.

RC output becomes high level when all outputs of QA output to QD output become high level (when count value becomes 15).
It is an output that becomes a high level, and is an output indicating a carry of binary-coded hexadecimal (overflow). The four binary counters 36 to 39 are cascaded so that the RC output of the front stage is input to the ENT terminal of the rear stage, whereby the reference clocks RCLK are 1/16 and 1/16 ² at the binary counters 37 to 39, respectively. , 1/16 ⁴ .

With the above configuration, when the character data "A" at the beginning of the AT command is received, the AND circuit 35 causes the binary counters 36 to 39 to be at the high level only during the start bit ST of the character data "A". The ENP signal is input (see FIG. 16, ENP signal), and the number of clock pulses of the reference clock RCLK generated during this period is counted. Then, this count data is input to the sampling clock selection circuit 21 as transmission speed data.

When the AT command character data "A" is received by the AT command receiving unit 12, the transmission speed is detected by the transmission speed detecting circuit 20 and all the characters that compose the AT command based on the transmission speed are detected. Data is received.

When the reception of all the character data forming the AT command is completed, the control section 6 sends a RESET signal to the AT command receiving section 12 to reset the count value of the transmission rate detecting circuit 20 and When the character data "A" of the AT command is received, the transmission rate is detected again by the transmission rate detection circuit 20. That is, the transmission speed of the AT command is detected every time the character data "A" of the AT command is received.

By the way, in the data communication by the AT command between the facsimile apparatus 1 and the personal computer PC, A
A facsimile mode of CLASS1 (hereinafter referred to as CLASS1 communication mode) is set by the T command, and data communication is performed in the CLASS1 communication mode.

In the CLASS1 communication mode, the AT command and the command not starting with “AT” are mixed and transmitted from the personal computer PC to the communication control unit 10.
Since the transmission speed is fixed to 19200 (bps) in the SS1 communication mode, for example, by holding the transmission speed detected by the AT command that sets the CLASS1 communication mode, or for commands that do not start with “AT” By holding the transmission rate detected by the AT command immediately before the command, the AT command receiving unit 12 can receive a command that does not start with “AT”.

FIG. 10 shows CLAS using the AT command.
It is a figure which shows an example of the communication procedure of S1 communication.

In FIG. The AT command “AT + FCCLASS = 1” of (4) is a command for instructing communication by CLASS 1, and No. The AT command “AT + FCCLASS = 0” in (11) is a command for instructing cancellation of communication by CLASS1.

No. Communication (1) to (4) and No. In the communication after (12), the transmission speed may differ depending on the command. Communication from (5) to (11) is CLASS
Since the communication is in one communication mode, each command is
19 regardless of whether the command starts with "AT"
Communication is performed at a transmission rate of 200 (bps).

In the CLASS1 communication mode,
When the AT command “AT + FCPASS = 1” is received and the transmission speed is detected from the AT command, the sending of the RESET signal to the communication control unit 10 is prohibited, and the AT command “AT + FCPASS = 0” is received. Then, if the prohibition of the transmission of the RESET signal is canceled, the No. The communication of (5) to (11) is performed at the transmission rate (= 19200 bps) detected by the AT command “AT + FCCLASS = 1”, and the procedure signal DCS and the training signal TCF which do not start with “AT” also receive the AT command receiving unit 12. It will be possible to receive at.

However, since detecting the transmission rate of the AT command or not detecting it depending on the contents of the AT command as described above complicates the control, the AT command
It is preferable that the transmission rate is always detected for a command, and that the command not starting with "AT" is received at the transmission rate detected by the immediately preceding AT command.

In the CLASS1 communication mode, "A
The type of AT command transmitted immediately before a command that does not start with "T" is specified. For example, in FIG.
Before the procedure signal DCS, be sure to use “A + FTH = 3” A
The T command is transmitted, and the AT command of “AT + FTM = ...” Is always transmitted before the training signal TCF.

Therefore, the contents of the received AT command are analyzed, and if the received AT command is a predetermined AT command, the transmission speed detected by the AT command is held to hold the next AT command. It is possible for the AT command receiving unit 12 to receive a command that does not start with "."

Control of data reception in CLASS 1 communication using the AT command will be briefly described with reference to the flowchart of FIG.

When the AT command is received (step S
10) The controller 6 analyzes the content of the AT command (step S11). Then, the received AT command is "AT + FTH = ...", "AT + FTM =
... ", it is determined whether it is an ATA or a non-final frame procedure signal (step S12), and if the AT command is not one of the above four types of commands, the control unit 6 sends a RESET signal to the communication control unit 10. It is output and the transmission speed detection circuit 20 is reset (step S13).

On the other hand, if the received AT command is any of the above four types of commands, step S13 is skipped, and the RESET signal is not output from the control section 6.

Then, after a predetermined process is performed according to the contents of the received AT command (step S14), the control unit 6 sends "O" to the personal computer PC via the communication control unit 10.
A predetermined response code such as "K" is transmitted (step S1
5) The AT command reception process ends.

In the present embodiment, due to the circuit configuration, when a command is received, the transmission rate detection circuit 20 always operates to detect the transmission rate, and immediately before the command which does not start with "AT". When an AT command is received, a RESET signal is output from the control unit 6 to the communication control unit 10 and the transmission speed detected by the AT command is held even when a command that does not start with the next "AT" is received. However, when the reception of the command immediately before the command that does not start with “AT” is completed, the transmission speed detection circuit 2
While stopping 0 to stop the transmission rate detection operation, a sampling clock SCLK having a predetermined frequency is generated from a sampling clock generation circuit 22 which will be described later, and “AT” is generated.
You may make it receive the command which does not start with.

CLA using AT command as described above
In the data communication in the SS1 communication mode, it is determined whether or not the next command to be transmitted is a command that does not start with “AT” transmitted at the same speed as the AT command, based on the AT command type, and the same speed is used. If it is a command to be transmitted, the command that does not start with the next "AT" at the transmission speed detected by the AT command is received, so regardless of whether the command starts with "AT" or not The command can be received only by the AT command receiving unit 12 for receiving the AT command, and the circuit configuration of the command receiving unit can be simplified.

Returning to FIG. 3, the sampling clock selection circuit 21 outputs a clock selection signal CS having a predetermined transmission rate based on the count data output from the transmission rate detection circuit 20.

As described above, the AT command transmitted from the personal computer PC is 19200 bps, 9600 bps, 48
00bps, 2400bps, 1200bps, 600bps and 3
Transmission is performed at any transmission rate of 00 bps.

The above transmission speeds of 19200 bps and 9600 bps
s, 4800bps, 2400bps, 1200bps, 600bp
s and 300 bps are represented as N0, N1, ..., N6, respectively, and the count values of the clock pulses of the reference clock RCLK corresponding to these are C0, C1, ..., C6, respectively, and the frequency f of the reference clock RCLK is 9. 830
Each transmission rate Ni (i = 0, 1, ..., 4) at 4 MHz
The count value Ci (i = 0, 1, ..., 6) corresponding to 6) is as shown in Table 3.

[0125]

[Table 3]

If the signal input to the DT input of the transmission speed detection circuit 20 is the data DT, the count value C output from the transmission speed detection circuit 20 is the count value Ci shown in Table 3 or its count value. Neighborhood value of Ci Ci '(≈
Ci).

However, the character data "A" is generated due to noise or the like.
Low-level pulse different from the start bit ST of
When input to the T input, a count value C ″ different from the count values Ci and Ci ′ is output from the transmission rate detection circuit 20. Therefore, the count value C of the transmission rate detection circuit 20 is changed to DT. A determination circuit for determining the authenticity of the signal input to the input and a reset circuit for resetting the counting operation of the transmission rate detection circuit 20 when the input signal of the DT input is not the data DT are required.

In this embodiment, as shown in Table 4, all the count values C of the reference clock RCLK have the above transmission rate Ni.
To the count value C output from the transmission speed detection circuit 20.
The clock selection signal CSi (i = 0, 1, ..., 6) is output from the sampling clock selection circuit 21. This eliminates the need for the determination circuit and the reset circuit, and simplifies the transmission speed detection circuit 20.

In Table 4, the boundary value Cki (i = 1, 2, ..., 6) of the count range corresponding to each transmission rate Ni is the count value corresponding to the adjacent transmission rate Ni, N (i + 1). Ci, C (i + 1)
Although the intermediate value Cm (= (Ci + C (i + 1) / 2)) is set, the boundary value Cki is not limited to the intermediate value Cm, and the count values Ci, C (i + Any count value C between 1) can be set to the boundary value Cki.

For example, the transmission rate N0 (= 19200 bps)
And the boundary value Ck1 of the count value C corresponding to the transmission rate N1 (= 9600 bps) is an intermediate value Cm = (C0 + C1) / of the count values C0 (= 512) and C1 (= 1024) corresponding to the transmission rates N0 and N1. Although 2 = 768 is set, an arbitrary count value C of 513 to 1023 can be set as the boundary value Ck1.

[0131]

[Table 4]

FIG. 12 shows an embodiment of the sampling clock selection circuit. Sampling clock selection circuit 21
Is composed of two latch circuits 41 and 42 each composed of an IC and a programmable logic circuit 43. The latch circuits 41 and 42 are connected in parallel, and the input terminals D1 to D8 of the latch circuit 41 are connected to the QC output and QD output of the binary counter 37 of the transmission speed detection circuit 20, the QA output of the binary counter 38, the QB output, and the binary counter. 39
QA output to QD output are input, and the QC output and QD output of the binary counter 39 are input to input terminals D1 and D2 of the latch circuit 42, respectively.

The OC terminals of the latch circuits 41 and 42 are output control terminals.
The D terminal is ready for output. The EN terminal is an enable input terminal, and when set to a high level, the data input to the input terminals D1 to D8 are latched, and these latched data are output from the output terminals Q1 to Q8, respectively. It

The DOWN signal output from the data rising / falling detection circuit 19 is input to the EN terminal, and the reference clock RCLK at the rising timing (see FIG. 16) of the start bit ST of the character data "A" is input. Count data is latched, and this count data is Q1.
It is output from the terminal to the Q8 terminal.

The programmable logic circuit 43 is a circuit for generating the clock selection signal CSi from the count data. Input terminals P1 to P1 of the programmable logic circuit 43
Outputs Q1 to Q8 of the latch circuit 41 are input to P8, and Q of the latch circuit 42 is input to input terminals P9 and P10.
1 output and Q2 output are input respectively.

Q1 terminal of programmable logic circuit 43
The Q6 terminals are respectively the clock selection signals CS0 to CS
6 corresponding to the input terminals P1 to P in accordance with the relationship between the count value C and the clock selection signal CSi shown in Table 4.
A predetermined clock selection signal CSi (i = 0, 1, ..., 6) corresponding to the count data input to 10 is output.

For example (P1, P2, P3, P4, P5, P6, P7, P8, P9, P1
When 0) = (0000001011), since the count value C is 704, the output CS (Q0, Q1, Q2, Q3,
Q4, Q5, Q6) become CS (1000000), and the high-level clock selection signal CS0 is output from the Q1 terminal. Also,
(P1, P2, P3, P4, P5, P6, P7, P8, P9, P10) = (0000001100)
In this case, since the count value C is 768, CS (Q0, Q
1, Q2, Q3, Q4, Q5, Q6) = (0100000) and output terminal Q2
Outputs a clock selection signal CS1.

Returning to FIG. 3, the sampling clock generation circuit 22 operates from the reference clock RCLK to seven types of sampling clocks SCLK corresponding to the transmission rate Ni.
(Frequency fs = 19200Hz, 9600Hz, 4800Hz, 2400Hz, 1200Hz, 6
00Hz, 300Hz) and outputs a predetermined sampling clock SCLK selected by the clock selection signal CS.

FIG. 13 is a diagram showing an embodiment of the sampling clock generation circuit. The sampling clock generation circuit 22 includes four 4-bit binary counters 45 to 48, which are the same as the binary counters 36 to 39 that form the transmission rate detection circuit 20, and a sampling clock selection circuit 21.
The programmable logic circuit 43 and the two programmable logic circuits 49 and 50 which are the same.

In the four binary counters 45 to 48, the RC output of the front stage is the E of the rear stage as in the transmission rate detection circuit 20.
Cascade connection is made so as to be input to the NT terminal, and one is selected from each of the QA terminal to the QD terminal of the binary counter 47.
9200Hz, 9600Hz, 4800Hz, 2400
The sampling clock SCLK of Hz is output, and the sampling clocks SCLK of 1200 Hz, 600 Hz, and 300 Hz are output from the data output QA terminal to QC terminal of the binary counter 48, respectively.

The CLR-A signal output from the character data end position detection circuit 24 described later is input to each CLR terminal of each of the binary counters 45 to 48, and each LOAD terminal is set to a high level. The above CLR
The -A signal is a detection signal of the stop bit SP of each character data (a signal indicating the end of character data), and this CLR-A
The signal causes the sampling clock SCLK to be reset every time the character data ends.

Further, each C of the binary counters 45 to 48
The reference clock RCLK is input to the LK terminal, and each EN
The CONTROL signal output from the count range setting circuit 23 described later is input to the T terminal. This CONTROL signal is a sampling clock SCL.
A signal for controlling the period for generating K controls the operation of the sampling clock generation circuit 22 (frequency division operation of the reference clock RCLK).

The programmable logic circuits 49 and 50 include select terminals S1 to S4, input terminals P1 to P4 and output terminal O.
When a select terminal Si (i = 1,2,3,4) is provided with an UT and is in an active state (high level here), the corresponding input terminal Pi (i = 1,2,3,4) is input. Output signal is output terminal O
It is set to be output from the UT.

The programmable logic circuits 49, 50
The signals output from the respective OUT terminals are input to the OR circuit 51, and the sampling clock SCLK selected via the OR circuit 51 is output to an external circuit.

Select terminal S of programmable logic circuit 49
Clock selection signals CS0 to CS3 output from the sampling clock selection circuit 21 are input to 1 to S4, respectively, and a selection terminal S1 of the programmable logic circuit 50 is input.
The clock selection signals CS4 to CS6 output from the sampling clock selection circuit 21 are input to S3 to S3, respectively.

Further, the QA outputs to Q of the binary counter 47 are applied to the input terminals P1 to P4 of the programmable logic circuit 49.
Programmable logic circuit 5 to which each D output is input
QA of the binary counter 48 to the 0 input terminals P1 to P3
Output to QC output are input respectively.

With the above configuration, for example, the sampling clock selection circuit 21 outputs the clock selection signal CS (1000
000) is input, P of programmable logic circuit 49
The sampling clock SCLK (frequency fs = 19200 Hz) input to one terminal is output from the OUT terminal and output to the count range setting circuit 23 and the character data end position detection circuit 24 via the OR circuit 51.

Further, for example, when the clock selection signal CS (0000100) is input from the sampling clock selection circuit 21, the sampling clock SCLK (frequency fs = 1) input to the P1 terminal of the programmable logic circuit 50 is input.
200 Hz) is output from the OUT terminal and output to the count range setting circuit 23 and the character data end position detection circuit 24 via the OR circuit 51.

Returning to FIG. 3, the count range setting circuit 2
Reference numeral 3 is a circuit for setting the count range of the clock pulse of the sampling clock SCLK. The character data end position detection circuit 24 counts a predetermined number of clock pulses of the sampling clock SCLK and receives the 8th bit b7 (the last bit of the information bit D) and the 10th bit b9 (each bit of the information bit D). And a stop bit SP).

If each character data of the AT command is transmitted from the personal computer PC at exactly fixed time intervals, the sampling clock SCLK having a predetermined frequency is generated in synchronization with the first character data "A". The sampling clock SC for the second and subsequent character data
Although LK can be accurately synchronized, in serial data transmission by the start-stop synchronization system, the start bit ST and the stop bit SP of the data received on the receiving side are referred to and the data is received. Therefore, each character data of the AT command is not always exactly transmitted at a constant time interval.

In this embodiment, each time the character data is received, the sampling clock SCLK is generated in synchronization with the start bit ST of the character data, and the clock pulse of the sampling clock SCLK is counted to stop the character data. When SP (end position of character data) is detected, sampling clock SCL
K is stopped so that the sampling clock SCLK is accurately synchronized with each character data.

FIG. 14 is a diagram showing an embodiment of the count range setting circuit. FIG. 15 is a diagram showing an embodiment of the character data end position detection circuit.

In FIG. 14, the count range setting circuit 2
Reference numeral 3 denotes a first count control circuit 23A that controls the count period of the sampling clock SCLK for the first character data "A" and a second count control circuit 23B that controls the count period of the sampling clock SCLK for the second and subsequent character data. It consists of and.

The first count control circuit 23A has two D
-FF53, 54 and AND circuit 52. The TRIG signal (see FIG. 8) is input to one input of the AND circuit 52, the Q output of the D-FF 53 is input to the other input, and the output of the AND circuit 52 is the D-FF 53.
Is input to the D terminal of. The Q output of the D-FF 53 is the CONTROL signal, which is input to the D terminal of the D-FF 54 and the sampling clock generation circuit 22.

The reference clock RCLK is input to the CLK terminal of the D-FF 53, and the sampling clock SCLK is input to the CLK terminal of the D-FF 54. Also, the CLR terminals of the D-FFs 53 and 54 are set to the inactive state (high level), and the / CRE terminal has the CLR terminal described above.
The -A signal (see FIG. 15) is input.

The second count control circuit 23B includes three D
-FF55, 56, 57, NAND circuit 58 and AND
The circuit 59 has the same circuit configuration as the circuit for detecting the rising timing of the data DT of the data rising / falling detection circuit 19 and the second hold circuit 19B for holding the detection of the rising timing. (See FIG. 8).
That is, the D-FFs 55, 56 and 57 correspond to the D-FFs 27, 22 and 24 of FIG.
AND circuit 59 is the NAND circuit 32 of FIG.
And AND circuit 34.

The UP signal is input to the D input of the D-FF 54, and the reference clock RCLK is input to the CLK terminals of the D-FFs 54 to 57. Also, D-FF5
The CLR-B signal (see FIG. 15) is input to the / PRE terminal of No. 7.

Further, the / Q output of the D-FF 54 (hereinafter referred to as S
T1 signal) and / Q output of D-FF 57 (hereinafter,
(ST2 signal) is input to the OR circuit 60, and the OR
The circuit 60 outputs the STON signal for controlling the generation period of the sampling clock SCLK. The sampling clock SCLK is counted during the high level period of the STON signal.

In FIG. 15, the character data end position detection circuit 24 detects a binary counter 61 that counts clock pulses of the sampling clock SCLK, and a first count value "9" of the binary counter 61.
The detection signals of the detection circuit 24A, the second detection circuit 24B that detects the count value "7" of the binary counter 61, and the first and second detection circuits 24A and 24B are the count stop control signals CLR-A and C of the sampling clock SCLK.
It is composed of a control signal output circuit 24C for outputting as LR-B.

The binary counter 61 is a 4-bit binary counter 3 which constitutes the transmission rate detection circuit 20.
It is composed of the same binary counters 6 to 39. In addition, the first detection circuit 24A includes two inverters 6
4, 65 and a NAND circuit 62, and the second detection circuit 24B includes an inverter 66 and a NAND circuit 63. The control signal output circuit 24C has two
It is composed of individual OR circuits 67 and 68.

The LOAD terminal and the ENT terminal of the binary counter 61 are set to the high level. The STON signal is input to the ENP terminal,
The sampling clock SCLK is input to the CLK terminal.

The NAND circuit 62 of the first detection circuit 24A receives the QA output to QD output of the binary counter 61. QA output and QD output are directly input, QB output
The output and the QC output are level-inverted and input by the inverters 64 and 65.

The QA output to QD output of the binary counter 61 are also input to the NAND circuit 63 of the second detection circuit 24B. QA to QC outputs are directly input,
The QD output is level-inverted by the inverter 66 and input.

The OR circuit 67 of the control signal output circuit 24C,
The RESET signal is input to one input of 68, the output signal of the NAND circuit 62 is input to the other input of the OR circuit 67, and the output signal of the NAND circuit 68 is input to the other input of the OR circuit 68.

In the above structure, when the TRIG signal is input to the AND circuit 52 of the count range setting circuit 23,
The TRIG signal is input to the D terminal of the D-FF 53, and the Q output (CONTROL signal) of the D-FF 53 is inverted to the low level. That is, the low-level CONTROL signal is output at the falling timing of the start bit ST of the data DT (see FIG. 16). This low level Q output is passed through the AND circuit 52 to the D-FF5.
Since it is fed back to the D terminal of No. 3, the Q output (CONTROL signal) of the D-FF 53 is input until the CLR-A signal is input (until the stop bit SP is detected).
Holds low.

When the Q output of the D-FF 53 falls from the high level to the low level, the D-FF 54 latches the D input (low level) at the rising timing of the sampling clock SCLK, and the / Q terminal of the D-FF 54. The ST1 signal output from the above is inverted from the low level to the high level, and the high level is held until the CLR-A signal is input. That is, the first rising timing of the sampling clock SCLK (see FIG. 16)
Outputs a high-level ST1 signal.

On the other hand, when the UP signal rises from the low level to the high level, the D-FFs 54 and 56 and the NAND circuit 58 detect the rising timing of the UP signal,
A low-level pulse signal is output from the NAND circuit 58. When the NAND circuit 58 outputs the pulse signal, the / Q output (ST2 signal) of the D-FF 57 is inverted from the high level to the low level, and the low level is maintained until it is reset by the CLR-B signal. To be done. That is, the high-level ST2 signal is output at the falling timing of the leading character data "A" (see FIG. 16).

Therefore, when the first character data "A" is received, the STON signal is the start bit S.
When the character data of the second and subsequent characters is received by inverting the low level to the high level at the falling timing of T (see FIG. 16), the low level is output at the first rising timing of the sampling clock SCLK (see FIG. 16). Invert from level to high level. As a result, for the first character data “A”, the sampling clock SCLK
Counting is started from the first clock pulse of the sampling clock SCLK and the first clock pulse of the sampling clock SCLK is not counted for the second and subsequent characters.
Counting starts from the second clock pulse.

When a high-level STON signal is input to the character data end position detection circuit 24, the binary counter 61 starts counting clock pulses of the sampling clock SCLK, and when the count value reaches "9", the binary counter A 4-bit signal “1001” is output from the QA terminal to QD terminal 61.

Since the QB output and the QC output are inverted to "1" by the inverters 64 and 65, the 4-bit signal "1111" is input to the NAND circuit 62, and the NAND circuit 62 detects the high level. The signal is output. Then, this detection signal is output as the count stop control signal CLR-A via the OR circuit 67, input to the CLR terminal of the binary counter 61, and the binary counters 45 to 45 of the sampling clock generation circuit 22. 48 and the / PRE terminals of the D-FFs 53 and 54 of the count range setting circuit 23. Therefore, the ST1 signal is reset to the low level when the stop bit S of each character data is detected.

When the count value of the clock pulse of the sampling clock SCLK by the binary counter 61 becomes "7", the 4-bit signal "0111" is output from the QA terminal to the QD terminal of the binary counter 61. Since the QD output is inverted to "1" by the inverter 66, the NAND circuit 63 has 4 bits of "1111".
A bit signal is input, and the NAND circuit 68 outputs a high-level detection signal. Then, this detection signal is output as the count stop control signal CLR-B via the OR circuit 68, and the count range setting circuit 2
3 is input to the / PRE terminal of the D-FF 57.

When the RESET signal is input, the RESET signal is also output as the count stop control signals CLR-A and CLR-B.

The count stop control signal CLR-B is
This is to make the start timing of the clock pulse of the sampling clock SCLK different between the first character data "A" and the second and subsequent character data.

The sampling clock SCLK is generated at the rising timing of the start bit ST for the first character data "A", that is, at the start point of the second bit b1 (see FIG. 16), and the second and subsequent characters. The character data is generated at the falling timing of the start bit ST (see FIG. 16).

Therefore, as shown in FIG. 16, for the character data of the second and subsequent characters, the start bit ST of the character data corresponds to the first clock pulse of the sampling clock SCLK, but for the first character data "A". The first clock pulse of the sampling clock SCLK corresponds to the second bit b1 of the character data and does not correspond to the start bit ST.

Therefore, in this embodiment, the stop bit SP can be detected by counting 9 clock pulses of the sampling clock SCLK for all the character data, so that the sampling clock SCLK for the leading character data "A" can be detected. Is started from the first clock pulse of the sampling clock SCLK, and counting is started from the second clock pulse of the sampling clock SCLK for the second and subsequent character data.

The count stop control signal CLR-B is
When the reading of the first character data “A” is completed, it is a control signal for stopping the control for starting the counting from the first clock pulse of the sampling clock SCLK. With this count stop control signal CLR-B, the second and subsequent character data Is the sampling clock SCLK 2
The counting is started from the second clock pulse.

That is, when the CLR-B signal is output when the leading character data "A" is read and the ST2 signal is reset to the low level, thereafter, the UP signal that sets the ST2 signal to the high level is the second signal. Since it is not input to the detection circuit 24B (see UP signal in FIG. 16), the STON signal that controls the count range of the clock pulse of the sampling clock SCLK for the second and subsequent character data is substantially the ST1 signal. Therefore, the sampling clock SCLK is applied to the second and subsequent characters.
The control for starting the counting from the first clock pulse of is not performed.

Next, the reception control of the character data transmitted using the time chart shown in FIG. 16 will be briefly described.

When the character data "A" is input to the data rising / falling detection circuit 19, the falling timing of the start bit ST of the character data "A" is detected and TRIG is set.
The signal is output. Further, the UP signal is inverted from the low level to the high level, and the CONTROL signal is inverted from the high level to the low level. Further, the rising timing of the start bit ST of the character data "A" is detected, and the DOWN signal is inverted from the high level to the low level.

When the UP signal is inverted to the high level,
The STON signal output from the count range setting circuit 23 is inverted to the high level, and the sampling clock SCLK
It becomes possible to count the number of clock pulses.

On the other hand, in the transmission speed detection circuit 20, the start bit S is calculated from the UP signal and the DOWN signal.
The period (and period) corresponding to the bit length τ of T is EN
The transmission rate Ni is determined from the number C of clock pulses of the reference clock RCLK included in the start bit ST, which is detected by the P signal. Then, the clock selection signal CS is output at the falling timing of the DOWN signal, and the sampling clock SLK having a predetermined frequency is generated.

When the sampling clock SCLK is generated, the character data end position detection circuit 24 starts counting clock pulses of the sampling clock SCLK. Since the STON signal is at the high level before the sampling clock SCLK is generated, the sampling clock SCLK is counted from the first clock pulse.

When the seventh clock pulse of the sampling SCLK is counted, the character data "A"
The character data end position detection circuit 24 outputs the CLR-B signal at the trailing edge of the last bit of the information bit D, and the ST2 signal is inverted to the low level. Further, when the ninth clock pulse of the sampling SCLK is counted, it is determined that the stop bit SP of the character data “A” has been detected (the character data “A” has finished), and the ninth clock pulse is detected. From the character data end position detection circuit 24 to the CLR at the rising edge of the pulse
-A signal is output, whereby the CONTROL signal is inverted to high level, and the sampling clock SCLK
Is stopped.

Subsequently, the character data "T" is set to the data start /
When input to the fall detection circuit 19, CONTR is generated at the fall timing of the start bit ST of the character data "T".
The OLL signal is inverted to the low level, and the sampling clock SCLK is generated.

When the sampling clock SCLK is generated, the STON signal is inverted from the low level to the high level at the rising timing of the first clock pulse of the sampling clock SCLK, and the sampling clock SC
Counting of LK clock pulses is started. Above S
Since the TON signal becomes high level at the first clock pulse of the sampling clock SCLK, the first clock pulse of the sampling clock SCLK is not counted and the counting is started from the second clock pulse.

When the ninth clock pulse of the sampling SCLK is counted, the character data "T"
Stop bit SP of is detected (character data "T"
Has been completed) and the character data end position detection circuit 24 outputs the CLR-A signal at the rising timing of the ninth clock pulse.
LL signal is inverted to high level and sampling SCLK
Is stopped.

For the character data of the third and subsequent characters, 2
The signal waveform is the same as that of the character data "T" of the character, the sampling clock SCLK is generated at the falling timing of the start bit ST of each character data, and counting is started from the second clock pulse of the sampling clock SCLK. Is started, and when the ninth clock pulse is counted, it is determined that the stop bit SP is detected, and the sampling SCLK is stopped.

When the start bit SP of each character data is detected as described above, the generation of the sampling clock SCLK is stopped and the sampling clock SCLK is generated at the falling timing of the start bit ST of the next character data. Therefore, the clock pulse of the sampling clock SCLK is accurately synchronized with each bit of the character data, and each character data can be reliably received.

Further, counting is started from the first clock pulse of the sampling clock SCLK for the first character data "A", and the second clock pulse of the sampling clock SCLK is started for the second and subsequent characters. Since I am trying to start counting from
Regardless of whether or not it is the first character data, the clock pulse of the sampling clock SCLK is counted by one (n-1) (9 in the above embodiment), which is one less than the number n of bits forming the character data. Thus, the stop bit SP of the character data can be detected. This simplifies the counter circuit for the sampling clock SCLK in the character data end position detection circuit 24.

Returning to FIG. 3, in the overrun error detection circuit 25, before the previous character data stored in the shift register 16 is latched (read) by the data latch circuit 17, the subsequent character data is shifted to the subsequent character data. Is a circuit for detecting that the previous character data could not be received (hereinafter referred to as an overrun error) due to the overrun of the subsequent character data.

The overrun error detection circuit 25 is
When the above-mentioned overrun error occurs, an overrun error detection signal is output only for the character data having the overrun error (the overrun detection flag is set).

FIG. 17 is a diagram showing an embodiment of the overrun error detection circuit. The overrun error detection circuit 25 includes an end position detection circuit 25A that detects the end position of the character data and an overrun detection circuit 25B that detects an overrun error.

The end position detection circuit 25A has two D-
The AND circuit 71 outputs a signal (hereinafter referred to as a NINT signal) that detects the end position of the character data. DF
F69 and 70 are connected in cascade, and D-FF6 of the previous stage is connected.
The STON signal is input to the D terminal of 9 and the D-
The Q output of the preceding D-FF 69 is input to the D terminal of the FF 70. The reference clock RCLK is input to the CLK terminals of the D-FFs 69 and 70, and the / Q of the D-FF 69 is input.
The output and the Q output of the D-FF 70 are input to the AND circuit 71. The / PRE terminal and the CLR terminal of the D-FFs 69 and 70 are set to the inactive state (high level).

The overrun detection circuit 25B includes three D-FFs 71 to 74, two AND circuits 75 and 76,
It is composed of a NAND circuit 77, an inverter 78 and an OR circuit 79, and an overrun detection signal OERR is output from the Q terminal of the D-FF 74.

A signal obtained by ANDing the data read signal CSD and the Q output of the D-FF 72 (hereinafter referred to as A signal) is input to the D terminal of the D-FF 73 by the AND circuit 75, and the D-FF 73 outputs D. A signal obtained by inverting the level of the A signal and the NINT signal by the AND circuit 76 by the inverter 78 to the terminal (hereinafter referred to as / NINT signal)
The signal obtained by the logical product of is input.

The reference clock RCLK is input to the CLK terminals of the D-FFs 72 and 73, and the / P of the D-FF 72 is input.
The / NINT signal is input to the RE terminal, and the D-FF
The RESET signal is input to the CLR terminal 72. Further, the CLR terminal and the / PRE terminal of the D-FF 73 are set to the inactive state (high level).

Further, the NIN is made by the NAND circuit 77.
A signal (hereinafter, referred to as a SET signal) obtained by taking a logical product of the T signal and the Q output of the D-FF 73 (hereinafter, referred to as B signal) is input to the / PRE terminal of the D-FF 74, and is reset by the OR circuit 79. A signal (hereinafter referred to as a CLEAR signal) obtained by ORing the signal and the CLR-A signal is D
It is input to the CLR terminal of the -FF74.

The SET signal is a control signal for generating the overrun detection signal OERR (setting the overrun detection flag), and the CLEAR signal stops the overrun detection signal OERR (resets the overrun detection flag). Control signal. In addition, D
The D terminal and the CLK terminal of the -FF74 are set to the inactive state (high level).

Next, the operation of the overrun error detection circuit 25 will be described with reference to the time chart of FIG.

FIG. 18 shows the STON signal, N when the character data "T" is overrun when the character data "A", "T", and "E" transmitted continuously are received.
It is a wave form diagram of an INT signal, a CSD signal, a SET signal, an OERR signal, and other related signals.

The CSD signal is composed of each character data "A",
When “T”, “E”, ... Are normally read, the character data is output from the control unit 6 during the transmission interval.
In FIG. 18, since the data read signal CSD (see S1 in the figure) is not output during the transmission interval between the character data “A” and the character data “T”, and the character data “A” is not read, the character data "T" is overrun.

When the stop bit SP of the first character data "A" is detected, the STON signal falls from the high level to the low level, and NIN is set at this fall timing.
A T signal (high-level pulse) is output (FIG. 18,
). Further, this NINT signal is the character data "T",
Each time a stop bit SP of "E", ... Is detected, it is output (see FIG.

When the NINT signal is output, DF
Set signal (/ NINT signal) to / PRE terminal of F72
Is input and the Q output of the D-FF 72 is set to a high level. When the Q output of the D-FF 72 is set to the high level, the data read signal CSD is not input (the data read signal CSD is at the high level), so the output of the AND circuit 75, that is, D- FF7
The D input of 2 is inverted to the high level, and the Q of the D-FF 72 is
The output is held high.

When the data read signal CSD is input to read the second character data "T" (see the figure), the Q output of the D-FF 72 is inverted to the low level. After that, the level of the A signal is alternately inverted at the detection timing of the stop bit SP of the third character data “E” and the input timing of the data read signal CSD (see FIG.

When the Q output of the D-FF 72 is inverted to the high level at the detection timing of the stop bit SP of the character data "A", the output of the AND circuit 76, that is, the D-FF is output at the timing of the NINT signal falling to the low level.
The D input of 73 is inverted from low level to high level, and the Q output (B signal) of the D-FF 73 is inverted from low level to high level.

The output of the AND circuit 76 is inverted to the low level when the Q output of the D-FF 72 is inverted to the low level or the NINT signal is output. Therefore, the output of the D-FF 73 is inverted to the high level. The output momentarily falls to a low level at the detection timing of the stop bit SP of the character data "T" of the second character (see the same figure), and the data read signal CS is read to read the character data "T".
When D is input, it falls to the low level again and is inverted to the high level at the detection timing of the stop bit SP of the third character data "T". Thereafter, the B signal is the same as the A signal in the detection timing of the stop bit SP of the character data "E" of the third character and the data read signal CS.
The levels are alternately inverted at the D input timing.

Since the SET signal is the logical product of the B signal and the NINT signal, it is output at the output timing of the NINT signal only when the stop bit SP of the character data "T" of the second character is detected. The Q output of the D-FF 74, that is, the overrun detection signal OERR is set to the high level (see the same figure).

When the stop bit SP of the character data "E" of the third character is detected, the CLR-A signal becomes O.
Since it is input to the CLR terminal of the D-FF 74 via the R circuit 79, the overrun detection signal OERR is reset to a low level at the detection timing of the stop bit SP of the character data "E" of the third character.

When the character data "E" is also overrun, the data read signal CSD (see S2 in the figure) is not input, so the A signal is the character data "E".
The high level is maintained until the data read signal CSD (see S3 in the same figure) for is input, and the B signal falls to the low level for a moment at the detection timing of the stop bit SP of the character data "E" of the third character. When the data read signal CSD for the character data “E” is input, it is inverted to the low level again.

Therefore, the overrun detection signal OE
The RR is once reset to a low level at the detection timing of the stop bit SP of the character data "E" and then immediately set to a high level, and reset to the low level at the detection timing of the stop bit SP of the fourth character data. To be done. That is, when the overruns occur continuously, the overrun detection signal OERR indicates that the stop bit SP of the character data in which the overrun occurs first.
Is set to a high level at the detection timing of, and is equivalently reset to a low level at the detection timing of the stop bit SP of the character data next to the character data in which the overrun has finally occurred.

If the next character data is stored in the shift register 16 before the character data stored in the shift register 16 is read into the control unit 6 as described above, it is considered that an overrun has occurred and the next character data is stored. When the reception of the following character data is received after the previous character data is read by the control unit 6 after the overrun detection flag is set at the completion of reception (when the stop bit SP is detected), Since the overrun detection flag is automatically reset at the completion of receiving the character data (when the stop bit SP is detected), it is easy to set / reset the overrun detection flag.

Although the communication control unit 10 provided in the facsimile apparatus 1 has been described in the above embodiment, the present invention is not limited to the one provided in the facsimile apparatus 1, and may be, for example, a personal computer or a printer. The present invention can be applied to other communicable devices such as, and a data reception control device such as a modem.

[0214]

As described above, according to the present invention,
In a data reception control device that receives start-stop and stop-bit transmission data before and after an information bit and a parity bit and that performs echo back to the transmission source of the received data,
Since the data composed of the information bit and the parity bit of the received transmission data is received as the data composed of the information bit, the start bit and the stop bit are added before and after the data to perform the echo back to the transmission source. The process of discriminating the transmission format from the received transmission data becomes unnecessary, and the received data can be echoed back quickly.

Further, according to the present invention, the data corresponding to the parity bit of the data consisting of the information bit and the parity bit fetched as the data consisting of the information bit is corrected to "0", and then the data is decoded. Since this is done, this decoding result matches the result of decoding the information bit of the data consisting of the information bit and the parity bit, and the information transmitted from the transmission source can be received normally.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a facsimile device including a data reception control device according to the present invention.

FIG. 2 is a block configuration diagram of a communication control unit (data reception control device).

FIG. 3 is a block configuration diagram of an AT command receiving unit.

FIG. 4 is a diagram showing a bit configuration of each character data of an AT command.

FIG. 5 is a flowchart of reception control of transmission data when echo back is requested.

FIG. 6 is a diagram showing a bit configuration of transmission data received in a reception format.

FIG. 7 is a diagram showing a bit configuration and a code number of character data received in a reception format.

FIG. 8 is a diagram showing an embodiment of a data rising / falling detection circuit.

FIG. 9 is a diagram showing an embodiment of a transmission rate detection circuit.

FIG. 10 is a diagram showing an example of a communication procedure of CLASS 1 communication using an AT command.

FIG. 11 is a flowchart of command reception control in CLASS1 communication using an AT command.

FIG. 12 is a diagram showing an embodiment of a sampling clock selection circuit.

FIG. 13 is a diagram showing an embodiment of a sampling clock generation circuit.

FIG. 14 is a diagram showing an embodiment of a count range setting circuit.

FIG. 15 is a diagram showing an embodiment of a character data end position detection circuit.

FIG. 16 is a time chart of the output of each circuit regarding data reception when character data “A” and “T” are input.

FIG. 17 is a diagram showing an embodiment of an overrun error detection circuit.

FIG. 18 is a time chart for explaining the operation of the overrun error detection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Facsimile apparatus 2 Scanner section 3 Printer section 4 Data processing section 5 Data transmission section 6 Control section 7 Operation section 8 Display section 9 Speaker 10 Communication control section 11 RS-232C interface section 12 AT command receiving section 13 Transmitting section 14 Address record section 15 Reference oscillator 16 Shift register 17 Data latch circuit 18 Data rising / falling detection circuit 19 Format detection circuit 20 Transmission rate detection circuit 21 Sampling clock selection circuit 22 Sampling clock generation circuit 23 Count range setting circuit 24 Character data end position detection Circuit 25 Overrun error detection circuit 26 Interrupt signal generation circuit 27-30, 53-57, 69, 70, 72-74 D
-Flip-flop 31, 32, 58, 62, 63, 77 NAND circuit 33, 34, 35, 52, 59, 71, 75, 76 A
ND circuit 36 to 39, 45 to 48, 61 Binary counter 40, 44, 64 to 66, 78 Inverter 41, 42 Latch circuit 43, 49, 50 Programmable logic circuit 51, 60, 67, 68, 79 OR circuit PC personal computer TC Telephone line FX facsimile

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display area H04N 1/32 AE

Claims (3)

[Claims] 1. A method of receiving start-stop and stop-bit transmission data before and after data consisting of an information bit and a parity bit, and echoing back the received data to a transmission source. In the data reception control device for performing, information bit capturing means for capturing the above data as data consisting of information bits,
Echo back data generating means for generating start back and stop bits before and after the data captured by the information bit capturing means to generate echo back data, and transmission for transmitting the generated echo back data to the transmission source And a data reception control device. 2. The data reception control device according to claim 1, wherein the data correction means corrects a bit corresponding to the parity bit of the data acquired by the information bit acquisition means to "0", and the data modification. And a data decoding means for decoding the data modified by the means. 3. The data reception control device according to claim 1, wherein the transmission data is an AT command.