JP3325703B2 - Data reception control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reception control device for controlling reception of serial data transmitted by an asynchronous system.

[0002]

2. Description of the Related Art Conventionally, as a serial data transmission method, a start bit and a stop bit are added before and after data to be transmitted (7 information bits + 1 parity bit), so that both a transmission side and a reception side are used. A start-stop synchronization method is known in which data can be transmitted at an arbitrary time interval by synchronizing by referring to the start bit and the stop bit.

The data transmission system based on the start-stop synchronization method is adopted for personal computer communication (hereinafter referred to as personal computer communication), and is also used for transmitting AT command character data, which is a standard command system for modem (MODEM) control. Has been adopted.

In receiving the AT command character data, as shown in FIG. 19, the receiving side determines the transmission speed from the bit length τ of the start bit ST of the first character data “A”, and determines the character data “A”. , A sampling clock SCLK for bit synchronization of a predetermined frequency (= 1 / t) corresponding to the transmission speed is generated from the start point of the second bit (the leading bit of the information bit), and the second and subsequent character data “ T ”,...
The sampling clock SCLK is generated from the start point of the above, and the number of clock pulses Ps of the sampling clock SCLK is counted by a predetermined number (here, nine or ten), thereby obtaining each character data "A", "T",. The end position is detected.

[0005]

In serial data transmission by the start-stop synchronization method, the transmission speed is determined from the start bit ST of the first character data "A". Are different from the generation timing of the sampling clock SCLK for the character data “T”,.

That is, for the first character data "A", the sampling clock SC is set at the start of the second bit.
LK is generated, and for the second and subsequent character data "T",..., A sampling clock SCLK is generated from the start point of the start bit ST. This is because the sampling clock SCLK cannot be generated from the start point of the start bit ST for the leading character data “A” because the frequency of the sampling clock SCLK is determined after the detection of the start bit ST. With respect to the character data “T”,... Following the first bit, if the start bit ST and the second bit have the same binary information, the start point of the second bit cannot be detected. To the sampling clock S
This is based on the need to generate the sampling clock SCLK from the start point of the start bit ST in order to synchronize CLK.

Therefore, the sampling clock SCLK
When the end position of the character data is detected by counting the clock pulse Ps, the count number differs between the first character data “A” and the character data “T”,. For example, when the character data is composed of 10 bits (start bit ST + 8 bit data + stop bit SP), the count number of the clock pulse Ps for the first character data “A” is “9”, but the second and subsequent characters are counted. Clock pulse P for character data "T",.
The count number of s is “10”.

When controlling the count of the clock pulse Ps of the sampling clock SCLK by hardware,
A counter K1 for the first character data and a counter K2 for the second and subsequent character data are prepared, and the counters K1 and K2 are set to the first character data "A" and the second and subsequent character data "T",. Although it is conceivable that the switching is performed by the above, the circuit configuration becomes complicated.

On the other hand, the sampling clock SCLK
It is also possible to control the count of the clock pulse Ps in a software manner, but in this case, the load on the data reception processing becomes too large, which is not preferable in controlling the data transmission.

The present invention has been made in view of the above problems, and provides a data reception control device capable of reliably detecting the end position of each character data transmitted by the start-stop synchronization method with a simple configuration. The purpose is to:

[0011]

According to the present invention, the transmission speed is determined from the bit length of the start bit of the first character data of a plurality of character data transmitted by the start-stop synchronization method.
A sampling clock having a predetermined frequency corresponding to the transmission speed is generated in synchronization with each bit of the character data, and the sampling clock is counted by a predetermined number smaller than the number of bits constituting the character data by one. A data reception control device for detecting an end position of character data, comprising: first bit start point detection means for detecting a start point of a second bit of the first character data; A second bit start point detecting means for detecting a start point of a start bit, and when the first character data is received, the sampling clock is generated from a start point of the second bit, and the second and subsequent characters are generated. When data is received, the sampling clock is generated from the start point of the start bit of the character data. And pulling clock generation control means,
When the first character data is received, the counting is started from the first clock pulse of the sampling clock. When the character data of the second character or later is received, the counting is started from the second clock pulse of the sampling clock. And a count start control means.

[0012]

According to the present invention, when the start bit of the first character data is received, the transmission rate is determined from the bit length of the start bit, and the transmission rate is determined from the start point of the bit next to the start bit. A sampling clock having a predetermined frequency based on the sampling clock is generated. Each clock pulse of the sampling clock corresponds to each bit constituting the leading character data, and the clock pulse is counted by a predetermined number which is one less than the number of bits constituting the character data, so that the end position of the leading character data is obtained. Is detected.

When the start point of the start bit is detected for the character data of the second and subsequent characters, the sampling clock is generated, and counting is started from the second clock pulse of the sampling clock. And
When the clock pulse of the sampling clock is counted by the predetermined number, the end position of each character data is detected.

[0014]

FIG. 1 is a block diagram of a facsimile apparatus provided with a data reception control device according to the present invention.

The facsimile apparatus 1 is a G3-type facsimile capable of transmitting and receiving encrypted data (hereinafter referred to as encrypted communication) and capable of high-speed transmission. Also,
The facsimile machine 1 is a personal computer PC
(Hereinafter referred to as PC) can be connected externally. In addition to the normal facsimile function, the PC
It has a personal computer communication function of performing communication processing according to an AT command transmitted from the PC. The facsimile machine 1 is not limited to the G3 type,
It may be a facsimile of four types or a type corresponding to an arbitrary standard.

The facsimile apparatus 1 includes a scanner unit 2 for reading a document to be transmitted to a destination facsimile FX, data read by the scanner unit 2 (hereinafter referred to as transmission data), and data transmitted from the facsimile FX (hereinafter referred to as facsimile FX).
A printer unit 3 for printing, on a recording sheet, data received from the personal computer PC (hereinafter referred to as transmission data), a data processing unit 4 for performing predetermined data processing on the transmission / reception data and transmission data, a telephone It comprises a data transmission unit 5 for transmitting the transmission / reception data via the line TC, and a control unit 6 for controlling the driving of the scanner unit 2 to the data transmission unit 5.

The control unit 6 includes a communication control unit (data reception control device) 10 having an interface of the RS-232C standard. The personal computer PC is communicably connected to the facsimile machine 1 via the communication control unit 10. You.
Note that the interface is not limited to the RS-232C standard interface as long as the personal computer PC can be communicably connected.

The control unit 6 has a data buffer 601 for receiving transmission data transmitted from the personal computer PC.
And a processing program for performing the facsimile function and the personal computer communication function, and various processing data (for example, data relating to driving conditions such as the light emission amount of the light source of the scanner unit 2 and the developing density of the printer unit 3; ,
A ROM (Read Only Memory) 602 in which data relating to messages such as operation procedures are recorded, and a RAM (Ra) for performing predetermined arithmetic processing in accordance with the processing program.
ndom Access Memory) 603 is built-in.

A communication program capable of interpreting the AT command system is mounted on the ROM 602, and the facsimile apparatus 1 is controlled by an AT command transmitted from the personal computer PC.

Further, the facsimile apparatus 1 includes a numeric keypad,
An operation unit 7 including key switches such as one-touch keys, L
CD (Liquid Crystal Display) or LED (Light Em
It has a display unit 8 composed of an itted diode and a speaker 9.

The scanner unit 2 includes an automatic document feeder for feeding a set document, a CCD (Charge Coupled Device).
ice) An image pickup unit comprising a line image sensor and an image processing unit are provided, and the image pickup unit is scanned relative to the original to read the original image in the transport direction (line direction of the original) in line units, and the read data is read. Is subjected to predetermined image processing such as level correction, γ correction, and A / D conversion, and then output to the data processing unit 4.

The printer unit 3 converts the modulated signal generated based on the configuration data of an image to be printed (hereinafter referred to as a print image) into a laser beam, and outputs the laser beam. A photosensitive section for forming a latent image of a printed image by a laser beam, a developing section for revealing the latent image of the printed image formed on the photosensitive section, and a transfer for transferring the revealed printed image to recording paper to form an image And a fixing unit for fixing a print image transferred and formed on recording paper.

The data processing unit 4 includes a memory 401 for storing data, a compression / expansion circuit 402 for compressing and expanding data, and an encryption / plaintext circuit 403 for encrypting transmission data and plaintext reception data. , And a data processing circuit 404 for controlling the compression / expansion and encryption / plaintext processing of data.

The memory 401 is a large-capacity memory capable of storing, for example, about 100 A4 size standard originals, and is capable of performing alternate reception, confidential reception, reservation transmission, and the like.

The compression / decompression circuit 402 is based on T.T. of ITU-T (International Telecommunication Union). It compresses transmission data and decompresses reception data based on the data compression method of the four recommendations. The compression / decompression circuit 402 is, for example, an MMR (Modi
fied Modified READ (Relative Element Adress Designa
te)) Compression and decompression of transmission / reception data by the encoding method. The transmission and reception data may be compressed and decompressed by an MH (Modified Huffman) coding method or an MR (Modified READ) coding method.

The encryption / plaintext circuit 403 performs data encryption and plaintext using a predetermined encryption key set in advance. The facsimile apparatus 1 has an encryption communication function of encrypting and transmitting data in a substitution encryption format. When the transmission / reception data and the encryption key are input from the data processing circuit 404 to perform the encrypted communication, the encryption / plaintext circuit 403 converts the transmission data into a word-by-word code using the encryption key. Converts the received data encrypted in units to plain text. The encryption key is registered in the encryption key table provided in the RAM 603 in the control unit 6 by the user.

The data processing circuit 404 performs predetermined data processing on transmission / reception data and transmission data based on the control signal of the control unit 6, and transmits the data or prints out the data on recording paper.

For example, when facsimile transmission of the document contents is performed, the data processing circuit 404 temporarily stores the data of the document image read by the scanner unit 2 in the memory 401. When a transmission start timing signal is input by the control unit 6, the data processing circuit 404
, And compresses the data at a predetermined compression rate by the compression / decompression circuit 402. Then, in accordance with the encryption instruction from the control unit 6, the transmission data is encrypted / plaintext circuit 403.
After that, the data is output to the data transmission unit 5.

When the transmission data transmitted from the personal computer PC is transmitted by facsimile, the transmission data is sent to the data processing circuit 404 via the control unit 6, and the data processing circuit 404 transmits the encryption instruction from the control unit 6. Then, the transmission data is encrypted by the encryption / plaintext circuit 403 in accordance with, and then output to the data transmission unit 5.

When performing facsimile reception, the data processing circuit 404 temporarily stores the data received by the data transmission unit 5 in the memory 401. When a recording start timing signal is input by the control unit 6, the data processing circuit 404 reads the received data from the memory 401, and in accordance with a plaintext instruction from the control unit 6, the received data is encrypted / encrypted. After plaintext by 403 and decompression by a compression / decompression circuit 402 at a predetermined decompression ratio, the data is output to the printer unit 3.

When the transmission data transmitted from the personal computer PC is printed out on recording paper, the transmission data is output to the printer unit 3 via the control unit 6 and the data processing circuit 404.

The data transmission unit 5 is a modem (MODEM (mo) that converts digital data into analog data.
dulator / demodulator) 501 and an NCU (network control unit) 502 for selecting a partner station, connecting a line, and the like.

The operation unit 7 transmits a FAX No. of a transmission partner when performing facsimile transmission. Input, instructions to start / stop facsimile transmission, registration / change / deletion of the encryption key, one-touch key or abbreviation No. Registration, setting of confidential reception, and setting of various other modes and conditions.

The display unit 8 displays the name of the transmission destination in the facsimile transmission, FAX No. , The presence or absence of encrypted communication,
Various information such as line connection status and transmission status information, communication status with personal computer PC, etc. are displayed as character information, and presence / absence of communication error, setting mode, reception image quality, necessity of memory proxy reception and maintenance, etc. are indicated by indicators. To display. Further, the speaker 9 issues an alarm or transmits a part of the character information by voice.

The communication control unit 10 controls communication of serial data with the personal computer PC by a start-stop synchronization method.

FIG. 2 is a block diagram of the communication control unit 10. As shown in FIG. The communication control unit 10 includes an RS-232C interface unit 11, an AT command receiving unit 12, and a transmitting unit 1.
3. It comprises an address record section 14 and a reference oscillator 15. The above components are driven by a reference clock RCLK (frequency f = 9.8) generated by the reference oscillator 15.
304 MHz).

The above RS-232C interface unit 1
1 performs level conversion between a signal level of transmission data and a signal level processed in the communication control unit 10.
The AT command receiving section 12 receives an AT command transmitted from the personal computer PC. Transmission unit 13
Transmits predetermined data to the personal computer PC in response to the AT command. Address record part 14
Is an interface to the control unit 6, transmission data, address data,
Various control signals and interrupt signals are exchanged.

The control signal includes a data read signal CSD for instructing reading of received data, and a format read signal R for instructing reading of a transmission format of received data.
The control unit 6 transmits the FT, an overrun read signal ROR for instructing reading of an overrun flag indicating the presence or absence of overrun of the received data, a chip select signal, and the like from the control unit 6 to the communication control unit 10. The interrupt signal INT is a signal indicating reception of transmission data transmitted from the personal computer PC.
It is transmitted from the communication control unit 10 to the control unit 6.

The interrupt signal INT is transmitted to the control unit 6 every time each character data constituting the AT command is received, and the control unit 6 confirms that the character data has been received by the interrupt signal INT. The character data is read out by sending a data read signal CSD and predetermined address data to the communication control unit 10 upon recognition. Each read character data is stored in a predetermined storage area of the data buffer 601.

FIG. 3 is a block diagram of the AT command receiving unit. The AT command receiving unit 12 includes a shift register 16, a data latch circuit 17, a format detection circuit 18, a data rise / fall detection circuit 19, a transmission speed detection circuit 20, a sampling clock selection circuit 21, a sampling clock generation circuit 22, a count Range setting circuit 2
3, a character data end detection circuit 24, an overrun error detection circuit 25, and an interrupt signal generation circuit 26.

The shift register 16 is a personal computer PC
This is for receiving serial transmission data transmitted from the PC in character units. The AT command has character data of 10
Start bit ST (first
Bit b0), information bit D (second bit b1 to eighth bit b7), parity bit PA (ninth bit b8), and stop bit SP (tenth bit b9) (see FIG. 4). . Therefore, shift register 1
6 comprises a 10-bit shift register.

Each time the data DT for one character is stored in the shift register 16, the data latch circuit 17 latches the data DT and reads the data DT as character data. From the received data DT, the format detection circuit 18 calculates (information bit D + parity bit P
The bit configuration of A) (hereinafter referred to as a transmission format) is detected.

In the data DT, data (hereinafter, referred to as 8-bit data) consisting of the above (information bit D + parity bit PA) is data to be substantially transmitted, and includes parity of character data "A" and "T". The four types of transmission formats shown in Table 1 can be selected depending on how the bit PA is set.

[0044]

[Table 1]

The character data is ASCII (American Sta.)
ndard Cord for Information Interchange) code, column number I (upper 3 bits) and row number J (lower 4 bits)
Bit) (IJ). The code numbers of the character data “A” and “T” are “A” = (41) and “T” = (54), and when represented by 7-bit data, A (b1, b2, b3, b4, b5, b6 , b7) = A
(1000001), T (b1, b2, b3, b4, b5, b6, b7) = T
(0010101).

Therefore, when the above-mentioned 8-bit data is represented by the above-mentioned four types of transmission formats, Table 2 is obtained.

[0047]

[Table 2]

When the format detection circuit 18 receives the AT command, the format detection circuit 18 determines the transmission format F from the bit patterns of the character data "A" and "T" (see Table 2).
(i) (i = 1, 2, 3, 4) is determined.

When the interrupt signal INT is input, the control section 6 sends a format read signal RFT to the format detection circuit 18 to read the result of discrimination of the transmission format, and outputs the data DT following the character data "T". While decoding according to the transmission format F (i), the data comprising the received information bits D
1 in a predetermined storage area.

On the other hand, when echo back of the data DT is requested from the personal computer PC, the control unit 6 does not determine the transmission format by the format detection circuit 18 but uses the predetermined reception format to be described later. The data DT is echoed back to the personal computer PC as it is, and data equivalent to the data composed of the information bits DT of the received data DT is stored in a predetermined storage area of the data buffer 601.

The reason why the transmission format F (i) of the received data DT is not determined when there is a request for echo back is to quickly echo back the data DT. As shown in Table 2 above, there are four transmission formats F (i), and the transmission format F
To determine (i), it is necessary to receive both character data "A" and "T" and determine the transmission format F (i) from the bit pattern of the 8-bit data of both character data. Therefore, after receiving the data DT, the data D
It takes a relatively long time before the echo back of T becomes possible.

In this embodiment, the transmission format F (i) of the received data DT is not determined, and the data DT is not determined.
Is transmitted as it is to the personal computer PC to speed up the echo back.

FIG. 5 is a flowchart of data reception control when echo back is requested.

When the AT command is received by the communication control unit 10, an interrupt signal INT is transmitted from the interrupt signal generation circuit 26 to the control unit 6 of the facsimile machine 1 (step S1). The control unit 6 recognizes the reception of the data DT from the personal computer PC based on the interrupt signal INT, and the communication control unit 1
0 to the data DT.
Is read (step S2).

The reading of the data DT is performed based on the reception format shown in FIG. In this receiving format, (information bit D + parity bit P) of data DT
The data consisting of A) is treated as 8-bit data consisting of information bits. By treating all 8 bits as information bits in this way, it becomes unnecessary to determine the transmission format F (i), and the start bit ST and the stop bit SP are added directly before and after the 8-bit data to the personal computer P.
It is possible to echo back to C.

Subsequently, it is determined whether or not the data DT is the first character data "A" (step S3), and if the data DT is the first character data "A" (step S3).
(YES at 3), the transmission speed is determined by detecting the bit length of the start bit ST of the leading character data "A" (step S4), and the determined transmission speed is transmitted as the transmission speed for echo back. This is set in the unit 13 (step S5). The details of the method of determining the transmission speed will be described later.

Subsequently, the transmission format is set in the transmission section 13 (step S6). The transmission format is the same as the reception format, which is (start bit ST + 8-bit data + stop bit SP).

Subsequently, transmission data for echo back is set based on the transmission format, and the transmission data is transmitted (echo back) from the communication control unit 10 to the personal computer PC (step S7).

Subsequently, the last bit b8 (bit corresponding to the parity bit PA) of the 8-bit data is "0".
(Step S8), the data buffer 60
1 is stored in the predetermined storage area (step S9).

The ninth bit b8 of the data DT is set to "0".
Is changed to correct the 8-bit data read by the receiving format to a correct code number.

FIG. 7 is a diagram showing the bit configuration and code numbers of character data "A" and "T" received according to the reception format.

If there is no request for echo back, character data "A" and "T" are received in accordance with a predetermined transmission format F (i), so that the code numbers are "A" =
41, "T" = 54, but when there is a request for echo back, the code number of the character data "A" or "T" is transmitted because the column number of the information bit D is indicated by 4 bits. This is different from the case of the format F (i).

For example, when the character data “A” and “T” transmitted in the transmission format F (1) are received in the reception format, the code number of the character data “A” does not change, but the character data “T” Code number is (D4)
Becomes When the character data "A" and "T" transmitted in the transmission format F (2) are received in the reception format, the code number of the character data "T" does not change, but the code of the character data "A" is changed. The number is (C1).

Therefore, by changing the ninth bit b8 to "0" so that the ninth bit b8 does not relate to the column number I of the information bit D consisting of seven bits, the contents of the eight-bit data are 7-bit data.

Returning to FIG. 5, if the received data DT is not the first character data "A" (NO in step S3),
Since the transmission speed and the transmission format have already been set, the process shifts to step S7 to perform echo back of the data DT without performing the processing of steps S4 to S6.

Referring back to FIG. 3, data rising / falling detecting circuit 1
Reference numeral 9 denotes a circuit for detecting the falling timing and the rising timing of the signal level of the data DT.

FIG. 8 is a diagram showing one embodiment of a data fall / rise detection circuit. Data rise / fall detection circuit 19
Is comprised of a fall / rise detection circuit 19A for detecting the falling and rising timings of the data DT, and a hold circuit 19B for holding the falling and rising timing detection states until reset by the RESET signal. ing.

The rise / fall detection circuit 19A has two D terminals each having a set terminal / PRE and a reset terminal CLR.
-Flip-flops (hereinafter referred to as D-FF) 27, 2
8 and two NAND circuits 31 and 32.

The D-FFs 27 and 28 are cascaded, and the data DT received at the D terminal of the preceding D-FF 27 is
And the reference clock RCLK is input to the CLK terminal. Also, the output of the Q terminal of the preceding D-FF 27 is connected to the D terminal of the succeeding D-FF 28 (hereinafter referred to as Q output).
And the reference clock RCLK is input to the CLK terminal. The D-FF 28 is connected to the NAND circuit 31.
Output and the output of the / Q terminal of the D-FF 27 (hereinafter, / Q
) Is input to the NAND circuit 32.
The / Q output of F28 and the Q output of D-FF 27 are input.

The CLR terminal and the / PRE terminal of the D-FFs 27 and 28 are set to an inactive state (high level).

The TRIG signal (falling detection pulse) detecting the falling timing of the data DT is output from the NAND circuit 31, and the pulse signal detecting the rising timing of the data DT is output from the NAND circuit 32. It has become.

The hold circuit 19B comprises a first hold circuit HD1 for holding the detection of the first falling timing of the data DT and a second hold circuit HD2 for holding the detection of the first rising timing of the data DT. The one hold circuit HD1 is connected to the AND circuit 33 and D-
FF29, the second hold circuit HD1 is A
The ND circuit 34 and the D-FF 30 are provided.

AND circuit 33 of first hold circuit HD1
The output (TRIG signal) of the NAND circuit 31 and D
The Q output of the -FF 29 is input, and the output of the AND circuit 33 is input to the D terminal of the D-FF 29. The AND circuit 34 of the second hold circuit HD2 has the NAN.
The output (rising detection pulse) of the D circuit 32 and the Q output of the D-FF 30 are input, and the output of the AND circuit 34 is the D-FF
30 are input to the D terminal.

The UP which holds the detection of the first falling timing of the data DT from the / Q terminal of the D-FF 29
A signal is output, and the data DT is output from the Q terminal of the D-FF 30.
A DOWN signal holding the detection of the first rising timing of is output.

The CLR terminals of the D-FFs 29 and 30 are set to an inactive state (high level). Also,
A RESET signal is input to the / PRE terminals of the D-FFs 29 and 30, and the / Q of the D-FF 29 is input by the RESET signal.
The output and the Q output of the D-FF 30 are reset.

The RESET signal is a signal for initial resetting each circuit of the AT command receiving unit 12 and is input from the control unit 6. Since the AT command may have a different transmission speed and transmission format for each command, the controller 6 normally transmits a RESET signal each time an AT command is received, and resets each circuit of the AT command receiver 12. .

Next, the data rise / fall detection circuit 19
Will be described with reference to the time chart of FIG.

FIG. 16 shows the data D when the first character data "A" and the second character data "T" of the AT command transmitted in the transmission format F (1) are received.
T, TRIG signal, sampling clock SCLK, U
It is a time chart of a P signal, a DOWN signal, a STON signal, a CLR-A signal, and the like.

The Q outputs of the D-FFs 27 and 28 are obtained by latching the D input at the rising edge of the reference clock RCLK, and are each delayed from the D input by one pulse of the reference clock RCLK. The / Q output is an inverted signal of the Q output and is delayed from the D input by one pulse of the reference clock RCLK.

When data DT is at a high level, NA
Since the / Q output of the low-level D-FF 27 and the Q output of the high-level D-FF 28 are input to the ND circuit 31, the output (TRIG signal) of the NAND circuit 31 is at the high level. Also, D of the first hold circuit HD1
Since the D input of the -FF 29 is at the high level, the / Q output (UP signal) of the D-FF 29 is held at the low level.

On the other hand, a high-level D
-Q output of FF27 and / Q of D-FF28 at low level
Since the output is input, the output of the NAND circuit 32 is also at the high level. Also, the second hold circuit HD2
Since the D input of the D-FF 30 is at a high level, the Q output (DOWN signal) of the D-FF 30 is held at a high level.

When the data DT falls from the high level to the low level (see FIG. 16), the / Q output of the D-FF 27 input to the NAND circuit 31 is inverted from the low level to the high level, and the D-FF 27 is turned off. The Q output of the D-FF 28 is inverted from the high level to the low level with a delay of one pulse of the reference clock RCLK from the inversion timing of the / Q output of the FF 27, whereby the NAND circuit 31 outputs a low-level pulse signal (TRIG signal). ) Is output. The TRIG signal is output each time the data DT falls from the high level to the low level (FIG. 16, TR
IG signal).

Further, the TR is applied to the first hold circuit HD1.
When the IG signal is input, the TRIG signal is input to the D terminal of the D-FF 29 via the AND circuit 33. TR
The low level of the IG signal is latched and the Q of the D-FF 29 is
When output from the terminal, this Q output is
3, the signal is fed back to the D terminal of the D-FF 29,
The output is kept at low level.

Therefore, the Q output (UP signal) of the D-FF 29 rises from a low level to a high level in synchronization with the fall of the data DT (see FIG. 16, UP signal). As a result, the UP signal holds this detection state when the fall timing of the start bit ST of the leading character data “A” is detected.

On the other hand, the D-
The levels of the Q output of the FF 27 and the / Q output of the D-FF 28 are also inverted in synchronization with the falling edge of the data DT.
Since the timing at which the Q output of the D-FF 27 is inverted from the high level to the low level is earlier than the timing at which the / Q output of the D-FF 28 is inverted from the low level to the high level, NAN is used.
The output of the D circuit 32 does not change. Therefore, the DOWN signal of the second hold circuit HD2 does not change (FIG. 16, DO
WN signal).

When the data DT rises from the low level to the high level (see FIG. 16), the Q output of the D-FF 27 input to the NAND circuit 32 rises from the low level to the high level, and the Q-level of the D-FF 27 increases. The / Q output of the D-FF 28 falls from the high level to the low level with a delay of one pulse of the reference clock RCLK from the rising edge of the output, whereby the NAND circuit 32 outputs a low-level pulse signal (rising detection signal). Is output.

When the rising detection signal is input to the second hold circuit HD 2, the rising detection signal is input to the D terminal of the D-FF 30 via the AND circuit 34. When the low level of the rise detection signal is latched and output from the Q terminal, the Q output (DOWN signal) is output to the AND circuit 3.
4, the signal is fed back to the D terminal of the D-FF 30.
OWN is held at a low level.

Therefore, the DOWN signal falls from the high level to the low level at the rising timing of the data DT (see the DOWN signal in FIG. 16). This makes DOWN
The signal is the start bit ST of the first character data "A".
When the rise timing is detected, this detection state is held.

On the other hand, D-
The levels of the / Q output of the FF 27 and the Q output of the D-FF 28 are also inverted in synchronization with the rise of the data DT.
Since the timing at which the / Q output of the D-FF 27 is inverted from the high level to the low level is earlier than the timing at which the Q output of the D-FF 28 is inverted from the low level to the high level, NAN is used.
The output of the D circuit 31 does not change. Accordingly, the UP signal of the first hold circuit HD1 does not change (see FIG. 16, UP signal).

Returning to FIG. 3, the transmission speed detection circuit 20
Detects the transmission speed of the received data DT. The data DT is 300 bps, 600 b set in advance.
ps, 1200bps, 2400bps, 4800bps, 960
The transmission is performed at any one of seven transmission speeds of 0 bps and 19200 bps, and is determined by detecting the bit length of the start bit ST of the leading character data “A”.

The transmission speed detecting circuit 20 detects the transmission speed by counting the number of clock pulses of the reference clock RCLK included in the start bit ST of the leading character data "A".

When the transmission speed is N (bps) and the reference clock RC
Assuming that the frequency of LK is f (Hz), the bit length τ of the start bit ST is 1 / N, and the pulse width t of the clock pulse of the reference clock RCLK is 1 / f. Therefore,
Assuming that the number of clocks of the reference clock RCLK included in the bit length τ is C, C = f / N, so that the transmission speed N is calculated by f / C.

The transmission speed N is 300 (bps) to 1920.
0 (bps), which is a discretely set speed, which corresponds to the count value C on a one-to-one basis. Therefore, the transmission speed detection circuit 20 determines the count value C of the clock pulse of the reference clock RCLK as the transmission speed N. Is output as the detection value of.

FIG. 9 is a diagram showing one embodiment of the transmission speed detection circuit. The transmission speed detection circuit 20 is an IC (Integrat
ed Circuit) composed of four 4-bit binaries (2
(Evolutionary hexadecimal) is constituted by a counter circuit formed by cascade-connecting counters 36 to 39.

The transmission speed detection circuit 20 is a 16-digit binary counter. The upper 10 digits of the count data are stored in the QC and QD terminals of the counter 37 and the Q and Q terminals of the counters 38 and 39.
The signals are output from the A terminal to the QD terminal. The count value C is calculated as follows: C = a15 × 2 ¹⁵ + a14 × 2 ¹⁴ +... + A6
Expressed in ^{× 2 6 + a5 × 2 5} + ...... + a1 × 2 1 + a0 × 2 0, respectively QA output ~QD output of the binary counter 39 is a15, a14, a13, correspond to a12, QA output of the binary counter 38 ~ QD outputs are a11, a10, a
QC output of binary counter 37, Q
The D outputs correspond to a7 and a6, respectively. Therefore, the transmission speed detection circuit 20 outputs a count value C obtained by counting the clock pulses of the reference clock RCLK in units of 64 as count data.

The CLR terminals of the binary counters 36 to 39 are terminals for resetting all outputs. When set to low level, the RC terminal and the QA to QD terminals are reset to low level. A RESET signal sent from the control unit 6 is input to each CLR terminal.

The LOAD terminals of the binary counters 36 to 39 are terminals for controlling the output states of the QA terminal to the QD terminal. When set to a high level, count data is output from the QA terminal to the QD terminal. The LOAD terminal is set to a high level.

The CLK terminals of the binary counters 36 to 39 are terminals to which a clock to be counted is input.
The reference clock RCLK is input. The ENT terminal and the ENP terminal of the binary counters 36 to 39 are
This terminal controls the counting operation of the reference clock RCLK.

When the ENT terminal and the ENP terminal are set to a high level, a count is possible and the C
The count value of the clock pulse of the reference clock RCLK input from the LK terminal is output from the QA terminal to the QD terminal.

To the ENP terminal, the data DT by the AND circuit 35 and the logical product signal of the UP signal and the DOWN signal output from the data rising / falling detecting circuit 19 are input. The AND circuit 35 detects the start bit ST of the character data "A" of the AT command and outputs a control signal ENP for counting the reference clock RCLK only during the start bit ST.
Since the start bit ST is a low level signal, the level of the data DT is inverted by the inverter 40 and input to the AND circuit 35.

The ENT terminal of the binary counter 36 is set to the high level, and the E of the binary counters 37 to 39 is set.
An output signal of the preceding RC terminal (hereinafter referred to as RC output) is input to the NT terminal.

When all the outputs QA to QD become high level (when the count value becomes 15), the RC output becomes:
This output is a high-level output and indicates a carry (overflow) of binary hex. Four binary counters 36-39 are cascade-connected as the preceding stage of the RC output is input to the subsequent ENT terminal, thereby the reference clock RCLK binary counter 37-39 are each 1 / 16,1 / 16 ² , 1/16 ⁴ .

With the above configuration, when the head character data "A" of the AT command is received, the AND circuit 35 causes the binary counters 36 to 39 to go to the high level during the period of the start bit ST of the character data "A". The ENP signal is input (see FIG. 16, ENP signal), and the number of clock pulses of the reference clock RCLK generated during this period is counted. Then, the count data is input to the sampling clock selection circuit 21 as transmission speed data.

When character data "A" of the AT command is received by the AT command receiving unit 12, the transmission speed is detected by the transmission speed detecting circuit 20, and all characters constituting the AT command are detected based on the transmission speed. Data is received.

When the reception of all the character data constituting the AT command is completed, a RESET signal is sent from the control section 6 to the AT command receiving section 12, and the count value of the transmission speed detecting circuit 20 is reset. When the character data "A" of the AT command is received, the transmission speed is detected again by the transmission speed detecting circuit 20. That is, each time the character data “A” of the AT command is received, the transmission speed of the AT command is detected.

In data communication between the facsimile machine 1 and the personal computer PC using an AT command, A
The facsimile mode of CLASS1 (hereinafter referred to as CLASS1 communication mode) is set by the T command, and data communication is performed in the CLASS1 communication mode.

In the CLASS1 communication mode, an AT command and a command not starting with “AT” are transmitted to the communication control unit 10 in a mixed manner from the personal computer PC.
In the SS1 communication mode, the transmission speed is fixed at 19200 (bps). For example, by holding the transmission speed detected by an AT command for setting the CLASS1 communication mode, or for a command not starting with "AT" By holding the transmission rate detected by the AT command immediately before the command, the AT command receiving unit 12 can receive a command that does not start with “AT”.

FIG. 10 shows a CLAS using an AT command.
It is a figure showing an example of the communication procedure of S1 communication.

In FIG. The AT command (AT + FCCLASS = 1) of (4) is a command for instructing communication by CLASS1. The AT command (AT + FCCLASS = 0) of (11) is a command for instructing cancellation of communication by CLASS1.

No. The communication of (1) to (4) and No. In the communication after (12), the transmission speed may be different depending on the command. (5) to (11) communication is CLASS
Since the communication is performed in one communication mode, each command is
Regardless of whether the command starts with "AT" or not, 19
Communication is performed at a transmission speed of 200 (bps).

In the CLASS1 communication mode,
When the AT command “AT + FCLASS = 1” is received and the transmission speed is detected from the AT command, transmission of the RESET signal to the communication control unit 10 is prohibited, and the AT command “AT + FCLASS = 0” is received. Then, if the prohibition of the transmission of the RESET signal is released, No. The communication of (5) to (11) is performed at the transmission rate (= 19200 bps) detected by the AT command “AT + FCLASS = 1”, and the procedure signal DCS and the training signal TCF that do not start with “AT” are also sent to the AT command receiving unit 12. It becomes possible to receive.

However, detecting or not detecting the transmission rate of the AT command depending on the contents of the AT command as described above complicates the control.
It is preferable that the transmission rate is always detected for the command, and that the command not starting with "AT" is received at the transmission rate detected by the immediately preceding AT command.

In the CLASS1 communication mode, “A
The type of AT command transmitted immediately before a command not starting with "T" is specified. For example, in FIG.
Before the procedure signal DCS, A of "AT + FTH = 3"
A T command is transmitted, and an AT command of "AT + FTM = ..." is always transmitted before the training signal TCF.

Therefore, the contents of the received AT command are analyzed, and if the received AT command is a predetermined AT command, the transmission rate detected by the AT command is held to thereby transmit the next AT command. "Can be received by the AT command receiving unit 12.

Here, control of data reception in CLASS1 communication using an AT command will be briefly described with reference to the flowchart of FIG.

When an AT command is received (step S
10), the content of the AT command is analyzed by the control unit 6 (step S11). Subsequently, the received AT command is "AT + FTH = ...", "AT + FTM =
.. ", It is determined whether or not the signal is an ATA or non-final frame procedure signal (step S12). If the AT command is not any of the four types of commands, the control unit 6 sends a RESET signal to the communication control unit 10. Then, the transmission speed detection circuit 20 is reset (step S13).

On the other hand, if the received AT command is any of the above four types of commands, step S13 is skipped and the control unit 6 does not output the RESET signal.

Subsequently, after a predetermined process is performed in accordance with the content of the received AT command (step S14), the control unit 6 sends a message "O" to the personal computer PC via the communication control unit 10.
A predetermined response code such as "K" is transmitted (step S1).
5), the AT command receiving process ends.

In this embodiment, when a command is received due to the circuit configuration, the transmission rate detection circuit 20 always operates to detect the transmission rate, and the transmission rate detection circuit 20 detects the transmission rate and immediately before the command that does not start with "AT". When an AT command is received, a RESET signal is output from the control unit 6 to the communication control unit 10, and the transmission rate detected by the AT command is held even when a command that does not start with the next "AT" is received. However, when the reception of the command immediately before the command not starting with "AT" is completed, the transmission speed detection circuit 2
0 is stopped to stop the transmission speed detection operation, and a sampling clock SCLK having a predetermined frequency is generated from a sampling clock generation circuit 22 to be described later to set “AT”.
May be received.

CLA using AT command as described above
In the data communication in the SS1 communication mode, it is determined from the type of the AT command whether or not the next command to be transmitted is a command that does not start with "AT" transmitted at the same speed as the AT command, and determines at the same speed. If the command is a command to be transmitted, a command that does not start with the next “AT” is received at the transmission rate detected by the AT command. Can be received only by the AT command receiving unit 12 for receiving the AT command, and the circuit configuration of the command receiving unit can be simplified.

Returning to FIG. 3, the sampling clock selection circuit 21 outputs a clock selection signal CS of a predetermined transmission speed based on the count data output from the transmission speed detection circuit 20.

As described above, the AT command transmitted from the personal computer PC is 19200 bps, 9600 bps, 48
00 bps, 2400 bps, 1200 bps, 600 bps and 3
It is designed to be transmitted at any transmission speed of 00 bps.

The above transmission speeds of 19200 bps and 9600 bps
s, 4800bps, 2400bps, 1200bps, 600bp
, and 300 bps are represented as N0, N1,..., N6, respectively, and the count value of the clock pulse of the reference clock RCLK corresponding thereto is C0, C1,. 830
Each transmission speed Ni (i = 0, 1,..., 4 MHz)
Table 3 shows count values Ci (i = 0, 1,..., 6) corresponding to 6).

[0124]

[Table 3]

If the signal input to the DT input of the transmission rate detection circuit 20 is data DT, the count value C output from the transmission rate detection circuit 20 is the count value Ci shown in Table 3 or its count value. Neighboring value Ci '(≒
Ci).

However, the character data "A"
A low-level pulse different from the start bit ST of D
When input to the T input, a count value C "different from the count values Ci and Ci 'is output from the transmission rate detection circuit 20. Therefore, the count value C of the transmission rate detection circuit 20 is converted to DT. A discrimination circuit for discriminating the truth of the signal input to the input and a reset circuit for resetting the count operation of the transmission speed detection circuit 20 when the input signal of the DT input is not the data DT are required.

In this embodiment, as shown in Table 4, the transmission speed Ni is applied to all the count values C of the reference clock RCLK.
And a predetermined transmission speed Ni is assigned to the count value C output from the transmission speed detection circuit 20.
The clock selection signal CSi (i = 0, 1,..., 6) is output from the sampling clock selection circuit 21. This eliminates the need for the determination circuit and the reset circuit, and allows the transmission speed detection circuit 20 to be simplified.

In Table 4, the boundary value Cki (i = 1, 2,..., 6) of the count range corresponding to each transmission speed Ni is set to the count value corresponding to the adjacent transmission speed Ni, N (i + 1). Ci, C (i + 1)
Although the intermediate value Cm (= (Ci + C (i + 1) / 2)) is set, the boundary value Cki is not limited to the intermediate value Cm, and the count values Ci, C (i + Any count value C during 1) can be set as the boundary value Cki.

For example, the transmission speed N0 (= 19200 bps)
The boundary value Ck1 of the count value C corresponding to the transmission speed N1 (= 9600 bps) is an intermediate value Cm = (C0 + C1) / of the count values C0 (= 512) and C1 (= 1024) corresponding to the transmission speeds N0 and N1. Although 2 is set to 768, any count value C of 513 to 1023 can be used as the boundary value Ck1.

[0130]

[Table 4]

FIG. 12 shows an embodiment of the sampling clock selection circuit. Sampling clock selection circuit 21
Is composed of two latch circuits 41 and 42 composed of ICs and a programmable logic circuit 43. The latch circuits 41 and 42 are connected in parallel, and the input terminals D1 to D8 of the latch circuit 41 have QC output and QD output of the binary counter 37 of the transmission speed detecting circuit 20, QA output and QB output of the binary counter 38, and a binary counter. 39
The QA output to the QD output of the binary counter 39 are input to the input terminals D1 and D2 of the latch circuit 42, respectively.

The OC terminals of the latch circuits 41 and 42 are output control terminals, and when set to a low level, the QA terminals to Q
The D terminal becomes ready for output. When the EN terminal is an enable input terminal and is set at a high level, data input to the input terminals D1 to D8 are latched, and these latched data are output from the output terminals Q1 to Q8, respectively. You.

The DOWN signal output from the data rising / falling detection circuit 19 is input to the EN terminal, and the DOWN signal of the reference clock RCLK at the rising timing of the start bit ST of the character data “A” (see FIG. 16) is input. The count data is latched, and this count data is
It is output from the terminals Q8 to Q8.

The programmable logic circuit 43 is a circuit for generating a clock selection signal CSi from the count data. Input terminals P1 to P1 of the programmable logic circuit 43
The outputs Q1 to Q8 of the latch circuit 41 are respectively input to P8, and the Q terminals of the latch circuit 42 are input to input terminals P9 and P10.
One output and Q2 output are input.

From the Q1 terminal of the programmable logic circuit 43 to
The Q6 terminals are connected to the clock selection signals CS0 to CS, respectively.
6, the input terminals P1 to P1 according to the relationship between the count value C and the clock selection signal CSi shown in Table 4.
A predetermined clock selection signal CSi (i = 0, 1,..., 6) corresponding to the count data input to 10 is output.

For example, (P1, P2, P3, P4, P5, P6, P7, P8, P9, P1
When (0) = (0000001011), the count value C is 704, so that the outputs CS (Q0, Q1, Q2, Q3,
Q4, Q5, and Q6) become CS (1000000), and a high-level clock selection signal CS0 is output from the Q1 terminal. Also,
(P1, P2, P3, P4, P5, P6, P7, P8, P9, P10) = (0000001100)
In the case of, since the count value C is 768, CS (Q0, Q
1, Q2, Q3, Q4, Q5, Q6) = (0100000) and the output terminal Q2
Outputs a clock selection signal CS1.

Returning to FIG. 3, the sampling clock generation circuit 22 converts seven types of sampling clocks SCLK corresponding to the transmission speed Ni from the reference clock RCLK.
(Frequency fs = 19200Hz, 9600Hz, 4800Hz, 2400Hz, 1200Hz, 6
00Hz, 300 Hz) and outputs a predetermined sampling clock SCLK selected by the clock selection signal CS.

FIG. 13 is a diagram showing one embodiment of the sampling clock generation circuit. The sampling clock generation circuit 22 includes four 4-bit binary counters 45 to 48, which are the same as the binary counters 36 to 39 included in the transmission speed detection circuit 20, and the sampling clock selection circuit 21.
And the same two programmable logic circuits 49 and 50 as the programmable logic circuit 43.

The four binary counters 45 to 48 output the RC output of the preceding stage to the E output of the subsequent stage similarly to the transmission speed detection circuit 20.
The cascade connection is performed so that the signal is input to the NT terminal.
9200Hz, 9600Hz, 4800Hz, 2400
The sampling clock SCLK of 1 Hz is output, and the sampling clock SCLK of 1200 Hz, 600 Hz, and 300 Hz is output from the data output terminals QA to QC of the binary counter 48, respectively.

A CLR-A signal output from a character data end position detection circuit 24 described later is input to each CLR terminal of the binary counters 45 to 48, and each LOAD terminal is set to a high level. The above CLR
The -A signal is a detection signal of the stop bit SP of each character data (a signal indicating the end of character data).
The sampling clock SCLK is reset every time the character data ends by a signal.

Further, each C of the binary counters 45 to 48 is
The reference clock RCLK is input to the LK terminal.
The CONTROL signal output from the count range setting circuit 23 described later is input to the T terminal. This CONTROLL signal is a sampling clock SCL
This signal controls the period during which K is generated, and controls the operation of the sampling clock generation circuit 22 (the frequency division operation of the reference clock RCLK).

The programmable logic circuits 49 and 50 include selection terminals S1 to S4, input terminals P1 to P4 and an output terminal O
When a selection terminal Si (i = 1, 2, 3, 4) becomes active (here, high level), a corresponding input terminal Pi (i = 1, 2, 3, 4) is input. The output signal is output terminal O
It is set to be output from the UT.

The programmable logic circuits 49 and 50
The signal output from each OUT terminal is input to an OR circuit 51, and the sampling clock SCLK selected via the OR circuit 51 is output to an external circuit.

The selection terminal S of the programmable logic circuit 49
Clock selection signals CS0 to CS3 output from the sampling clock selection circuit 21 are input to 1 to S4, respectively.
The clock selection signals CS4 to CS6 output from the sampling clock selection circuit 21 are input to.

The input terminals P1 to P4 of the programmable logic circuit 49 have QA outputs to Q
D outputs are input, respectively, and the programmable logic circuit 5
0 of the binary counter 48 to the input terminals P1 to P3 of 0.
Output to QC output are input.

With the above configuration, for example, the clock selection signal CS (1000
000) is input, the P of the programmable logic circuit 49 is
The sampling clock SCLK (frequency fs = 19200 Hz) input to one terminal is output from the OUT terminal and output to the count range setting circuit 23 and the character data end position detection circuit 24 via the OR circuit 51.

When a clock selection signal CS (0000100) is input from the sampling clock selection circuit 21, for example, the sampling clock SCLK (frequency fs = 1) input to the P1 terminal of the programmable logic circuit 50 is input.
200 Hz) is output from the OUT terminal and output to the count range setting circuit 23 and the character data end position detection circuit 24 via the OR circuit 51.

Referring back to FIG. 3, the count range setting circuit 2
Reference numeral 3 denotes a circuit for setting the count range of the clock pulse of the sampling clock SCLK. The character data end position detecting circuit 24 counts the clock pulse of the sampling clock SCLK by a predetermined number and receives the eighth bit b7 (the last bit of the information bit D) and the tenth bit b9 (each of the information bits D) of the received character data. Stop bit SP).

If each character data of the AT command is transmitted from the personal computer PC at exactly fixed time intervals, a sampling clock SCLK having a predetermined frequency is generated in synchronization with the leading character data "A". And the sampling clock SC for the second and subsequent character data.
The LK can be accurately synchronized. However, in serial data transmission by the start-stop synchronization method, the reception side receives the data by referring to the start bit ST and the stop bit SP of the data received on the receiving side. Therefore, each character data of the AT command is not always transmitted at exactly constant time intervals.

In this embodiment, each time character data is received, a sampling clock SCLK is generated in synchronization with a start bit ST of the character data, and a clock pulse of the sampling clock SCLK is counted to stop the character data. When SP (end position of character data) is detected, sampling clock SCL
K is stopped to accurately synchronize the sampling clock SCLK with each character data.

FIG. 14 is a diagram showing one embodiment of the count range setting circuit. FIG. 15 is a diagram showing an embodiment of a character data end position detection circuit.

Referring to FIG. 14, count range setting circuit 2
Reference numeral 3 denotes a first count control circuit 23A for controlling the count period of the sampling clock SCLK for the leading character data "A" and a second count control circuit 23B for controlling the count period of the sampling clock SCLK for the character data of the second and subsequent characters. It is composed of

The first count control circuit 23A has two D
And FFs 53 and 54 and an AND circuit 52. The TRIG signal (see FIG. 8) is input to one input of the AND circuit 52, the Q output of the D-FF 53 is input to the other input, and the output of the AND circuit 52 is the D-FF 53
Is input to the D terminal. The Q output of the D-FF 53 is the CONTROLLL signal, which is input to the D terminal of the D-FF 54 and is also input to the sampling clock generation circuit 22.

The reference clock RCLK is input to the CLK terminal of the D-FF 53, and the sampling clock SCLK is input to the CLK terminal of the D-FF 54. The CLR terminals of the D-FFs 53 and 54 are set to an inactive state (high level), and the / PRE terminal is connected to the CLR terminal.
-A signal (see FIG. 15) is input.

The second count control circuit 23B has three D
-FF55, 56, 57, NAND circuit 58 and AND
The circuit 59 has the same circuit configuration as the circuit for detecting the rising timing of the data DT of the data rising / falling detecting circuit 19 and the second hold circuit 19B for holding the detection of the rising timing. (See FIG. 8).
That is, the D-FFs 55, 56, and 57 correspond to the D-FFs 27, 22, and 24 in FIG.
And the AND circuit 59 are respectively the NAND circuit 32 of FIG.
And the AND circuit 34.

The UP signal is input to the D input of the D-FF 54, and the reference clock RCLK is input to the CLK terminals of the D-FFs 54 to 57. Also, D-FF5
7, the CLR-B signal (see FIG. 15) is input to the / PRE terminal.

The / Q output of the D-FF 54 (hereinafter referred to as S
T1 signal) and the / Q output of the D-FF 57 (hereinafter, referred to as T1 signal).
ST2 signal) is input to an OR circuit 60,
The circuit 60 outputs an STON signal for controlling the period during which the sampling clock SCLK is generated. The sampling clock SCLK is counted while the STON signal is at a high level.

In FIG. 15, a character data end position detecting circuit 24 includes a binary counter 61 for counting clock pulses of the sampling clock SCLK, and a first counter for detecting a count value “9” of the binary counter 61.
The detection signals from the detection circuit 24A, the second detection circuit 24B that detects the count value “7” of the binary counter 61, and the first and second detection circuits 24A and 24B are used as count stop control signals CLR-A and C for the sampling clock SCLK.
The control signal output circuit 24C outputs the signal as LR-B.

The binary counter 61 is a 4-bit binary counter 3 constituting the transmission speed detection circuit 20.
6 to 39 are constituted by the same binary counter. The first detection circuit 24A includes two inverters 6
4 and 65 and a NAND circuit 62, and the second detection circuit 24B includes an inverter 66 and a NAND circuit 63. Also, the control signal output circuit 24C has 2
And OR circuits 67 and 68.

The LOAD terminal and the ENT terminal of the binary counter 61 are set to a high level. The STON signal is input to the ENP terminal,
The sampling clock SCLK is input to the CLK terminal.

The QA output to the QD output of the binary counter 61 are input to the NAND circuit 62 of the first detection circuit 24A. QA output and QD output are directly input,
The output and the QC output are input with their levels inverted by inverters 64 and 65.

The QA output to the QD output of the binary counter 61 are also input to the NAND circuit 63 of the second detection circuit 24B. QA output to QC output are directly input,
The QD output is input after its level is inverted by the inverter 66.

The OR circuit 67 of the control signal output circuit 24C,
The RESET signal is input to one input of the OR circuit 68, the output signal of the NAND circuit 62 is input to the other input of the OR circuit 67, and the output signal of the NAND circuit 68 is input to the other input of the OR circuit 68.

In the above configuration, when the TRIG signal is input to the AND circuit 52 of the count range setting circuit 23,
The TRIG signal is input to the D terminal of the D-FF 53, and the Q output (CONTROL signal) of the D-FF 53 is inverted to a low level. That is, a CONTROL signal of a low level is output at the falling timing of the start bit ST of the data DT (see FIG. 16). This low-level Q output is supplied to the D-FF5 via the AND circuit 52.
3, the Q output (CONTROL signal) of the D-FF 53 is output until the CLR-A signal is input (until the stop bit SP is detected).
Held at low level.

When the Q output of the D-FF 53 falls from the high level to the low level, the D input (low level) is latched by the D-FF 54 at the rising timing of the sampling clock SCLK, and the / Q terminal of the D-FF 54 Is inverted from low level to high level, and the high level is held until the CLR-A signal is input. That is, the first rising timing of the sampling clock SCLK (see FIG. 16)
Outputs a high-level ST1 signal.

On the other hand, when the UP signal rises from the low level to the high level, the rising timing of the UP signal is detected by the D-FFs 54 and 56 and the NAND circuit 58.
A low-level pulse signal is output from the NAND circuit 58. When the pulse signal is output from the NAND circuit 58, the / Q output (ST2 signal) of the D-FF 57 is inverted from the high level to the low level, and is held at the low level until reset by the CLR-B signal. Is done. That is, a high-level ST2 signal is output at the falling timing of the leading character data “A” (see FIG. 16).

Therefore, when the leading character data "A" is received, the STON signal is set to the start bit S.
At the falling timing of T (see FIG. 16), the signal is inverted from the low level to the high level, and when the character data of the second and subsequent characters is received, the signal rises at the first rising timing of the sampling clock SCLK (see FIG. 16). Invert from level to high level. Thereby, the sampling clock SCLK is applied to the first character data “A”.
The first clock pulse of the sampling clock SCLK is not counted for the character data of the second character and thereafter,
Counting starts from the second clock pulse.

When a high-level STON signal is input to the character data end position detecting circuit 24, the binary counter 61 starts counting clock pulses of the sampling clock SCLK. When the count value becomes "9", the binary counter 61 A 4-bit signal “1001” is output from the QA terminal to the QD terminal 61.

Since the QB output and the QC output are inverted to "1" by the inverters 64 and 65, a 4-bit signal "1111" is input to the NAND circuit 62, and the NAND circuit 62 detects a high level signal. A signal is output. The detection signal is output as the count stop control signal CLR-A via the OR circuit 67 and is input to the CLR terminal of the binary counter 61, and the binary counter 45 to the binary counter 45 of the sampling clock generation circuit 22. 48 and the / PRE terminals of the D-FFs 53 and 54 of the count range setting circuit 23. Therefore, the ST1 signal is reset to a low level when the stop bit S of each character data is detected.

When the count value of the clock pulse of the sampling clock SCLK by the binary counter 61 becomes "7", a 4-bit signal "0111" is output from the QA terminal to the QD terminal of the binary counter 61. Since the QD output is inverted to “1” by the inverter 66, the NAND circuit 63 outputs “4” of “1111”.
A bit signal is input, and a high-level detection signal is output from the NAND circuit 68. Then, this detection signal is output as the count stop control signal CLR-B via the OR circuit 68, and the count range setting circuit 2
3 is input to the / PRE terminal of the D-FF 57.

When the RESET signal is input, the RESET signal is also output as count stop control signals CLR-A and CLR-B.

The count stop control signal CLR-B is
This is for making the count start timing of the clock pulse of the sampling clock SCLK different between the first character data “A” and the second and subsequent character data.

The sampling clock SCLK is generated at the rising timing of the start bit ST for the first character data "A", that is, at the start point of the second bit b1 (see FIG. 16). Are generated at the falling timing of the start bit ST (see FIG. 16).

Therefore, as shown in FIG. 16, for the character data of the second character and thereafter, the first clock pulse of the sampling clock SCLK corresponds to the start bit ST of the character data. The first clock pulse of the sampling clock SCLK corresponds to the second bit b1 of the character data, and does not correspond to the start bit ST.

Therefore, in this embodiment, the sampling clock SCLK is applied to the first character data "A" so that the stop bit SP can be detected by counting nine clock pulses of the sampling clock SCLK for all character data. , The count is started from the first clock pulse, and the count for the second and subsequent character data is started from the second clock pulse of the sampling clock SCLK.

The count stop control signal CLR-B is
When the reading of the first character data "A" is completed, this is a control signal for stopping the control of starting counting from the first clock pulse of the sampling clock SCLK. The count stop control signal CLR-B is used to control the second and subsequent character data. Is 2 of the sampling clock SCLK
The counting is started from the second clock pulse.

That is, when the leading character data "A" is read, the CLR-B signal is output, and when the ST2 signal is reset to a low level, the UP signal for setting the ST2 signal to a high level is thereafter output. Since the signal is not input to the detection circuit 24B (see the UP signal in FIG. 16), the STON signal that controls the count range of the clock pulse of the sampling clock SCLK for the character data of the second and subsequent characters is substantially the ST1 signal. Therefore, the sampling clock SCLK
Is no longer controlled to start counting from the first clock pulse.

Next, reception control of transmitted character data will be briefly described with reference to a time chart shown in FIG.

When character data "A" is input to data rise / fall detection circuit 19, the fall timing of start bit ST of character data "A" is detected, and TRIG
A signal is output. Further, the UP signal is inverted from the low level to the high level, and the CONTROLLL signal is inverted from the high level to the low level. Further, the rising timing of the start bit ST of the character data “A” is detected, and the DOWN signal is inverted from the high level to the low level.

When the UP signal is inverted to a high level,
The STON signal output from the count range setting circuit 23 is inverted to a high level, and the sampling clock SCLK
Clock pulses can be counted.

On the other hand, in the transmission rate detecting circuit 20, the start bit S is obtained from the UP signal and the DOWN signal.
A period corresponding to the bit length τ of T (period with) is EN
The transmission speed Ni is detected from the P signal, and the transmission speed Ni is determined from the number C of clock pulses of the reference clock RCLK included in the start bit ST. Then, the clock selection signal CS is output at the falling timing of the DOWN signal, and the sampling clock SLK having a predetermined frequency is generated.

When the sampling clock SCLK is generated, the character data end position detection circuit 24 starts counting clock pulses of the sampling clock SCLK. Since the STON signal is at a high level before the generation of the sampling clock SCLK, the sampling clock SCLK is counted from the first clock pulse.

When the seventh clock pulse of the sampling SCLK is counted, the character data "A"
The CLR-B signal is output from the character data end position detection circuit 24 at the falling timing of the last bit of the information bit D, thereby inverting the ST2 signal to a low level. When the ninth clock pulse of the sampling SCLK is counted, it is determined that the stop bit SP of the character data “A” has been detected (the character data “A” has ended), and the ninth clock pulse is counted. At the rising edge of the pulse, the character data end position detection circuit 24 outputs the CLR signal.
-A signal is output, whereby the CONTROLLL signal is inverted to a high level, and the sampling clock SCLK
Is stopped.

Subsequently, the character data "T" is
When input to the fall detection circuit 19, the control signal CONTR is output at the fall timing of the start bit ST of the character data "T".
The OLL signal is inverted to a low level, and a sampling clock SCLK is generated.

When the sampling clock SCLK is generated, the STON signal is inverted from the low level to the high level at the rising timing of the first clock pulse of the sampling clock SCLK, and the sampling clock SC
The counting of the LK clock pulse is started. The above S
Since the TON signal goes high at the first clock pulse of the sampling clock SCLK, the first clock pulse of the sampling clock SCLK is not counted, and the counting starts from the second clock pulse.

When the ninth clock pulse of the sampling SCLK is counted, the character data "T"
Is detected (character data "T")
Is completed), and the CLR-A signal is output from the character data end position detection circuit 24 at the rising timing of the ninth clock pulse.
The LL signal is inverted to the high level, and the sampling SCLK
Is stopped.

For character data after the third character, 2
The signal waveform becomes the same as that of the character data "T" of the character, a sampling clock SCLK is generated at the falling timing of the start bit ST of each character data, and counting is performed from the second clock pulse of the sampling clock SCLK. Is started, and when the ninth clock pulse is counted, it is determined that the stop bit SP has been detected, and the sampling SCLK is stopped.

When the start bit SP of each character data is detected as described above, the generation of the sampling clock SCLK is stopped, and the sampling clock SCLK is generated at the falling timing of the start bit ST of the next character data. Therefore, the clock pulse of the sampling clock SCLK is accurately synchronized with each bit of the character data, and each character data can be reliably received.

For the first character data "A", counting starts from the first clock pulse of the sampling clock SCLK, and for character data of the second and subsequent characters, the second clock pulse of the sampling clock SCLK is used. Since we start counting from
Regardless of whether it is the first character data or not, counting the clock pulse of the sampling clock SCLK by one (n-1) (nine in the above embodiment) one less than the number n of bits constituting the character data Thus, the stop bit SP of the character data can be detected. This simplifies the counter circuit for the sampling clock SCLK in the character data end position detection circuit 24.

Returning to FIG. 3, the overrun error detecting circuit 25 outputs the character data after the previous character data stored in the shift register 16 before being latched (read) by the data latch circuit 17. And a circuit for detecting that the previous character data could not be received due to the overrun of the subsequent character data (hereinafter referred to as an overrun error).

The overrun error detection circuit 25 includes:
When the overrun error occurs, an overrun error detection signal is output only for the character data having the overrun error (an overrun detection flag is set).

FIG. 17 is a diagram showing one embodiment of the overrun error detection circuit. The overrun error detection circuit 25 includes an end position detection circuit 25A for detecting an end position of character data and an overrun detection circuit 25B for detecting an overrun error.

The end position detection circuit 25A has two D-
The AND circuit 71 outputs a signal (hereinafter, referred to as a NINT signal) that detects the end position of the character data. DF
F69 and 70 are cascaded, and the D-FF 6
9, the STON signal is input to the D terminal, and the D-
The Q output of the preceding D-FF 69 is input to the D terminal of the FF 70. The reference clock RCLK is input to the CLK terminals of the D-FFs 69 and 70, and the / Q of the D-FF 69
The output and the Q output of the D-FF 70 are input to the AND circuit 71. Note that the / PRE terminal and the CLR terminal of the D-FFs 69 and 70 are set to an inactive state (high level).

The overrun detection circuit 25B includes three D-FFs 71 to 74, two AND circuits 75 and 76,
The D-FF 74 includes an NAND circuit 77, an inverter 78, and an OR circuit 79, and outputs an overrun detection signal OERR from the Q terminal.

A signal obtained by calculating the logical product of the data read signal CSD and the Q output of the D-FF 72 (hereinafter, referred to as A signal) by the AND circuit 75 is input to the D terminal of the D-FF 72, A signal in which the A signal and the NINT signal are inverted in level by an inverter 78 by an AND circuit 76 (hereinafter, referred to as a / NINT signal).
And a signal that has been logically ANDed is input.

The reference clock RCLK is input to the CLK terminals of the D-FFs 72 and 73,
The / NINT signal is input to the RE terminal, and the D-FF
A RESET signal is input to the CLR terminal 72. The CLR terminal and the / PRE terminal of the D-FF 73 are set to an inactive state (high level).

Further, the NIN circuit 77
A signal (hereinafter, referred to as a SET signal) obtained by ANDing the T signal and the Q output (hereinafter, referred to as a B signal) of the D-FF 73 is input to the / PRE terminal of the D-FF 74, and the OR circuit 79 resets the signal. A signal obtained by calculating the logical sum of the CLR-A signal and the CLR-A signal (hereinafter referred to as a CLEAR signal) is a D signal.
-Input to the CLR terminal of FF74.

The SET signal is a control signal for generating an overrun detection signal OERR (setting an overrun detection flag), and the CLEAR signal is for stopping the overrun detection signal OERR (resetting the overrun detection flag). S) control signal. Note that D
The D terminal and the CLK terminal of the FF 74 are set to an inactive state (high level).

Next, the operation of the overrun error detecting circuit 25 will be described with reference to the time chart of FIG.

FIG. 18 shows a STON signal when character data "T" is overrun when continuously transmitting character data "A", "T", and "E".
FIG. 7 is a waveform diagram of an INT signal, a CSD signal, a SET signal, an OERR signal, and other related signals.

The CSD signal is composed of character data “A”,
When “T”, “E”,... Are normally read, they are output from the control unit 6 during the transmission interval of each character data.
In FIG. 18, the data read signal CSD (see S1 in the figure) is not output during the transmission interval between the character data "A" and the character data "T", and the character data "A" is not read. "T" is overrun.

When the stop bit SP of the first character data "A" is detected, the STON signal falls from the high level to the low level.
A T signal (high-level pulse) is output (FIG. 18,
). The NINT signal is composed of character data "T",
It is output each time a stop bit SP of “E”,.

When the NINT signal is output, DF
Set signal (/ NINT signal) to the / PRE terminal of F72
Is input, and the Q output of the D-FF 72 is set to a high level. When the Q output of the D-FF 72 is set to the high level, the data read signal CSD is not input (because the data read signal CSD is at the high level), so the output of the AND circuit 75, that is, D- FF7
2 is inverted to a high level, and the D-FF 72 Q
The output is kept at high level.

When the data read signal CSD is input to read the character data "T" of the second character (see FIG. 17), the Q output of the D-FF 72 is inverted to a low level. Thereafter, the level of the signal A is alternately inverted at the timing of detecting the stop bit SP of the character data "E" of the third character and the timing of inputting the data read signal CSD (see FIG. 4).

When the Q output of the D-FF 72 is inverted to the high level at the timing of detecting the stop bit SP of the character data "A", the output of the AND circuit 76, that is, the D-FF, is output at the timing when the NINT signal falls to the low level.
The D input of the D-FF 73 is inverted from a low level to a high level, and the Q output (B signal) of the D-FF 73 is inverted from a low level to a high level.

The output of the AND circuit 76 is inverted to the low level when the Q output of the D-FF 72 is inverted to the low level or when the NINT signal is output. The output momentarily falls to a low level at the timing of detecting the stop bit SP of the character data "T" of the second character (see FIG. 3), and the data read signal CS reads the character data "T".
When D is input, it falls to low level again and is inverted to high level at the timing of detecting the stop bit SP of the third character data "T". Thereafter, the B signal is the same as the A signal, the detection timing of the stop bit SP of the third character data “E” and the data read signal CS.
The level is alternately inverted at the D input timing.

Since the SET signal is the logical product of the B signal and the NINT signal, it is output at the output timing of the NINT signal only when the stop bit SP of the character data "T" of the second character is detected. The Q output of the D-FF 74, that is, the overrun detection signal OERR is set to a high level (see FIG. 3).

When the stop bit SP of the third character data “E” is detected, the CLR-A signal is
Since the signal is input to the CLR terminal of the D-FF 74 via the R circuit 79, the overrun detection signal OERR is reset to a low level at the timing of detecting the stop bit SP of the third character data "E".

When the character data "E" is also overrun, the data read signal CSD (see S2 in the figure) is not input, so that the A signal is the character data "E".
Is held at a high level until a data read signal CSD (see S3 in the figure) is input, and the B signal falls to the low level momentarily at the timing of detecting the stop bit SP of the character data "E" of the third character. When the data read signal CSD for the character data "E" is input, the signal is inverted to the low level again.

Therefore, the overrun detection signal OE
RR is once reset to a low level at the timing of detecting the stop bit SP of the character data "E", and is immediately set to a high level, and reset to a low level at the timing of detecting the stop bit SP of the fourth character data. Is done. That is, when overruns occur consecutively, the overrun detection signal OERR becomes the stop bit SP of the character data in which the overrun first occurred.
Is set to the high level at the detection timing, and equivalently reset to the low level at the detection timing of the stop bit SP of the character data next to the character data in which the overrun occurred last.

If the next character data is stored in the shift register 16 before the character data stored in the shift register 16 is read into the control unit 6 as described above, it is determined that an overrun has occurred and the next character data is stored. When the reception of the character data is completed (when the stop bit SP is detected), the overrun detection flag is set. Thereafter, after the previous character data is read into the control unit 6, when the next character data is received, the next character data is received. Since the overrun detection flag is automatically reset when the reception of the character data is completed (when the stop bit SP is detected), it is easy to set / reset the overrun detection flag.

In the above embodiment, the communication control section 10 provided in the facsimile apparatus 1 has been described. However, the present invention is not limited to the communication control section provided in the facsimile apparatus 1, and may be, for example, a personal computer or a printer. And other data-communication control devices such as a communicable device and a modem.

[0213]

As described above, according to the present invention,
The transmission speed is determined from the bit length of the start bit of the first character data of the plurality of character data transmitted by the start-stop synchronization method, and a sampling clock having a predetermined frequency according to the transmission speed is synchronized with each bit of the character data. A data reception control device for detecting the end position of each character data by counting the clock pulse of the sampling clock by a predetermined number smaller than the number of bits constituting the character data by one.
For the first character data, a predetermined number of clock pulses are counted from the start of the generation of the sampling clock. For the second and subsequent character data, the sampling clock is generated from the start point of the start bit. Since a predetermined number of clock pulses are counted from the second clock pulse of the sampling clock, the end position of all character data can be detected by counting the same number of clock pulses. The data receiving circuit is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a facsimile apparatus provided with a data reception control device according to the present invention.

FIG. 2 is a block diagram of a communication control unit (data reception control device).

FIG. 3 is a block diagram of an AT command receiving unit.

FIG. 4 is a diagram illustrating a bit configuration of each character data of an AT command.

FIG. 5 is a flowchart of reception control of transmission data when echo back is requested.

FIG. 6 is a diagram illustrating a bit configuration of transmission data received in a reception format.

FIG. 7 is a diagram illustrating a bit configuration and a code number of character data received by a reception format.

FIG. 8 is a diagram showing one embodiment of a data rise / fall detection circuit.

FIG. 9 is a diagram illustrating an embodiment of a transmission rate detection circuit.

FIG. 10 is a diagram showing an example of a communication procedure of CLASS 1 communication using an AT command.

FIG. 11 is a flowchart of command reception control in CLASS1 communication using an AT command.

FIG. 12 is a diagram showing one embodiment of a sampling clock selection circuit.

FIG. 13 is a diagram showing one embodiment of a sampling clock generation circuit.

FIG. 14 is a diagram showing one embodiment of a count range setting circuit.

FIG. 15 is a diagram showing one embodiment of a character data end position detection circuit.

FIG. 16 is a time chart of output of each circuit regarding data reception when character data “A” and “T” are input.

FIG. 17 is a diagram illustrating an embodiment of an overrun error detection circuit.

FIG. 18 is a time chart for explaining the operation of the overrun error detection circuit.

FIG. 19 is a time chart for explaining a method of detecting the end position of character data in a conventional start-stop synchronous serial data transmission.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Facsimile apparatus 2 Scanner part 3 Printer part 4 Data processing part 5 Data transmission part 6 Control part 7 Operation part 8 Display part 9 Speaker 10 Communication control part 11 RS-232C interface part 12 AT command reception part 13 Transmission part 14 Address record part 15 Reference oscillator 16 Shift register 17 Data latch circuit 18 Data rise / fall detection circuit 19 Format detection circuit 20 Transmission speed detection circuit 21 Sampling clock selection circuit 22 Sampling clock generation circuit 23 Count range setting circuit 24 Character data end position detection Circuit 25 Overrun error detection circuit 26 Interrupt signal generation circuit 27 to 30, 53 to 57, 69, 70, 72 to 74 D
-Flip-flops 31, 32, 58, 62, 63, 77 NAND circuits 33, 34, 35, 52, 59, 71, 75, 76A
ND circuit 36 to 39, 45 to 48, 61 Binary counter 40, 44, 64 to 66, 78 Inverter 41, 42 Latch circuit 43, 49, 50 Programmable logic circuit 51, 60, 67, 68, 79 OR circuit PC Personal computer TC Telephone line FX facsimile

Claims (1)

(57) [Claims] A transmission speed is determined from a bit length of a start bit of a first character data of a plurality of character data transmitted by a start-stop synchronization method, and a sampling clock of a predetermined frequency according to the transmission speed is determined. A data reception control device which generates the data in synchronization with each bit and counts the sampling clock by a predetermined number which is one less than the number of bits constituting the character data, thereby detecting the end position of each character data. First bit start point detecting means for detecting the start point of the second bit of the first character data, and second bit start point detecting means for detecting the start point of the start bit of the second and subsequent character data. When the first character data is received, the sampling clock is generated from the starting point of the second bit. A sampling clock generation control means for generating the sampling clock from a start point of a start bit of the character data when character data of a second character or later is received; And counting start control means for starting counting from the first clock pulse of the first clock pulse and starting counting from the second clock pulse of the sampling clock when character data of the second and subsequent characters is received. Data reception control device.