JPH07321709A - Acquisition and latch device for spread spectrum code synchronization - Google Patents

Abstract

PURPOSE:To allow the device being hardly susceptible to the effect with temperature by reducing the number of adjustment factors. CONSTITUTION:The device is provided with a 1st spread code generator 7 for demodulation, a 2nd spread code generator 8 for synchronization acquisition and latching, a 1st multiplier 2 applying inverse spread to a received signal by multiplying a spread code 9 from the 1st spread code generator with a received signal, a 2nd multiplier 3 applying inverse spread to the received signal by multiplying a spread code 10 from the 2nd spread code generator with the received signal, a correlation device 6 obtaining the correlation of outputs of the 2nd multiplier 3, and a control means 13 that shifts the phase of the spread code of the 2nd spread code generator 8 over one period for synchronization acquisition, matches the phase of the spread codes from the 1st and 2nd spread code generators 7, 8 with a phase providing a maximum value when the maximum correlation by the correlation device at that time exceeds a prescribed value, shifts the phase of the spread code of the 2nd spread code generator 8 at a small prescribed phase width for synchronization latching and matches the phase of the spread codes from the 1st and 2nd spread code generators 7, 8 with a phase providing a maximum value of the correlation value by the correlation device at that time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a spread spectrum code synchronization acquisition and holding device used in, for example, power line carrier communication.

[0002]

2. Description of the Related Art In a spread spectrum communication system, an information signal to be transmitted is multiplied by a pseudo noise code (hereinafter referred to as a PN code) used as a spreading code to spread the information signal in a band wider than the bandwidth of the information signal. It is a communication method of transmitting by allowing it to be transmitted, and since it has excellent confidentiality and noise resistance, it is often used for communication on a poor transmission line.

In order to receive the signal transmitted by the spread spectrum communication, the PN included in the received signal is used.
It is necessary to generate and multiply the same PN code as the code on the receiving device side so that the phases match. As a matter of course, since the phase of the PN code included in the received signal cannot be known in advance on the receiving device side, as shown in FIG.
The phase of the PN code is detected by utilizing the characteristic that almost no correlation can be obtained when there is a phase difference of one chip (minimum unit of PN code) or more with respect to the autocorrelation function of the N code. In order to establish the phase synchronization of the PN code on the receiver side, it is necessary to have a function of capturing the phase error of the PN code within one chip and a function of holding the phase error of the PN code to 0.

FIG. 7 shows an example of a conventional spread spectrum code synchronization acquisition / holding device. In FIG. 7, 21 is an input terminal, 22, 23, 24 are multipliers, 25, 26, 27 are bandpass filters, 28, 29, 30 are envelope detectors, 31
Is a comparator, 32 is a differential amplifier, 33 is a loop filter,
34 is a voltage controlled oscillator, 35 is an AND gate, 36 is P
N code generator, 37 is a sweep controller, and 38 is a delay locked loop.

The spread spectrum signal input to the input terminal 21 is divided into three, and the PN code (0, + Δ, − from the PN code generator 36 is shifted by one chip each.
After being despread by being multiplied by Δ) by the multipliers 22 to 24, it passes through the band pass filters 25 to 27 that pass only the information modulation band, and the envelope detectors 28 to 3
It is detected by 0. The outputs are shown in FIGS. 8 (a) and 8 (b).
As shown in (c).

The synchronization acquisition here is performed in a sliding correlation loop. The output of the envelope detector 28, which has been subjected to envelope detection over one period of the PN code, is compared with a preset threshold level 39 by the comparator 31, and no correlation exceeding the threshold level 39 can be obtained. At this time, the sweep controller 37 operates and the PN code generator 36
The pulse of the input clock to is extracted by 1 pulse and the phase of the PN code is shifted by 1 chip. Since the PN code can usually obtain the correlation only within the range of the phase difference of ± 1 chip, if the output of the envelope detector 28 has the correlation exceeding the threshold level 39, the synchronization can be captured. And the sweep is stopped. After that, when the output of the envelope detector 28 falls below the threshold level, it is considered that the synchronization is lost, and the sweep is restarted.

The synchronization is maintained in the delay locked loop 38 while the sweep is stopped. Delayed phase and advanced phase 2
Despread with two PN codes, detected, differential amplifier 32
The control voltage of the voltage controlled oscillator 34 obtained by being differentially amplified by
As shown in (d), the delay lock loop 38 operates so as to be stable at the synchronization point 40 where the phase difference is zero.

[0008]

In FIG. 7, a correlator composed of bandpass filters 25 to 27 and envelope detectors 28 to 30 is used for synchronization acquisition and out-of-sync detection and synchronization holding PN. There are three for the code delay phase and for the sync hold PN code lead phase, and if the delay phase correlator and the lead phase correlator are not balanced, the output difference of these two correlators is given. There is a problem that the control voltage waveform of the voltage controlled oscillator 34 is distorted and an offset occurs in the delay locked loop 38, which causes deterioration of performance.

The voltage controlled oscillator 34 is set to output the rated frequency clock to the PN code generator 36 with the voltage at the synchronization point 40 of the control voltage. If the rated frequency clock is not output with voltage, there is a problem that the loop becomes stable at the point of deviation.

An object of the present invention is to provide a spread spectrum code synchronization acquisition / holding device which can reduce the number of adjustment elements and can be less affected by temperature.

[0011]

The present invention is a first demodulation system.
Spreading code generator, a second spreading code generator for synchronization acquisition and holding, and a first spreading code for despreading the received signal by multiplying the received signal by the spreading code from the first spreading code generator. A multiplier, a second multiplier that despreads the received signal by multiplying the received signal by the spreading code from the second spreading code generator, and a correlation value of the output of the second multiplier The phase of the spreading code of the second spreading code generator is shifted over one period for the correlator and the synchronization acquisition, and the maximum value of the correlation value by the correlator at that time exceeds a predetermined value. , The phases of the spreading codes of the first and second spreading code generators are made to coincide with the phase giving the maximum value, and in order to maintain synchronization, the phase of the spreading code of the second spreading code generator is set. Is shifted by a small predetermined width, and the correlator at that time is shifted The phase which gives the maximum value of the correlation values by, and a control means for matching the first and second spreading code generators spread code phase.

[0012]

In the present invention, the phase of the spreading code of the second spreading code generator is shifted over one cycle independently of the first spreading code generator, so that the single correlator holds the synchronous acquisition and holding. I am trying to do it.

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention.

1 is an input terminal of a spread spectrum signal which is a received signal, 2 and 3 are multipliers, 4 is a band pass filter, and 5
Is an envelope detector, which is a bandpass filter 4 and an envelope detector 5.
Constitutes the correlator 6. 7 is a PN code generator for demodulation,
Numeral 8 is a PN code generator for holding and capturing synchronization, and multipliers 2, 3
PN codes 9 and 10 are output with respect to. 11 and 12 are P
A programmable counter that supplies a clock CK to the N code generators 7 and 8, 13 is a programmable counter 11,
A CPU which controls 12 and outputs a clear signal 14 for setting the phase of the PN code of the PN code generators 7 and 8 to 0,
15 is an A / D converter for converting the correlation value into a digital value,
16 is a memory.

FIG. 2 shows a synchronization acquisition operation, that is, C in which the phase difference between the PN code included in the received signal and the PN codes 9 and 10 generated by the PN code generators 7 and 8 is within one chip.
It is a flowchart which shows operation | movement of PU13. [Step 1] The CPU 13 sends a clear signal 14 to the PN code generators 7 and 8 at the same time to send the two PN codes 9 and 9.
The phase of 10 is set to 0. Then, the programmable counters 11 and 12 are initialized so as to output the rated frequency clock of the PN code. [Step 2] P address, MP address, MA of memory 16
Address X is set to 0. PN code 9 and P at address P
A value indicating the phase difference of the N code 10 in units of one chip is stored. If one cycle of the PN code is M chips, 0 ≦ P ≦ M
Is. However, P = 0 and P = M are the same. A value indicating the phase of the PN code 10 giving the maximum correlation value is stored in the MP address. 0 ≦ MP ≦ M. The maximum correlation value is stored in the MAX address. 0 ≦ MAX. [Step 3] The CPU 13 controls the programmable counter 12 to change the pulse width of the clock CK to the PN code generator 8 to delay the phase of the PN code 10 by one chip. At this time, the phase of the PN code 9 is not shifted. How to shift the phase will be described later. [Step 4] The value of the address P in the memory 16 is incremented by 1. [Step 5] The CPU 13 waits for one cycle of the PN code 10. During this time, the received signal is divided into two, and the multipliers 2, 3
Are multiplied by the PN codes 9 and 10, respectively, and despread. The signal despread by the multiplier 3 passes through the bandpass filter 4, is detected by the envelope detector 5, and is converted into an A / D signal.
The signal is converted into a digital signal by the converter 15 and the CPU
13 is input. [Step 6] The CPU 13 samples the correlation value subjected to envelope detection over one period of the PN code 10. [Step 7] The sampled correlation value is compared with the value at the MAX address. Since MAX = 0 now at the beginning, the correlation value is naturally large, so the process proceeds to step 8.
If the correlation value of this time sampling is less than or equal to the value at the MAX address, the process jumps to step 10. [Step 8] The value of the address P is stored in the address MP, and the correlation value of the current sampling is stored in the address MAX. [Step 9] It is determined whether or not P = M, and steps 3 to 8 are repeated while P <M. That is, the correlation value sampling is repeated until the phase difference between the PN code 9 and the PN code 10 becomes M chips, and the maximum correlation value and its phase are stored in the MP address and the MAX address. When P = M, step 1
Move to 0. [Step 10] It is determined whether or not the maximum correlation value stored in the MAX address is higher than the threshold level sh. If it is larger, the process proceeds to step 11, and if it is smaller than that, the process proceeds to step 12. [Step 11] The phases of the PN code 9 and the PN code 10 are delayed by MP chips. As a result, the phase difference between the PN code included in the received signal and the PN codes 9 and 10 is within one chip.

In the above operation, the correlation value is sampled while being delayed by one chip. Therefore, the correlation value exceeding the threshold level sh cannot be obtained by sampling at the timing shown in FIG. It is possible. This is the case where the maximum correlation value in step 10 is less than or equal to the threshold level sh.
[Step 12] The phases of the PN code 9 and the PN code 10 are delayed by 1/2 chip, and the synchronization acquisition operation from step 2 is performed again.

Here, the shifting of the phases of the PN codes 9 and 10 by changing the pulse width of the clock CK of the programmable counters 11 and 12 will be described with reference to FIG.

The programmable counters 11 and 12 are CP
At the moment when the comparison value set by U13 and the count value match, the count value is cleared and toggled. For example, programmable counter 1
The frequency of the clock input to 1, 12 is the PN code 9,
Assuming 40 times the rated frequency of 10, if the comparison value is set to 20 by the CPU 13, 20 clocks are input to the programmable counters 11 and 12 to output P which is the output of the programmable counters 11 and 12.
A half cycle of the clock CK of the N code generators 7 and 8 is formed, the next half cycle is formed by inputting the next 20 clocks, and a total of 40 clock inputs form the PN code generators 7 and 8. Since one cycle of the clock CK is formed, the output frequencies of the programmable counters 11 and 12 become the rated frequencies of the PN codes 9 and 10.

Taking the case where the phase is delayed by 1/2 chip in step 12, the CPU 13 is monitoring the output of the programmable counter 12, and the count value (= 20) at time t ₁ in FIG. As soon as it is cleared, the comparison value is rewritten to 40. Then, when the count value (= 40) is cleared at time t ₂ , the comparison value is rewritten to 20 again. By this operation, the clock CK is kept at the high level from time t _{1 to} t ₂ , so that the phase is 1
/ 2 chips will be delayed. When advancing the phase by ½, as shown in FIG. 4B, the comparison value should be rewritten to 10 at time t ₃ and returned to 20 at time t ₄ . Similarly, by rewriting the comparison value to a value in the range of 1 to 40, the phase can be arbitrarily delayed or advanced with a shift width in which 1/40 chip is the minimum unit. Further, when the phase is shifted by a width such that the speed of the CPU 13 cannot catch up with the above operation, it may be performed in plural times.

Next, the synchronization holding operation will be described. FIG. 5 is a flow chart showing the synchronous holding operation, that is, the operation of the CPU 13 which brings the phase difference between the PN code and the PN codes 9 and 10 in the received signal within 1 chip close to 0 and keeps the phase difference at 0. Is.

Since the correlation was obtained while delaying by one chip at the time of acquisition, the phase of the PN code 10 is ±
There should be a maximum correlation value within 1/2 chip. [Step 21] The CPU 13 controls the programmable counter 12 to change the pulse width of the clock CK to the PN code generator 8 to advance only the phase of the PN code 10 by 1/2 chip. Here, it is assumed that the minimum shift width defined by the clock speed input to the programmable counters 11 and 12 is 1/40. From this step, the operation to bring the phase difference closer to 0 is started.
The phase will be shifted between 1/2 chips. [Step 22] The CPU 13 sets the comparison value X of the programmable counter 12 to 20. [Step 23] -X is stored in the P'address of the memory 16. Address P'is a value indicating the phase difference between PN code 9 and PN code 10 in units of 1/40 chips (-20≤P'≤20,-
The code is an address in which a phase lead) is stored. -X
Is stored in the memory 16 by -20/40, that is, by ½ chip. [Step 24] The CPU 13 waits for one cycle of the PN code 10. During this time, the received signal is divided into two, and the multiplier 2,
3, the PN codes 9 and 10 are respectively multiplied and despread. The signal despread by the multiplier 3 passes through the band pass filter 4, is detected by the envelope detector 5, and
The digital signal is converted by the D converter 15 into the CP.
Input to U13. [Step 25] The CPU 13 samples the correlation value detected by the envelope detection over one period of the PN code 10. [Step 26] -X is stored in the address MP ', and the correlation value of the current sampling is stored in the address MAX'. MP ′
A value indicating the phase of the PN code 10 that gives the maximum correlation value is stored in the address. -20 ≦ MP ′ ≦ 20. MA
The maximum correlation value is stored in the address X '. 0 ≦ MAX ′. [Step 27] The CPU 13 delays only the phase of the PN code 10 by 1/40 chip. [Step 28] The value at the address P'is incremented by one. [Step 29] The CPU 13 waits for one cycle of the PN code 10. During this time, the received signal is subjected to envelope detection, and the CPU 1
Input to 3. [Step 30] The CPU 13 samples the envelope-detected correlation value over one period of the PN code 10. [Step 31] The sampled correlation value is MAX ′.
Compare with the address value. If the correlation value is larger, the process proceeds to step 32, and the correlation value of the current sampling is MA.
If it is less than the value of the address X ', the process jumps to step 33. [Step 32] The value of the P'address is stored in the MP 'address, and the correlation value of the current sampling is stored in the MAX' address. [Step 33] It is determined whether or not P ′ = X, and −20 <
While P <20, steps 27 to 32 are repeated. That is,
Correlation value sampling is repeated until the phase difference between the PN code 10 and the PN code 9 becomes +1/2 chip, and the maximum correlation value and its phase are stored in the MP 'address and the MAX' address. When P = 20, the process proceeds to step 34. [Step 34] The phase of the PN code 10 is shifted to the phase indicated by (value stored in MP 'address / 40). [Step 35] The phase of the PN code 9 is matched with the phase of the PN code 10. As a result, P included in the received signal
The phase difference between the N code and the PN codes 9 and 10 is within 1/2 of the minimum shift width (within ± 1/80 chip). [Step 36] It is determined whether or not the maximum correlation value stored in the address MAX 'is higher than the threshold level sh. If it is less than that, it is considered that the synchronization is lost, and the process returns to step 2 of the synchronization acquisition operation of FIG. 2, and if it is larger, the process proceeds to step 37. [Step 37] The CPU 13 controls the programmable counter 12 to change the pulse width of the clock CK to the PN code generator 8 to advance only the phase of the PN code 10 by 3/40 chips. From this step, the operation to keep the phase difference at 0 is started, and in this operation ± 3 /
The phase will be shifted between 40 chips. [Step 38] The CPU 13 sets the comparison value X of the programmable counter 12 to 3. After this, step 2
3, and steps 23 to 38 are repeated.

Although the above-described synchronization holding operation has two steps, that is, an operation of approaching 0 and an operation of keeping it at 0, it may be one step of only an operation of approaching 0, or an operation of approaching 0 may be performed in two or more steps. The total number of stages may be three or more.

In the illustrated embodiment, the PN of the PN code generator 8 is
Since the phase of the code 10 is shifted independently of the PN code generator 7, the single correlator 6 carries out the synchronous acquisition and holding, so that it is not necessary to consider the balance of the correlators. , The number of adjustment elements can be reduced,
It can be made less susceptible to temperature.

When synchronization is held by a single correlator, it is not possible to know whether the phase shift is advanced or delayed by simply changing the correlation value. Therefore, unnecessary phase shift is performed to deteriorate the performance of information demodulation. Although it is possible that the two PN code generators 7 and 8 are used, the phase of one PN code generator 7 is fixed and the phase of the other PN code generator 8 is shifted during the sampling of the correlation value. Therefore, it is possible to judge whether the phase difference is advanced or delayed.

In the prior art, if the correlation value exceeds the threshold level, it is assumed that the synchronous acquisition is performed and the process shifts to the holding, so there may be another peak value and it may have been overlooked, but in the illustrated embodiment. Since the synchronization acquisition operation finds the maximum value by making correlation while shifting the phase for one cycle, it is possible to reliably prevent erroneous detection and oversight of synchronization.

It is conceivable that the spread spectrum signal will be momentarily cut off on a poor transmission line, but in the conventional loss-of-synchronization detection, information will be lost for a long time until the synchronization is captured again. On the other hand, in the illustrated embodiment, the received signal is despread by the demodulating PN code generator 7 and the multiplier 2 even during correlation value sampling, and is sent to the information demodulator, so that information loss is minimized. be able to.

[0027]

As described above, according to the present invention,
The first spread code generator for demodulation, the second spread code generator for synchronization and holding, and the spread code from the first spread code generator are multiplied by the received signal to reverse the received signal. A first multiplier for spreading, a second multiplier for despreading the received signal by multiplying the received signal by the spreading code from the second spreading code generator, and an output of the second multiplier The correlator that obtains the correlation value of
When the phase of the spread code of the second spread code generator is shifted over one cycle and the maximum value of the correlation value by the correlator at that time exceeds a predetermined value, the phase giving the maximum value is In order to make the phases of the spreading codes of the first and second spreading code generators coincide with each other and maintain the synchronization, the phases of the spreading codes of the second spreading code generator are shifted by a small predetermined width, and at that time, And a control means for matching the phases of the spreading codes of the first and second spreading code generators with the phase that gives the maximum correlation value by the correlator. Since the phase of the spread code is shifted over one cycle independently of the first spread code generator, the single correlator performs synchronous acquisition and holding, so that the number of adjustment elements can be reduced, Less susceptible to temperature It is possible. In addition, it is possible to reliably prevent erroneous detection and miss of synchronization.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a synchronization acquisition operation of the CPU in FIG.

FIG. 3 is a diagram showing a relationship between sampling points and correlation values in a synchronization acquisition operation.

FIG. 4 is a diagram showing an operation of the programmable counter in FIG.

5 is a flowchart showing a synchronization holding operation of the CPU in FIG.

FIG. 6 is a diagram showing an autocorrelation function of a PN code of one cycle M chips.

FIG. 7 is a block diagram showing an example of a conventional spread spectrum code synchronization acquisition and holding device.

8 is a diagram showing output waveforms of the envelope detector and the differential amplifier in FIG.

[Explanation of symbols]

 1 Input Terminal 2,3 Multiplier 4 Band Pass Filter 5 Envelope Detector 6 Correlator 7,8 PN Code Generator 9,10 PN Code 11,12 Programmable Counter 13 CPU 14 Clear Signal 15 A / D Converter 16 memory CK clock sh threshold level

Claims (1)

[Claims] 1. A received signal is multiplied by a first spreading code generator for demodulation, a second spreading code generator for synchronization and holding, and a spreading code from the first spreading code generator. A first multiplier for despreading the received signal according to
Second multiplier for despreading the received signal by multiplying the received signal by the spread code from the spread code generator, a correlator for obtaining a correlation value of the output of the second multiplier, In order to do so, when the phase of the spreading code of the second spreading code generator is shifted over one cycle, and the maximum value of the correlation value by the correlator at that time exceeds a predetermined value,
The phases of the spreading codes of the first and second spreading code generators are matched with the phase that gives the maximum value, and the phase of the spreading code of the second spreading code generator is made small in order to maintain synchronization. Spread spectrum including a control means for shifting the phase of a spread code of the first and second spread code generators to a phase that gives a maximum value of the correlation value by the correlator at the time of shifting by a predetermined width Code synchronization acquisition and holding device.