JPH07321645A - Phase comparator - Google Patents

Abstract

PURPOSE:To provide an output of a phase difference signal not including spike noise and a defective phase difference. CONSTITUTION:When the phase of an input signal R changes, a signal S103 in a set state is fed from a NAND gate 103 and a phase difference signal UP1 goes to an H level. When an input signal (v) changes, a signal S104 is fed from a NAND gate 104, since an RS-F108 is set, no spike noise is produced. In this case, each input terminal of a NAND gate 107 goes to an H level, a reset signal S107 is fed to RS-FFs105, 106, which are reset. Thus, output signals of the NAND gates 103, 104 are reset and the phase difference signal UP1 goes to an L. That is, the output signals S103, 104 are set as termination condition of the output of the phase difference signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase Locked).
Loop; hereinafter referred to as PLL) and the like.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference: Japanese Patent Application Laid-Open No. 63-263819 FIG. 2 is a circuit diagram of a phase comparator showing a first conventional example, and shows a phase comparator and a charge pump for generating a voltage according to its output. . The phase comparator 10 has three input terminals 11, 12, and 13. An input digital signal R is input to the input terminal 11, a digital feedback signal V from, for example, a voltage controlled oscillator is input to the input terminal 12, and an input. Terminal 1
A reset signal RS is input to each of the signals 3. Input terminals 11 and 13 are three-input NAND gate 1
4 and the input terminals 12 and 13 are connected to the input side of a 3-input NAND gate 15, respectively. The fed back signals are input to the remaining inputs of the NAND gates 14 and 15, respectively. N
The output terminal of the AND gate 14 is connected to one input terminal of the 3-input NAND gate 16,
The output signal from the output terminal 6 is fed back to the NAND gate 14. The output terminal of the NAND gate 15 is connected to one input terminal of the 3-input NAND gate 17,
The output signal from the output terminal of the ND gate 17 is fed back to the NAND gate 15. The phase comparator 10 is a reset set flip-flop (hereinafter referred to as RS-FF) composed of two 2-input NAND gates 18 and 19.
20 and an RS-FF 23 composed of two 2-input NAND gates 21 and 22. One input terminal of each NAND gate 18 and 19 and the NAND gate 1
The outputs of 8 and 19 are cross-connected to each other, and the output terminal of the NAND gate 14 is connected to the other input terminal of the NAND gate 18. The output terminal of the NAND gate 18 sends out the output signal RFF of the RS-FF 20, and the signal R
FF is a connection supplied to one input terminal of the NAND gate 16 and one input terminal of the 4-input NAND gate 24. The output terminal of the NAND gate 14 is connected to the other one of the input terminals of the NAND gate 24.
The output terminal of the D gate 24 has NAND gates 16 and 17
It is connected to the. On the other hand, each N in RS-FF23
One of the input terminals of the AND gates 21 and 22 and their NA
The outputs of the ND gates 21 and 22 are cross-connected to each other,
The output terminal of the NAND gate 15 is connected to the other input terminal of the NAND gate 22. NAND gate 22
Output terminal VFF of the RS-FF 23 is output, and the signal VFF is a connection supplied to one input terminal of the NAND gate 17 and one input terminal of the NAND gate 24. The output terminal of the NAND gate 24 is R
NAND gates 21 and 19 in the S-FFs 20 and 23
Is connected to the other input terminal of. The NAND gates 16 and 17 send output signals U and D corresponding to the phase difference between the signals R and V to the charge pump 30, respectively.

The charge pump 30 has field effect transistors 31 and 32 connected in series between a power source and ground,
The transistor 31 has a configuration in which conduction is controlled based on a signal U input to the gate. The transistor 32 is NOT
The configuration is such that conduction is controlled based on a signal D input to the gate through the circuit 33. The charge pump 30 outputs a voltage signal from the output terminal 34 according to the conduction state of each of the transistors 31 and 32. FIG. 3 is a time chart showing the operation of FIG. 2, and shows the waveform of each part of the phase comparator. The reset signal RS is at a high level (hereinafter,
"H"), the reset state is released and, for example, the signals RFF and VFF rise as shown in FIG. After that, when the signal R falls, N
The output signal U of the AND gate 16 falls as shown in (G) of FIG. 3, and the output signal FB and the signal D of the NAND gate 24 become (F) of FIG.
It falls like (H). Further, each of the signals U and D becomes low level (hereinafter referred to as "L") and "H" due to the fall of the signal FB. Each signal U, D
Is a determination signal indicating the phase and frequency difference between the signals R and V. For example, when the phase of the signal V is behind that of the signal R, the signal U becomes "L" and the signal D becomes "H". If the signal V leads the signal R in phase, the signal U becomes "H" and the signal D becomes "L". When the signal V has the same phase as the signal R, both the signal U and the signal D are “H”. The signals U and D are supplied to the charge pump 30,
The field effect transistors 31 and 32 are switched. As a result, the voltage signal shown in (I) of FIG. 3 is output from the output terminal 34. Here, X in (I) of FIG.
1 and X2 are parts where the level is indefinite and become spike noise. FIG. 4 is a circuit diagram of a phase comparator showing a second conventional example, and elements common to FIG. 2 in the circuit of FIG. 4 are designated by common reference numerals. The phase comparator of the second conventional example is an improvement of the circuit of the phase comparator of FIG. 2 in order to output a voltage signal in which the levels X1 and X2 of which the levels are undefined are generated in the phase comparator of FIG. It is a thing.

This phase comparator has an input digital signal R and a digital feedback signal V as in the first conventional example shown in FIG.
And NAND gates 14 to 22 and three delay terminals T1 and T2 are provided unlike FIG. The delay element T1 is connected between the output terminal of the NAND gate 14 and the input terminal of the NAND gate 16, and the delay element T2 is connected between the output terminal of the NAND gate 15 and the input terminal of the NAND gate 17. FIG. 5 is a time chart showing the operation of FIG. 4, and this figure corresponds to FIG. Although the phase comparator shown in FIG. 2 produced indefinite portions X1 and X2 in the output signal of the charge pump, they act on the signals U and D shown in FIG. 3 due to the delay time in the NAND gate 24. Noise n1, n2
It was happening because of. That is, for example, NAN
The output signal of the NAND gate 15 is directly supplied to the D gate 17, and the signal via the NAND gate 24 is input. Since the NAND gate 24 has a delay time, noises n1 and n2 were generated. Since the phase comparator of FIG. 4 is provided with the delay elements T1 and T2, the signals input from the NAND gates 14 and 15 to the NAND gates 16 and 17 are delayed by at least the delay time of the NAND gate 24, and noise is generated. Generation of n1 and n2 is prevented. Therefore, it is possible to obtain a voltage output without an indefinite portion as shown in FIG.

[0005]

However, the conventional phase comparator has the following problems. The phase comparator of the first conventional example has a problem that the output signal of the charge pump 30 contains spike noise because of the delay time due to the NAND gate 24. Further, spike noise does not occur in the phase comparator of the second conventional example, but the phase difference between the two input signals R and V is smaller than the rising or falling delay time of the logic gate constituting this phase comparator. The output signals U and D of 1 are crushed, and a dead zone in which the phase difference cannot be detected occurs. For example,
When the input signal R becomes “L” first and then the input signal V becomes “L”, it is delayed through the delay element T2 that the NAND gate 16 starts the phase difference output “L”. When the inverted input signal R is input to the NAND gate 16, the end of the output of the phase difference signal of the NAND gate 16 depends on the output of the NAND gate 15 not through the delay element T2. Therefore, when the phase difference between the input signals R and V is small, the NAND gate 16 does not output "L" of the phase difference signal, and the state ends.
Since the phase comparator is mainly used as a circuit forming a PLL, when the phase comparator of the first conventional example is used for the PLL, it is affected by spike noise, and the phase comparator of the second conventional example is used. If there was a dead zone,
There is a problem that the jitter in the PLL increases.

[0006]

In order to solve the above-mentioned problems, the first invention is to detect the rising or falling of the first input signal and the second input signal and detect the phase of the first input signal. Is ahead of the phase of the second input signal, the first phase difference signal is transmitted during a period corresponding to the phase difference, and the phase of the first input signal is greater than the phase of the second input signal. In the phase comparator which outputs the second phase difference signal for a period corresponding to the phase difference when delayed, the following first set circuit,
It has a second set circuit, a flip-flop output stage, and a logic circuit. The first set circuit includes one or a plurality of flip-flops, is set according to the level of the first input signal, is reset by a first reset signal, and has a set state and a set state corresponding to the set and reset, respectively. The configuration is such that the first set signal that becomes the logic level in the reset state is transmitted. The second set circuit is composed of one or more flip-flops,
A function of transmitting a second set signal which is set according to the level of the second input signal and is reset by the first reset signal and which becomes a set state and a logic level of the reset state corresponding to the set and the reset, respectively. Have The flip-flop output stage is set or reset by the first and second set signals,
The first and second phase difference signals are output.
A logic circuit is composed of one or more logic gates,
When the first and second set signals are both in the set state, the first reset signal is sent to the first and second set circuits. The second invention is the first
A first set circuit, a second set circuit,
The flip-flop output stage and the logic circuit are configured as follows. That is, the first set circuit is set by the level of the first input signal and is reset by the first reset signal to be set and logical levels of a set state and a reset state according to the reset. Having a first RS-FF for transmitting a set signal,
The first set signal is in a set state while the third set signal is in the logic level of the set state,
The second set circuit is set by a level of a second input signal and reset by the first reset signal to be a set state corresponding to the set and the reset and a logic level of the reset state. And a second RS-FF for transmitting the signal, the second set signal is in the set state during the period of the logic level in which the fourth set signal is in the set state.

The flip-flop output stage has the first
And a third R which is set or reset by the first and second set signals and outputs the first and second phase difference signals.
S-FF, and the logic circuit includes the first and second logic circuits.
Is detected from the third and fourth set signals, and the first reset signal is sent to the first and second RS-FFs. A third invention is the first set circuit, the second set circuit, the flip-flop output stage in the first invention,
And the logic circuit has the following configuration. That is, the first set circuit inputs the first input signal to the clock terminal, takes in data of a predetermined level in synchronization with the falling or rising of the first input signal, and becomes the set. Of the first D-type flip-flop (hereinafter, referred to as D-FF) which is reset when the reset signal is input to the reset terminal and sends out the first set signal of the logic level corresponding to the set and reset. is doing. When the second input signal is input to the clock terminal, data of a predetermined level is captured in synchronization with the fall or rise of the second input signal, and the set is made, and the first reset signal is input to the reset terminal. The second D-FF is set to be reset and the second set signal having a logic level corresponding to the set and the reset is transmitted. The flip-flop output stage is configured by an RS-FF that is set or reset by the first and second set signals and outputs the first and second phase difference signals, and the logic circuit includes the first and second RS-FFs. The second reset signal and the second reset signal are both set, and the first reset signal is sent to the first and second D-FFs. A fourth invention comprises the first set circuit, the second set circuit and the flip-flop output stage in the first invention, and is constituted by one or a plurality of logic gates, and the first set signal is set. When the second phase difference signal is output in the state or when the first phase difference signal is output in the state where the second set signal is set, the first reset signal is set to the first and the second reset signals. A logic circuit for sending to the set circuit 2 is provided.

According to a fifth aspect of the invention, the first set circuit, the second set circuit, the flip-flop output stage, and the logic circuit of the fourth aspect are configured as follows. That is, the first set circuit is set by the level of the first input signal and is reset by the first reset signal to be set and logical levels of a set state and a reset state according to the reset. A first RS-FF for transmitting a set signal is provided, and the first set signal is in the set state while the third set signal is at the logic level of the set state. The second set circuit is set by a level of a second input signal and reset by the first reset signal to be a set state corresponding to the set and the reset and a logic level of the reset state. Second RS sending out
-FF, and the second set signal is in the set state while the fourth set signal is in the logic level of the set state. The flip-flop output stage is set or reset by the first and second set signals and outputs the first and second phase difference signals.
When the second phase difference signal is output while the first set signal is in the set state, or when the second set signal is in the set state, the logic circuit has a first position. When the phase difference signal is output, the first reset signal is sent to the first and second RS-FFs. A sixth invention is the first invention of the fourth invention.
The setting circuit, the second setting circuit, the flip-flop output stage, and the logic circuit are configured as follows. That is,
The first reset circuit inputs the first input signal to a clock terminal, fetches data of a predetermined level in synchronization with the falling or rising of the first input signal, and is set to be the first reset. A first signal that is reset when a signal is input to the reset terminal, and that sends out the first set signal having a logic level corresponding to the set and the reset and a third set signal having a phase opposite to that of the first set signal. DF
It consists of F. The second set circuit includes the second set circuit.
Input signal is input to the clock terminal, data of a predetermined level is taken in and set in synchronization with the fall or rise of the second input signal, and reset when the first reset signal is input to the reset terminal. , A second D-FF for transmitting a second set signal having a logic level corresponding to the set and reset and a fourth set signal having a phase opposite to that of the second set signal. The flip-flop output stage is configured by an RS-FF that is set or reset by the first and second set signals and outputs the first and second phase difference signals, and the logic circuit includes the third circuit. The first reset signal is output when the second phase difference signal is output in the set state of the second set signal or when the first phase difference signal is output in the set state of the fourth set signal. The configuration is such that the data is sent to the first and second D-FFs.

[0009]

According to the first aspect of the invention, since the phase comparator is constructed as described above, the rising or falling of the first input signal and the second input signal is detected and the phase of the first input signal is detected. Is ahead of the phase of the second input signal, the first phase difference signal is transmitted for a period corresponding to the phase difference, and the first phase difference signal is transmitted.
When the phase of the input signal of 1 is delayed from the phase of the second input signal, the following operation is performed in the phase comparator which transmits the second phase difference signal for a period corresponding to the phase difference. The first set signal, which becomes a logic level in the set state and the reset state according to the level of the first input signal, is the first
The second set signal is transmitted from the second set circuit and is set to the logic level of the set state and the reset state according to the level of the second input signal.
For example, when the level of the first input signal changes from the initial state, the first set signal in the set state is sent to the flip-flop output stage, the flip-flop stage is set, and the first phase difference signal is sent. It On the other hand, when both the first and second set signals are in the set state, the first reset signal is sent from the logic circuit to the first and second set circuits, and the first and second set circuits are reset. .
Therefore, the transmission of the first phase difference signal ends. According to the second invention, the third set signal corresponding to the level of the first input signal is transmitted from the first RS-FF, and the third set signal is output during the period of the logic level in the set state. The first set signal in the first aspect of the invention is transmitted in the set state. The fourth set signal according to the level of the second input signal is transmitted from the first RS-FF, and the third set signal is the second level of the first invention during the period of the logic level in the set state. The set signal is sent in the set state. The third RS-FF is set or reset by the first and second set signals, and the first and second phase difference signals are output from the third RS-FF. On the other hand, the logic circuit detects from the third and fourth set signals that the first and second set signals are both in the set state, and the first reset signal is the first and second RS-FF. Sent to. According to the third invention, the first set signal in the first invention is transmitted from the first D-FF, and the second set signal is transmitted from the second D-FF. The RS-FF is set or reset by the first and second set signals, and the RS-FF outputs the first and second phase difference signals. On the other hand, the logic circuit includes the first and second
It is detected that the set signals of the above are both set, and the first reset signal is output from the logic circuit to the first and second D-F.
Sent to F.

According to a fourth aspect of the invention, the logic circuit outputs the first set signal in the set state and the second phase difference signal in the set state, or the second set signal in the set state in the first state. The first reset signal is transmitted when the phase difference signal is being output, and the first reset signal causes the first reset signal to be output.
The first set circuit and the second set circuit in the invention are reset. According to a fifth invention, in the fourth invention, the first RS-FF sends out a third set signal that is in a set state based on the first input signal, and the third set signal is During the set state, the first set signal in the fourth aspect of the invention is in the set state. Second RS-
The FF sends out the fourth set signal that is in the set state based on the second input signal, and while the fourth set signal is in the set state, the second set signal in the fourth invention is in the set state. . The third RS-FF is set or reset by the first and second set signals, and
And the second phase difference signal is output by the third RS-FF. On the other hand, the first reset is performed when the first set signal is in the set state and the second phase difference signal is output, or when the second set signal is in the set state and the first phase difference signal is output. The signal is sent to the first and second RS-FFs by the logic circuit. According to a sixth invention, in the fourth invention, the first D-FF sends the first set signal and a third set signal having a phase opposite to that of the first set signal, and the second D-FF outputs the second set signal. The D-FF sends a second set signal and a fourth set signal having a phase opposite to that of the second set signal. RS
-FF is set or reset by the first and second set signals, and the first and second phase difference signals have their RS
-Output by FF. On the other hand, the logic circuit outputs the first signal when the third set signal is in the set state and the second phase difference signal is output, or when the fourth set signal is in the set state.
It is detected that the phase difference signal is output, and the first reset signal is sent to the first and second D-FFs. Therefore, the above problem can be solved.

[0011]

First Embodiment FIG. 1 is a circuit diagram of a phase comparator showing a first embodiment of the present invention. The phase comparator detects rising or falling of the first input signal R and the second input signal V, and when the phase of the signal R leads the phase of the signal V, the phase comparator detects the rising or falling of the first input signal R and the second input signal V during a period corresponding to the phase difference. The phase difference signal UP1 is transmitted, and when the phase of the signal R is delayed from the phase of the signal V, the second phase difference signal DW1 is transmitted for a period corresponding to the phase difference, and the phase comparator of FIG. It has two input terminals In1 and In2 for inputting respective signals R and V, respectively. Input terminal In
1 is a NAND having two input terminals a and b (not shown)
The input terminal In2 is connected to the input terminal a of the gate 101.
Is connected to the input terminal a of the NAND gate 102 having two input terminals a and b (not shown). The output terminal of the NAND gate 101 has an input terminal a of the NAND gate 103 having three input terminals a, b and c (not shown).
The output terminal of the NAND gate 103 is connected to N
It is feedback-connected to the input terminal b of the AND gate 101. The output terminal of the NAND gate 102 has a NAND gate 104 having three input terminals a, b and c (not shown).
Of the NAND gate 104, and the output terminal of the NAND gate 104 is feedback-connected to the input terminal b of the NAND gate 102. That is, the two NAND gates 101, 1
03 constitutes one flip-flop, and similarly 2
One NAND gate 102, 104 constitutes one flip-flop. This phase comparator includes two RS-FFs 10 which are a first RS-FF and a second RS-FF, respectively.
5, 106 are provided. An output terminal of the NAND gate 101 is connected to one input terminal of a 2-input RS-FF 105 and an input terminal a of a NAND gate 107 of a logic circuit having four input terminals a, b, c and d (not shown). Has been done. The RS-FF 105 includes two NAND gates 105-1 and 105-2, and each NAND gate 10
5-1 and 105-2 respectively have two input terminals a and b. The output terminal of the NAND gate 101 is connected to the input terminal a of the NAND gate 105-1,
The output terminal of the ND gate 105-1 is the RS-FF10.
5 output terminals. NAND gate 105-1
Of the NAND gate 105-2 has an output terminal of
And the output terminal of the NAND gate 105-2 is NAN.
The input terminals b of the D-gate 105-1 are connected side by side. The output terminal of the NAND gate 105-1,
That is, the output terminal of the RS-FF 105 is the NAND gate 10
3 and the NAND gate 1
07 is connected to the input terminal b.

On the other hand, the output terminal of the NAND gate 102 is connected to one input terminal of a 2-input RS-FF 106 and N
It is connected to the input terminal d of the AND gate 107.
The RS-FF 106 has two NAND gates 106-1,
106-2, each NAND gate 106-1,10
6-2 has two input terminals a and b, respectively.
The NAND gate 106-1 has an input terminal a at which a NAND
The output terminal of the gate 102 is connected to the NAND gate 1
The output terminal of 06-1 is the output terminal of the RS-FF 106. The output terminal of the NAND gate 106-1 is connected to the input terminal a of the NAND gate 106-2, and the NAN
The output terminal of the D gate 106-2 is the NAND gate 106.
The input terminals b of -1 are connected side by side.
Output terminal of NAND gate 106-1, that is, RS-FF
The output terminal of 106 is the input terminal b of the NAND gate 104.
And the input terminal c of the NAND gate 107. The output terminals of the NAND gates 107 are commonly connected to the other input terminals of the RS-FFs 105 and 106. NAND gates 101 and 103
The flip-flop composed of 1 and the RS-FF 105 constitute a first set circuit F1, which is set according to the level of the signal R to output the first set signal to the NAND gate 10
It sends from 3. In addition, each NAND gate 102, 10
The flip-flop composed of 4 and the RS-FF 106 constitute a second set circuit F2, which is set in accordance with the level of the signal V to output the second set signal to the NAND gate 1
This is a configuration for sending from 04. Two NAND gates 1
The output terminals of 03 and 104 are connected to the input terminals of a two-input third RS-FF 108 which is a flip-flop output stage. The RS-FF 108 has two NOR gates 1.
08-1 and 108-2, and each NOR gate 108-
Reference numerals 1 and 108-2 denote input terminals a and b (not shown), respectively.
Is equipped with. The output terminal of the NAND gate 103 is NO
NAND connected to the input terminal a of the R gate 108-1
The output terminal of the gate 104 is connected to the input terminal a of the NOR gate 108-2. Those NOR gates 108
-1, 108-2 output terminals and NOR gate 108-
The input terminals b of 1 and 108-2 are cross-connected to each other, and the output terminals Out1 and Out2 of the NOR gates 108-1 and 108-2 output the phase difference signals UP1 and DW1 which are the phase difference detection results. It is a configuration.

FIG. 6 is a time chart showing the operation of FIG. 1, and shows the waveform of each part of FIG. The operation of the phase comparator of FIG. 1 will be described with reference to this figure. In the initial state, as shown in FIG. 6, the two input signals R and V are both "H", and the output signals S101 and S of the NAND gates 101 and 102, respectively.
102 are both "L", outputs S105 and S106 of the RS-FFs 105 and 106 are both "H", and output signals of the NAND gates 103 and 104, that is, signals S103 and S104 that are the first and second set signals are both "H", NAN
An output signal of the D gate 107, that is, a first reset signal S10 for resetting the first and second set circuits F1 and F2.
7 is "H", and the phase difference signals UP1 and DW1 are both "L". When the input signal R changes to "L" in such an initial state, the signal S101 changes to "H", and the output signal S1 of the NAND gate 103 changes.
03 becomes the set state “L”. Therefore, RS-F
F108 is set, the phase difference signal UP1 changes to "H", and the output of the phase difference is started. Next, when the input signal V also changes to "L", the output signal S102 of the NAND gate 102 changes to "H" and the output signal S104 of the NAND gate 104 changes to "L" in the set state. Signal S
104 is supplied to RS-FF 108, but RS-FF
Since 108 has already been set, RS-FF108
Output DW1 remains unchanged at "L". That is, in the previous stage, the output signal of the NOR gate 108-1 becomes "H" and is input to the input terminal b of the NOR gate 18-2, so that even if the signal S104 changes to "L", The phase difference signal DW1 does not change and is held as "L". For this reason, spike noise unlike the first conventional example does not occur. Further, at this time, the input signals R and V are "L", and the signals S101 and S102, the output signal S105 of the RS-FFS 105, and the output signal S106 of the RS-FF 106 are output.
All become "H", and the output signal S107 of the NAND gate 107 changes to "L" which is the first reset signal. As the signal S107 changes to "L", each R
S-FFs 105 and 106 and NAND gates 103 and 10
4 are reset respectively. Therefore, each NAND
Output signals S103 and S104 of the gates 103 and 104
Both change to "H", the RS-FF 108 is reset, and the output of the phase difference by the phase difference signal UP1 ends. On the other hand, even when the input signal V first changes to "L" in the initial state, the output signal does not include spike noise. This is clear from the symmetry of the circuit.

As described above, in this embodiment, the RS-FF is used.
Since 108 is provided, the RS-FF 108 enters a set state at the edge that arrives first with respect to the phase difference between the falling edges of the two input signals R and V, and the signal UP1 or DW1 that is the phase difference detection signal is transmitted. Starts and does not change at the trailing edge. Therefore, no spike noise is generated. Further, the reset condition in the RS-FF 108 is that the levels of the two signals S103 and 104 are "L", that is, that the input signals R and V are both "L". Even if the phase difference between the input signals R and V is extremely small, the output signal is not crushed. Therefore, when this phase comparator is used in a PLL, jitter can be reduced.

Second Embodiment FIG. 7 is a circuit diagram of a phase comparator showing a second embodiment of the present invention. This phase comparator has an input terminal I for inputting two signals R and V which are first and second input signals, respectively.
n1 and In2, and input signals R and V from the input terminals In1 and In2 to the clock terminal CLK, respectively.
And second D-FFs 201 and 202. Each of the D-FFs 201 and 202 has a data input terminal D and always inputs a signal of "H" to the data input terminal D, respectively. That is, the respective D-FFs 201 and 202 take in "H" from the data input terminal D in synchronization with the falling edges of the signals R and V. Further, each D-FF 201, 202 has a positive phase output terminal Q.
And a reset terminal Re for sending an inverted output and a reset terminal Re, respectively. The inverting output terminal Q / of the D-FF 201 has an input terminal a of a NOR gate 203 which is a logic circuit having two input terminals a and b (not shown),
RS-FF20 which is a 2-input flip-flop output stage
4 is connected to one of the input terminals. D-FF2
The inverting output terminal Q / of 02 is connected to the input terminal b of the NOR gate 203 and the other input terminal of the RS-FF 204. The output terminal of the NOR gate 203 is connected to each D-FF2.
The terminals Re of 01 and 202 are commonly connected. RS
-FF204 has two NOR gates 204-1 and 20-2.
It is composed of 4-2. Each NOR gate 204-1,
204-2 has input terminals a and b (not shown), and the input terminals b and output terminals of the NOR gates 204-1 and 204-2 are connected to each other in a side-by-side relationship. Output terminals Out1 and Ou of the NOR gates 204-1 and 204-2
The first and second phase difference signals UP2 and DW2, which are phase difference detection signals between the two input signals R and V, are output from t2.

FIG. 8 is a time chart showing the operation of FIG. 7, and the operation of this phase comparator will be described with reference to this figure. FIG. 8 shows the input signals R and V and the D-FF 201.
Inverted output signal S201, inverted output signal S202 of D-FF202, and output signal S20 of NOR gate 203
3 and the waveforms of the phase difference signals UP2 and DW2 are shown. In the initial state, as shown in FIG. 8, the two input signals R and V are both “H”, the respective signals S201 and S202 are both “H”, the two phase difference signals UP2 and DW2 are both “L”, and the NOR gate. It is assumed that the output signal of 203, that is, the reset signal S203 is "L". In the initial state, for example, when the level of the input signal R first changes to "L", the signal S201 which is the first set signal changes to "L" in the set state. R with the change of the signal S201
The S-FF 204 is set, the phase difference detection is started, and the phase difference signal UP2 becomes "H". Next, when the input signal V also changes to "L", the signal S2 which is the second set signal
02 changes to "L" in the set state and RS-FF204
Is supplied to. Since the RS-FF 204 has already been set, the level of the phase difference signal DW2 does not change and "L" is held. That is, the output signal does not include spike noise. At this time, signals S201 and S202
Are both "L", the signal S203 sent from the NOR gate 203 changes to "H", and each D-FF 20
1, 202 are reset together. Therefore, each signal S
Both 201 and S202 change to "H", and the D-FF20
4 is reset. That is, the phase difference signal UP2 ends the output of the phase difference detection. On the other hand, even when the input signal V first changes to "L" in the initial state, the output signal does not include spike noise. This is clear from the symmetry of the circuit. As described above, in this embodiment, RS-F
Since the F204 is provided, the RS-FF 204 enters the set state at the edge that arrives first with respect to the phase difference between the falling edges of the two input signals R and V, and outputs the signal UP2 or DW2 which is the phase difference detection signal. Starts and does not change at the trailing edge. Therefore, no spike noise is generated. Further, the levels of the two input signals R and V are "L".
Since this is a reset condition in the RS-FF 204, the output signal is not crushed even when the phase difference between the input signals R and V is extremely small. Therefore, when this phase comparator is used for PLL,
Jitter can be reduced.

Third Embodiment FIG. 9 is a circuit diagram of a phase comparator showing a third embodiment of the present invention. This phase comparator has two input terminals In for inputting two first and second input signals R and V, respectively.
1 and In2. The input terminal In1 is connected to the input terminal a of the NAND gate 301 having two input terminals a and b (not shown), and the input terminal In2 is connected to the input terminal a of the NAND gate 302 having two input terminals a and b (not shown). Has been done. The output terminal of the NAND gate 101 is connected to the input terminal a of a NAND gate 303 having three input terminals a, b, and c (not shown), and the output terminal of the NAND gate 303 is the NAND gate 30.
It is feedback-connected to the input terminal b of 1. The output terminal of the NAND gate 302 has three input terminals a,
connected to an input terminal a of a NAND gate 304 having b and c, and an output terminal of the NAND gate 304 is NAN.
It is feedback-connected to the input terminal b of the D gate 302. That is, the two NAND gates 301 and 303 configure one flip-flop, and similarly, the two NAND gates 302 and 304 configure one flip-flop. This phase comparator includes first and second RS-FFs.
The RS-FFs 305 and 306 are respectively included. The output terminal of the NAND gate 301 is a 2-input R
A NAND gate 3 having one input terminal of the S-FF 305 and five input terminals a, b, c, d and e (not shown).
07 is connected to the input terminal a. RS-FF30
5 includes two NAND gates 305-1 and 305-2, and each NAND gate 305-1 and 305-2 has two input terminals a and b, respectively. The output terminal of the NAND gate 301 is connected to the input terminal a of the NAND gate 305-1, and the output terminal of the NAND gate 305-1 is the output terminal of the RS-FF 305.
The output terminal of the NAND gate 305-1 is connected to the input terminal a of the NAND gate 305-2, and the NAND gate 305
The output terminal of -2 is connected to the input terminal b of the NAND gate 305-1 in a crossed manner. The output terminal of the NAND gate 305-1, that is, the output terminal of the RS-FF 305 is connected to the input terminal b of the NAND gate 303 and the input terminal b of the NAND gate 307.

On the other hand, the output terminal of the NAND gate 302 is connected to one input terminal of a 2-input RS-FF 306 and the NAN.
It is connected to the input terminal e of the D gate 307. R
The S-FF 306 has two NAND gates 306-1 and 3-3.
06-2, each NAND gate 306-1, 306
-2 has two input terminals a and b, respectively. N
The output terminal of the NAND gate 302 is connected to the input terminal a of the AND gate 306-1, and the NAND gate 30
The output terminal of 6-1 is the output terminal of the RS-FF 306. The output terminal of the NAND gate 306-1 is N
To the input terminal a of the AND gate 306-2 and the NAND
The output terminal of the gate 306-2 is the NAND gate 306-
Each of the input terminals 1 is connected to the other input terminal b. N
Output terminal of AND gate 306-1, that is, RS-FF3
The output terminal of 06 is connected to the input terminal b of the NAND gate 304 and the input terminal d of the NAND gate 307.
It is connected to the. The output terminals of the NAND gates 307 are commonly connected to the other input terminals of the RS-FFs 305 and 306. The flip-flop composed of the NAND gates 301 and 303 and the RS-FF 305 are
It constitutes a first set circuit F1. The third set signal S is output from the RS-FF 305 according to the levels of the signals R and V.
305 is sent out, and the first set signal S303 set by the third set signal S305 is NAND.
It is transmitted from the gate 303. In addition, a flip-flop composed of each NAND gate 302, 304 and RS-
The FF 306 constitutes a second set circuit F2. A fourth set signal S306 is sent from the RS-FF 306 according to the levels of the signals R and V, and a second set signal S304 set by the third set signal S306 is sent from the NAND gate 304. is there.

The output terminals of the two NAND gates 303 and 304 are RS, which is a third flip-flop having two inputs.
-Connected to the input terminal of FF308. RS-FF
A flip-flop output stage 308 has two NOs.
It has R gates 308-1 and 308-2. Each NO
The R gates 308-1 and 308-2 respectively include input terminals a and b (not shown). NAND gate 303
Of the NAND gate 303 is connected to the input terminal a of the NOR gate 308-1, and the output terminal of the NAND gate 303 is connected to the input terminal a of the NOR gate 308-2. Each NOR
The output terminals of the gates 308-1 and 308-2 and the input terminals b of the NOR gates 308-1 and 308-2 are cross-connected to each other, and their NOR gates 308-1 and 308-2 are connected.
The output signals UP3 and DW3 which are the phase difference detection results are output from the output terminals Out1 and Out2. Further, the phase comparator of the present embodiment has a logic circuit 3
NAND gates 309, 310 and 311 are provided, and each NAND gate 309, 310 and 311 has two input terminals a and b (not shown). The output terminal of the NAND gate 301 is connected to the input terminal a of the NAND gate 309,
The output terminal of the NOR gate 308-2 in the RS-FF 308 is connected to the input terminal b of. The output terminal of the NAND gate 302 is connected to the input terminal a of the NAND gate 310, and the output terminal of the NOR gate 308-1 is connected to the input terminal b of the NAND gate 310. The output terminals of the NAND gates 309 and 310 are N
The AND gate 311 is connected to the input terminals a and b, respectively, and the output terminal of the NAND gate 311 is connected to the NAND gate 311.
The input terminal c of the gate 307 is connected. Figure 10
10 is a time chart showing the operation of FIG. 9, and the operation of the phase comparator of FIG. 10 will be described with reference to this figure. In the initial state, as shown in FIG. 10, the two input signals R and V are both “H”, and the output signals S of the NAND gates 301 and 302 are
301 and S302 are both “L”, each RS-FF 305,
The output of 306, that is, the third and fourth set signals S305,
Both S306 are "H", each NAND gate 303, 30
4 output signals, that is, the first and second set signals S303,
Both of S304 are “H”, the output signal S307 of the NAND gate 307 is “H”, and the phase difference signal UP3 is UP3.
It is assumed that both DW3 are "L".

When the input signal R changes to "L" in such an initial state, the signal S301 changes to "H",
The output signal of the NAND gate 303, that is, the signal S303, which is the first set signal, becomes "L" in the set state. Therefore, RS-FF308 is set, and the phase difference signal UP
3 changes to "H" and the output of the phase difference is started. next,
When the input signal V also changes to "L", the NAND gate 30
The output signal S302 of No. 2 becomes "H", and the output signal S304 of the NAND gate 304 changes to "L". The signal S304 which is the second set signal is supplied to the RS-FF 308, but since the RS-FF 308 has already been set, the output DW3 of the RS-FF 308 remains "L" and does not change. That is, in the previous stage, the output signal of the NOR gate 308-1 becomes "H" and is input to the input terminal b of the NOR gate 308-2, so that the signal S304 is "L".
, The phase difference signal DW3 does not change and is held as "L". Therefore, spike noise unlike the conventional case does not occur. Further, at this time, since the signal S302 and the phase difference signal UP3 are both "H", the NAND gate 3
The output signal S310 of 10 changes to "L", and the output signal S311 of the NAND gate 311 changes to "H". Further, when the input signals R and V are "L" and each signal S30
1, output signal S305 of S302 and RS-FFS305
And the output signal S306 and the signal S311 of the RS-FF 306
And are all "H", the NAND gate 30
The output signal S307 of No. 7 changes to "L" and becomes the first reset signal. As the signal S307 changes to "L", the RS-FFs 305 and 306 and the NAND gate 30
3, 304 are reset respectively. Therefore, the output signals S303, S of the NAND gates 303, 304
Both 304 change to "H", RS-FF308 is reset, and the output of the phase difference by the phase difference signal UP3 is complete | finished. On the other hand, even when the input signal V first changes to "L" in the initial state, the output signal does not include spike noise. This is clear from the symmetry of the circuit. As described above, in this embodiment, since the RS-FF 308 is provided, the RS-FF 308 is set to the set state at the first-arriving edge with respect to the phase difference between the falling edges of the two input signals R and V. Signal UP that is a phase difference detection signal
3 or the signal DW3 is started to be transmitted, and does not change at the trailing edge. Therefore, no spike noise is generated. Further, since the signal UP3 or DW3 outputting the phase difference is a reset condition for ending the phase difference detection, even if the phase difference between the two input signals R and V is extremely small, the output is performed. The signal does not collapse.
Therefore, when this phase comparator is used in a PLL, jitter can be reduced.

Fourth Embodiment FIG. 11 is a circuit diagram of a phase comparator showing a fourth embodiment of the present invention. This phase comparator has input terminals In1 and In2 for inputting two signals R and V which are first and second input signals and input signals R and V from the input terminals In1 and In2 to a clock terminal CLK. First and second respectively
D-FFs 401 and 402 are provided. Each D-FF4
01 and 402 have a data input terminal D, and a signal of "H" is always inputted to the data input terminal D, respectively. That is, each of the D-FFs 401 and 402 takes in "H" from the data input terminal D in synchronization with the falling edges of the signals R and V. Each D
Each of the -FFs 401 and 402 has a positive phase output terminal Q, an inverting output terminal Q / for sending an inverting output, and a reset terminal Re. Inverted output terminal Q / of D-FF401
Outputs a first set signal S401 / and is connected to one input terminal of a 2-input RS-FF403. The inverting output terminal Q / of the D-FF402 is the second
Output the set signal S402 /
It is connected to the other input terminal of the FF403. RS-
The FF403 is a flip-flop output stage and includes two N
It is composed of OR gates 403-1 and 403-2.
Each of the NOR gates 403-1 and 403-2 has input terminals a and b (not shown). D-FF401,
The inverting output terminal Q / of 402 is the NOR gate 403-
1, 403-2 are respectively connected to the input terminals a, and each N
The input terminals b and output terminals of the OR gates 403-1 and 403-2 are connected to each other in a side-by-side relationship. NOR gate 40
Phase difference signals UP4 and DW4, which are phase difference detection signals between the two input signals R and V, are output from the output terminals Out1 and Out2 of 3-1 and 403-2, respectively.

The phase comparator of this embodiment further includes three NAND gates 404, 405, which form a logic circuit.
406 is provided and each of the NAND gates 404, 4 is provided.
05 and 406 are two input terminals a, not shown,
b. The positive-phase output terminal Q of the D-FF 401 that outputs the third set signal S401 is the NAND gate 4
No. 4 of the NOR gate 4 in the RS-FF 403 is connected to the input terminal a of
The output terminal of 03-2 is connected. The positive-phase output terminal Q of the D-FF 402 that outputs the fourth set signal is NA
The NAN connected to the input terminal a of the ND gate 405.
The NOR gate 403 is connected to the input terminal b of the D gate 405.
The output terminal of -1 is connected. Each NAND gate 4
The output terminals of 04 and 405 are connected to the input terminals a and b of the NAND gate 406, and the output terminals of the NAND gate 406 are commonly connected to the terminals Re of the D-FFs 401 and 402. FIG. 12 is a time chart showing the operation of FIG. 11, and the operation of this phase comparator will be described with reference to this figure. In FIG. 12, input signals R and V and D-
Positive phase output signals S401 and S402 of the FFs 401 and 402
And the inverted output signal S401 of each D-FF 401, 402.
/, S402 / and the output signal S of the NAND gate 404
404 and the output signal S405 of the NAND gate 405.
, And the output signal S406 of the NAND gate 406 and the waveforms of the phase difference signals UP4 and DW4 are shown. In the initial state, as shown in FIG. 12, the two input signals R and V are both "H", the respective signals S401 / and S402 / are both "H", and the two phase difference signals UP4 and DW4 are both "L".
Shall be In the initial state, for example, when the level of the input signal R first changes to "L", the first set signal S401 / changes to "L". The RS-FF 403 is set in accordance with the change of the signal S401 /, the phase difference detection is started, and the output signal UP4 becomes "H". Next, when the input signal V also changes to "L", the signal S402 / changes to "L".
And is supplied to the RS-FF 403. RS-FF
Since 403 has already been set, the phase difference signal DW4
The level of is not changed and "L" is held. That is, the output signal does not include spike noise.

At this time, since the positive phase output signal S402 and the phase difference signal UP4 of the D-FF 402 are both "H", the output signal S405 of the NAND gate 405 is "L".
, And the output signal S406 of the NAND gate 406 changes to "H". Therefore, two D-FFs 401,
402 is reset and RS-FF403 is also reset, and the output signal UP4 ends the output of the phase difference. on the other hand,
Even when the input signal V first changes to "L" in the initial state, the output signal does not include spike noise. This is clear from the symmetry of the circuit. As described above, in this embodiment, since the RS-FF 403 is provided, with respect to the phase difference between the falling edges of the two input signals R and V,
The RS-FF 403 enters the set state at the first-arriving edge and starts transmitting the signal UP4 or DW4 which is the phase difference detection signal, and does not change at the last-arriving edge. for that reason,
No spike noise is generated. Further, the fact that the signal UP4 or DW4 outputs the phase difference is a reset condition for ending the phase difference detection. Therefore, even if the phase difference between the two input signals R and V is extremely small, the output is performed. The signal does not collapse. Therefore, when this phase comparator is used in a PLL, jitter can be reduced. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the first to fourth embodiments, the phase difference signals UP1 and UP are based on the falling edges of the input signals R and V.
2, UP3, UP4, DW1, DW2, DW3, DW4
Is transmitted, the rising edge may be detected and the phase difference signal may be output. Also in this case, the jitter in the PLL can be reduced as in the above embodiment. (2) The NAND gates 107 and 307 in the first and third embodiments may be composed of a plurality of logic gates.

[0024]

As described in detail above, the first to third aspects
According to the invention of claim 1, a first set circuit and a second set circuit for sending the first and second set signals to the phase comparator in accordance with the levels of the first and second input signals, respectively. When the flip-flop output stage set or reset by the first and second set signals and the first and second set signals are both in the set state, the first reset signal is set to the first and second reset signals.
And a logic circuit for sending to the set circuit. Therefore, it is possible to send the first and second phase difference signals which do not include spike noise and whose phase difference is not collapsed.
Therefore, for example, when the phase comparator is used for the PLL, the jitter can be reduced. According to the fourth to sixth inventions, in the logic circuit of the first invention, the first set signal is in the set state and the second phase difference signal is output, or the second set signal is in the set state. Since the first reset signal is output to the first and second set circuits when the first phase difference signal is being output by the first phase difference signal, the first and second phase difference signals from the flip-flop output stage are output. The signal reset condition is that the first or second phase difference signal is output, spike noise is not included,
Moreover, it is possible to send the first and second phase difference signals whose phase difference is not collapsed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a phase comparator showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a phase comparator showing a first conventional example.

FIG. 3 is a time chart showing the operation of FIG.

FIG. 4 is a circuit diagram of a phase comparator showing a second conventional example.

5 is a time chart showing the operation of FIG. 4. FIG.

FIG. 6 is a time chart showing the operation of FIG.

FIG. 7 is a circuit diagram of a phase comparator showing a second embodiment of the present invention.

FIG. 8 is a time chart showing the operation of FIG.

FIG. 9 is a circuit diagram of a phase comparator showing a third embodiment of the present invention.

FIG. 10 is a time chart showing the operation of FIG.

FIG. 11 is a circuit diagram of a phase comparator showing a fourth embodiment of the present invention.

FIG. 12 is a time chart showing the operation of FIG. 11.

[Explanation of symbols]

105, 106, 108, 204, 305, 306, 3
08,403 RS-FF 107,203,307,309-311,404-4
06 logic gate (logic circuit) 201, 202, 401, 402 D-FF F1, F2 set circuit R, V input signal UP1 to UP4, DW1 to DW4 phase difference signal

Claims (6)

[Claims] 1. When the rising or falling of the first input signal and the second input signal is detected and the phase of the first input signal leads the phase of the second input signal, the phase difference When the phase of the first input signal lags behind the phase of the second input signal, the first phase difference signal is sent for a corresponding period, and the second phase difference signal is sent for a period corresponding to the phase difference. In the phase comparator, one or more flip-flops are set, which are set by the level of the first input signal and reset by the first reset signal, and set state and reset corresponding to the set and reset, respectively. A first set circuit that sends out a first set signal that is the logical level of the state; and one or more flip-flops, which are set according to the level of the second input signal. A second set circuit which is reset by the first reset signal and sends out a second set signal which becomes a logical level of a set state and a reset state corresponding to the set and reset, respectively; and the first and second set circuits. A flip-flop output stage that is set or reset by a set signal and outputs the first and second phase difference signals, and one or a plurality of logic gates, and the first and second set signals are both set. A logic circuit for sending the first reset signal to the first and second set circuits when in the state. 2. The first set circuit is set by the level of a first input signal and reset by the first reset signal to be set and logical levels of a set state and a reset state corresponding to the reset. A first reset set flip-flop for transmitting a third set signal, wherein the first set signal is in a set state while the third set signal is at a logic level in a set state, The second set circuit sets a fourth set signal that is set according to the level of the second input signal and is reset by the first reset signal to become the set state corresponding to the set and the reset and the logical level of the reset state. Has a second reset set flip-flop for sending out,
The second set signal is in the set state while the fourth set signal is in the logic level of the set state, and the flip-flop output stage is set or reset by the first and second set signals. And a third reset set flip-flop for outputting the first and second phase difference signals, wherein the logic circuit is configured so that the first and second set signals are both in a set state. The phase comparator according to claim 1, characterized in that the first reset signal is detected from the third and fourth set signals and the first reset signal is sent to the first and second reset set flip-flops. 3. The first set circuit inputs the first input signal to a clock terminal and fetches data of a predetermined level in synchronization with the falling or rising of the first input signal to form a set. A first D-type flip-flop that is reset when the first reset signal is input to a reset terminal and sends out the first set signal having a logic level corresponding to the set and the reset; Input signal is input to the clock terminal, data of a predetermined level is taken in in synchronization with the fall or rise of the second input signal, and a set is made, which is reset when the first reset signal is input to the reset terminal. And a second D-type flip-flop for transmitting the second set signal having a logic level corresponding to the set and reset. The output stage is configured by a reset set flip-flop that is set or reset by the first and second set signals and outputs the first and second phase difference signals, and the logic circuit includes the first and second set signals. 2. The configuration is such that it is detected that both second set signals are in a set state and the first reset signal is sent to the first and second D-type flip-flops. Phase comparator. 4. A first set circuit and a second set circuit according to claim 1.
A set circuit and a flip-flop output stage, and is configured by one or a plurality of logic gates, and when the second phase difference signal is output in the set state of the first set signal or the second phase difference signal. A logic circuit is provided for sending the first reset signal to the first and second set circuits when the first phase difference signal is being output in the set state of the set signal. Comparator. 5. The first set circuit is set by a level of a first input signal and reset by the first reset signal to be a set state and a logic level of a reset state corresponding to the set and reset. A first reset set flip-flop for transmitting a third set signal, wherein the first set signal is in a set state while the third set signal is at a logic level in a set state, The second set circuit sets a fourth set signal that is set according to the level of the second input signal and is reset by the first reset signal to become the set state corresponding to the set and the reset and the logical level of the reset state. Has a second reset set flip-flop for sending out,
The second set signal is in the set state while the fourth set signal is in the logic level of the set state, and the flip-flop output stage is set or reset by the first and second set signals. And a third reset set flip-flop for outputting the first and second phase difference signals, wherein the logic circuit outputs the second phase difference signal in the set state of the first set signal. Or if the second
When the set signal is set and the first phase difference signal is output, the first reset signal is sent to the first and second reset set flip-flops. The phase comparator according to claim 4. 6. The first setting circuit is set by inputting the first input signal to a clock terminal, taking in data of a predetermined level in synchronization with the falling or rising of the first input signal, and setting the data. The first reset signal is reset when the first reset signal is input to the reset terminal, and the first set signal having a logic level corresponding to the set and reset and a third set signal having a phase opposite to the first set signal. The second set circuit inputs the second input signal to a clock terminal and synchronizes with the falling or rising of the second input signal. A second set signal of a logic level corresponding to the set and the reset, which is reset when the first reset signal is input by inputting data of a predetermined level and the first reset signal is input to the reset terminal. A second D-type flip-flop for transmitting a fourth set signal having an opposite phase to the second set signal, wherein the flip-flop output stage is set by the first and second set signals. The reset circuit includes a reset set flip-flop that is reset and outputs the first and second phase difference signals, and the logic circuit outputs the second phase difference signal in the set state of the third set signal. Case or the fourth
When the set signal is set and the first phase difference signal is output, the first reset signal is sent to the first and second D-type flip-flops. The phase comparator according to claim 4.