JPH07321195A - Soi-type semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve a peripheral structure of an SOT layer and to restrain formation of a parasitic MOS transistor not to reduce connection with an adjacent element and an SOI layer even if an isolation size becomes small regarding an SOI-type semiconductor device wherein an island-like thin film semiconductor part is formed on an insulation film. CONSTITUTION:A structure of an SOI-type semiconductor device wherein an island-like thin film semiconductor part is formed on an insulation film is made free from a corner of a lower layer part of a periphery of a semiconductor part 18. When an insulation film 16 is formed on a surface of a first semiconductor substrate, a second substrate 15 is adhered through at least the insulation film 16, film thinning is realized by polishing a rear of the first semiconductor substrate and an SOI-type semiconductor device is formed by forming a thin film semiconductor part, isotropic etching is carried out first during isolation region formation in a rear formation process and then silicon is etched by anisotropic etching and a structure which is free from a corner of a lower layer part of a periphery of a thin film semiconductor part is acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI type semiconductor device and a method for manufacturing the same. In the present specification, “SOI
The term “mold” generally refers to a semiconductor device having a structure in which a semiconductor portion is formed in a thin film shape, surrounded by an insulating material, and exists in an island shape, and is not necessarily limited to a silicon semiconductor device.

[0002]

2. Description of the Related Art Conventionally, there is known a semiconductor device having a structure in which a semiconductor portion is formed in a thin film shape, surrounded by an insulating material, and exists in an island shape. For example, as this type, SOI (Si having a thin silicon layer formed on an insulating film
2. Description of the Related Art A semiconductor device such as a Licon on Insulator) is known. Such a semiconductor device has advantages over a bulk semiconductor device such as no latch-up, good radiation resistance, a small junction capacitance, and a high-speed circuit, and a fully depleted SOI device. In the semiconductor device, compared with the partially depleted SOI semiconductor device,
It has many advantages such as a small S value and a low substrate bias effect.

SOI for forming SOI semiconductor device
There are various methods for manufacturing a substrate, such as a bonding method and a SIMOX method. Here, a semiconductor substrate and another substrate are adhered via at least an insulating film, and the semiconductor substrate is polished from the back surface (generally, a polishing A conventional bonding method for forming an element on an SOI layer obtained by thinning the film by performing grinding to near the end point and a final precision polishing step) will be described.

Please refer to FIG. 20 through FIG. First, a resist is applied to the surface of the first semiconductor substrate 31 and patterned to obtain a resist pattern 32 (FIG. 20).
Using this as a mask, a portion to be an element isolation region in the final SOI type semiconductor device structure is patterned by anisotropic etching (etching depth is 100 nm or less, for example) (FIG. 21).

Next, a silicon oxide film (thickness: 100 nm to 1 μm, for example) 33 is formed as a buried insulating film on the surface of the first semiconductor substrate 31 by thermal oxidation and the CVD method (FIG. 22).

Next, a polycrystalline silicon layer (having a thickness of, for example, 5 μm) is formed as the bonding layer 34 by the CVD method,
The surface is polished to form a flat bonding surface. FIG. 23
Shows the state after polishing the polycrystalline silicon that is the bonding layer 34. (The broken line is the state before polishing.)

Next, the above-mentioned bonding layer (polycrystalline silicon layer) 3
The surface of the first semiconductor substrate 31 is attached to the surface of the second semiconductor substrate 35 which will be the base, as shown in FIG.
Are turned upside down, that is, the back surface of the first semiconductor substrate 31 faces upward.

Next, the back surface of the first semiconductor substrate 31 is polished by using the silicon oxide film 33 for forming the element isolation region as a stopper to form an SOI layer 36 forming an island-shaped silicon island (FIG. 25). Here, the polishing is performed by so-called physical polishing with chemical polishing while using a polishing liquid.

Thereafter, a gate insulating film (gate oxide film) 37 and a gate electrode 38 are formed by a generally used ordinary method to form a transistor (FIG. 2).
6). FIG. 27 is a plan view (however, the gate insulating film 37 is not shown) of FIG. 26 viewed from the direction XXVII in FIG.

[0010]

By the way, in the SOI transistor manufactured by the conventional method described above,
As shown in the graph of FIG. 28, the back gate bias dependency has a problem that “bump” can be formed in a region below the threshold voltage.

This is considered to be caused by the presence of a parasitic MOS transistor having a low threshold voltage Vth, and as can be understood from the Id-Vg characteristic of FIG. 29, it is susceptible to the back gate bias effect. , Corners of the lower layer of the silicon layer where electric field concentration is likely to occur (symbol A in FIG.
It is considered that a parasitic MOS transistor is present in the area marked with ().

In order to suppress the formation of the parasitic MOS transistor, it is effective to form the SOI layer in a forward taper shape as shown in FIG. Due to this taper, the SOI layer 36, as shown by reference numeral A ′ in FIG.
The corners at the bottom of the are relaxed or disappear (the taper portion is shown by the symbol B in FIG. 30). For example, in the case where a tapered SOI layer is formed by using the LOCOS method, as shown in FIG. 31, even if a back gate bias is applied, the parasitic MOS
No transistor formation is seen.

However, in the forward taper etching method, as shown in FIG. 32A, the substrate 4 is formed by taper etching using a resist pattern 42, for example.
After forming No. 1, an insulating film 43 and a bonding film 44 are formed as shown in FIG. 32B, and a substrate 45 to be a base is laminated and polished as shown to form an SOI layer 46 which is a semiconductor portion. However, in this case, when the size of the element isolation formed by the insulating film 43 becomes small, there arises a problem that the SOI layers 46 contact each other and are connected to the adjacent element. Also, L
In the method using the OCOS method, the LOCOS 47 is used as shown in FIG. 33A, and the semiconductor portion 46 between the LOCOS 47 is used as the SOI layer as shown in FIG. 33B. When the element isolation size formed by the film 43 is reduced, the SOI layer 46 is reduced in size.

The present invention was devised in view of such conventional problems. Even if the size of element isolation becomes small, the element is connected to the adjacent element or the semiconductor portion S is formed.
An SOI semiconductor device capable of improving the structure around an SOI layer (silicon island or the like) which is a semiconductor portion and suppressing the formation of a parasitic MOS transistor therein without reducing the size of the OI layer, and a method of manufacturing the same. Is what you are trying to get.

[0015]

According to the invention of claim 1 of the present application, an S-shaped semiconductor film portion having an island-shaped thin film is formed on an insulating film.
In the OI type semiconductor device, an SOI type semiconductor device is characterized in that a lower layer portion around the semiconductor portion has no corner, and the above problem is solved by this.

According to the invention of claim 2 of the present application, an insulating film is formed on the surface of the first semiconductor substrate, and the second substrate is bonded through at least the insulating film, and the back surface of the first semiconductor substrate is formed. In a method of manufacturing an SOI type semiconductor device in which a thin film is formed by polishing a thin film to form a thin film semiconductor portion, isotropic etching is first performed at the time of forming an element isolation region in a back surface forming step, and then silicon is anisotropically etched. An SOI having a structure in which a cornerless structure of a lower layer portion around a thin film semiconductor portion is obtained by etching.
A method for manufacturing a semiconductor device of the type, which solves the above problems.

The invention according to claim 3 of the present application is an SOI in which an island-shaped thin film semiconductor portion is formed on an insulating film by partially insulating a semiconductor substrate to form an insulating film.
In the method for manufacturing a type semiconductor device, when the element isolation region is formed, first, anisotropic etching is performed, and then silicon is etched by isotropic etching, thereby forming a cornerless structure of a lower layer portion around the thin film semiconductor portion. A method for manufacturing an SOI type semiconductor device, which is characterized in that it is obtained, and which solves the above-mentioned problems.

The invention according to claim 4 of the present application is the method for manufacturing an SOI semiconductor device according to claim 3, wherein the partial insulation treatment is ion implantation and / or heat treatment. This solves the above problem.

According to a preferred aspect of the present invention, there is provided an SOI semiconductor device in which a silicon semiconductor device has a corner-less structure in a lower layer portion around a formed SOI layer (silicon island).

In addition, an insulating film is formed on the surface of the first semiconductor substrate, and the second semiconductor substrate is adhered onto the insulating film, for example, via a polycrystalline silicon layer or directly to form a first semiconductor substrate. The back side is ground and polished to make it thin, and S
In the method for manufacturing an SOI semiconductor device in which an OI layer is formed, isotropic etching is first performed and then silicon is anisotropically etched to form an SOI layer (silicon island ) SO in a mode of eliminating the corners of the lower layer around
An I semiconductor device manufacturing method is provided.

Further, in a method of manufacturing an SOI semiconductor device in which an insulating film is formed on a semiconductor substrate by ion implantation of oxygen and heat treatment, and an SOI layer is formed, anisotropic etching is first performed at the time of forming an element isolation region, Then, by over-etching silicon by isotropic etching, there is provided a method for manufacturing an SOI semiconductor device in which the corners of the lower layer are eliminated around the SOI layer (silicon island).

According to the present invention, for example, as shown in FIG. 34, the semiconductor substrate 51 is previously etched by an etching technique using a resist pattern 52 or the like to form a convex portion 56 'having a tapered corner. Figure 34
As shown in (b), the SOI layer 56 without corners is obtained. In the figure, 53 is an insulating layer, 54 is a bonding layer, and 55 is a base substrate.

[0023]

According to the present invention, by eliminating the corner of the lower layer around the SOI layer (the island-shaped semiconductor portion such as a silicon island), formation of the parasitic MOS transistor in the peripheral portion of the SOI layer can be suppressed. . Further, even if the size of element isolation is reduced, there is no concern that it will be connected to an adjacent element or the SOI layer will be reduced.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. However, it should be understood that the present invention is not limited to the illustrated embodiments.

Example 1 In this example, the present invention is embodied when an SOI semiconductor device is obtained by a bonding method.

Please refer to FIG. 1 through FIG. First, the first
A resist is applied to the surface portion of the semiconductor substrate 11 and patterned to obtain a resist pattern 12 (FIG. 1).

Using this as a mask, the portion that will eventually become the element isolation region in the SOI type semiconductor device structure is patterned into a concave shape. In this case, as shown in FIG. 2, etching is performed under isotropic etching conditions. (The etching depth is, for example, 50 nm or less).

Subsequently, as shown in FIG. 3, etching is further performed (the etching depth is, for example, 50 nm or less) under anisotropic etching conditions. The resist is removed to obtain the structure shown in FIG.

In the semiconductor substrate 11, the region etched under the isotropic etching condition is considered to be basically rounded, but it may be tapered if it is. In the present invention, the effect is exhibited even if the portion is straight or rounded, as long as it has a shape without a corner.

Next, the semiconductor substrate 1 that has been etched
On the surface of No. 1 by a thermal oxidation and / or CVD method as a buried insulating film 13 having a silicon oxide film (thickness of 1
00 nm to 1 μm) (FIG. 5). If it is necessary to embed wiring, capacitors, etc. on the back surface of the finally formed SOI layer, they may be formed at this stage.

Further, a polycrystalline silicon layer (thickness, for example, 5 μm) is formed as the bonding layer 14 by the CVD method, and the surface thereof is polished to form a flat bonding surface. FIG. 6 shows a state after the bonding layer (polycrystalline silicon) 14 is polished. (The broken line shows the state before polishing.)

Next, the above-mentioned bonding layer (polycrystalline silicon layer) 1
The front surface of No. 4 is attached to the surface of the second substrate 15 serving as a base, and the first semiconductor substrate 1 is turned upside down, that is, the back surface of the first semiconductor substrate 11 is turned upward as shown in FIG. To be Since the second substrate 15 is used as a table, this is not necessarily a semiconductor substrate. Substrates of any material can be used as long as they are compatible with the subsequent semiconductor process, and an appropriate material may be used. However, since a material similar to that of the semiconductor substrate 11 is preferable in terms of thermal expansion and the like, a silicon substrate is also used here. Further, when a semiconductor substrate is used as the base substrate 15, a device can be formed on this substrate 15.

Next, the back surface of the first semiconductor substrate 11 is ground and polished to leave a silicon layer of several μm. Further, physical polishing is performed using the polishing liquid while using the element isolation region insulating film (silicon oxide film) 13 as a stopper, so to speak, so to speak, so as to obtain silicon oxide as shown in FIG. An SOI layer 18 surrounded by the film 13 is formed.

After that, the gate oxide film 16 and the gate electrode 17 are formed by a generally used ordinary method to form a transistor (FIG. 9). 10 is a plan view of the X direction arrow of FIG. 9 (however, the gate insulating film 16 is not shown).
Shown in.

As described above, according to the present embodiment, the insulating film is formed on the surface of the first semiconductor substrate, the second substrate is adhered on the insulating film, and the first semiconductor is formed. In a method of manufacturing an SOI semiconductor device in which a back surface of a substrate is thinned by grinding and polishing to form an SOI layer, isotropic etching is first performed when an element isolation region is formed in a back surface forming step, and then anisotropy is performed. By etching the silicon by etching, the corners of the lower layer around the SOI layer (silicon island) can be eliminated, and formation of the parasitic MOS transistor in the peripheral portion of the silicon island can be suppressed. Further, even if the size of element isolation is reduced, there is no concern that the element will be connected to the adjacent element or the SOI layer will be reduced.

Example 2 This example is an example in which the present invention is embodied by using a partial insulation treatment of a silicon substrate, in particular, insulation by ion implantation of oxygen.

First, as shown in FIG. 11, oxygen ion implantation (implantation amount is, for example, 10 nm) into the first semiconductor substrate 21.
¹⁸ / cm ² and the implantation depth is 100 nm). Reference numeral 22 denotes a layer into which oxygen ions are implanted (ion implantation layer)
Indicates.

Next, heat treatment (1200 to 1350 ° C., 4
~ 6 hours) to react the ion-implanted oxygen with silicon to form a silicon oxide film layer forming the insulating film 23. FIG. 12 shows a state in which the insulating film (silicon oxide film) 23 is formed. The portion indicated by the reference numeral 24 above it is the SOI layer.

This method is generally used for SIMO.
Similar to the X method, the crystallinity of the semiconductor layer (silicon layer) 24 on the insulating film (silicon oxide film) 23 can be kept good by alternately repeating ion implantation and heat treatment.

Next, resist patterning is performed on a portion to be an element isolation region by using a photolithography technique to obtain a resist pattern 25 (FIG. 13).

Next, as shown in FIG. 14, the sidewall protective film 2
The semiconductor region (silicon SOI layer) 24 is etched under anisotropic etching conditions while the number 6 is given. At this time, the etching time depends on the insulating film (buried oxide film)
The time to reach 23 can be determined in advance and subtracted from the time by a certain amount of time, and etching is stopped in a state where the insulating film (buried oxide film) 23 is not reached.

Subsequently, the buried oxide film 23 is etched under isotropic etching conditions having a high selection ratio with respect to the oxide film.
After reaching the point, overetching is performed. Then,
As shown in FIG. 15, SOI layer (silicon island)
It is possible to obtain a cornerless structure in the lower layer around 24. The resist is removed to obtain the structure shown in FIG.

Subsequently, as shown in FIG. 17, the etched element isolation region is filled with the insulating film 27, and there are various methods. For example, there is a method of thickly depositing an insulating film, flattening it, and then etching back, a method of combining a bias ECRCVD method and CMP, but any method may be used.

After that, a gate oxide film 28 and a gate electrode 29 are formed by a commonly used ordinary method to form a transistor (FIG. 18). XIX in FIG.
A plan view seen from the direction of the arrow is shown in FIG. 19 (however, the gate insulating film 28 is not shown).

As described above, according to the present embodiment, the semiconductor substrate is partially insulated, in which oxygen ion implantation and heat treatment are performed to form an insulating film. When obtaining an SOI type semiconductor device in which an island-shaped semiconductor portion is formed on an insulating film, anisotropic etching is first performed at the time of forming an element isolation region, and then silicon is etched by isotropic etching to obtain a thin film. It is possible to eliminate the corners of the lower layer around the semiconductor part,
It was possible to suppress the formation of the parasitic MOS transistor in the peripheral portion of the silicon island. Further, even if the size of element isolation is reduced, there is no concern that the element will be connected to the adjacent element or the SOI layer will be reduced.

[0046]

As described above, according to the present invention, even if the size of element isolation is reduced, the SOI layer (island-shaped semiconductor portion) is not connected to the adjacent element or the SOI layer is reduced. It was possible to provide an SOI semiconductor device and a method for manufacturing the same, which can eliminate the corners of the lower layer around () and suppress the formation of parasitic MOS transistors there.

[Brief description of drawings]

FIG. 1 is a sectional view showing the manufacturing process of the first embodiment of the present invention (1).

FIG. 2 is a sectional view showing the manufacturing process of the first embodiment of the present invention (2).

FIG. 3 is a cross-sectional view showing the manufacturing process of Example 1 of the present invention (3).

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention (4).

FIG. 5 is a sectional view showing the manufacturing process of the first embodiment of the present invention (5).

FIG. 6 is a cross-sectional view showing the manufacturing process of Example 1 of the present invention (6).

FIG. 7 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention (7).

FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention (8).

FIG. 9 is a cross-sectional view showing the manufacturing process of Example 1 of the present invention (9).

FIG. 10 is a plan view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing the manufacturing process of the second embodiment of the present invention (1).

FIG. 12 is a sectional view showing the manufacturing process of the second embodiment of the present invention (2).

FIG. 13 is a sectional view showing the manufacturing process of the second embodiment of the present invention (3).

FIG. 14 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention (4).

FIG. 15 is a sectional view showing the manufacturing process of the second embodiment of the present invention (5).

FIG. 16 is a cross-sectional view showing the manufacturing process of Example 2 of the present invention (6).

FIG. 17 is a sectional view showing the manufacturing process of the second embodiment of the present invention (7).

FIG. 18 is a cross-sectional view showing the manufacturing process of Example 2 of the present invention (8).

FIG. 19 is a plan view showing a manufacturing process according to the second embodiment of the present invention.

FIG. 20 is a sectional view showing the manufacturing process of the conventional example (1).

FIG. 21 is a cross-sectional view showing the manufacturing process of the conventional example (2).

FIG. 22 is a cross-sectional view showing the manufacturing process of the conventional example (3).

FIG. 23 is a cross-sectional view showing the manufacturing process of the conventional example (4).

FIG. 24 is a cross-sectional view showing the manufacturing process of the conventional example (5).

FIG. 25 is a cross-sectional view showing the manufacturing process of the conventional example (6).

FIG. 26 is a cross-sectional view showing the manufacturing process of the conventional example (7).

FIG. 27 is a plan view showing the manufacturing process of the conventional example.

FIG. 28 is a diagram showing a problem.

FIG. 29 is a diagram showing a problem.

FIG. 30 is a diagram showing a problem.

FIG. 31 is a diagram showing a problem.

FIG. 32 is a diagram showing a problem.

FIG. 33 is a diagram showing a problem.

FIG. 34 is an explanatory diagram showing a configuration of the present invention.

[Explanation of symbols]

 11, 21 1st semiconductor substrate 12, 22 resist pattern 13, 23 (embedding) insulating film (oxide film) 14 bonding layer (polycrystalline silicon layer) 15 (becomes a base) second substrate 16, 28 gate insulating film 17,29 Gate electrode 18,24 SOI layer (island semiconductor part)

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[Procedure amendment]

[Submission date] October 28, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art Conventionally, there is known a semiconductor device having a structure in which a semiconductor portion is formed in a thin film shape, surrounded by an insulating material, and exists in an island shape. For example, as this type, SOI (Si having a thin silicon layer formed on an insulating film
2. Description of the Related Art A semiconductor device such as a Licon on Insulator) is known. Such a semiconductor device has advantages such as no latch-up, good radiation resistance, a small junction capacitance, and a high-speed circuit, as compared with a bulk semiconductor device, and also a fully depleted SOI device. In the semiconductor device, compared with the partially depleted SOI semiconductor device,
S value is small, it has many advantages such as less susceptible to the substrate bias effect.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010]

By the way, in the SOI transistor manufactured by the conventional method described above ,
As shown in the graph of FIG. 29 , there is a problem that “bump” can be formed in a region below the threshold voltage.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

This is considered to be caused by the presence of a parasitic MOS transistor having a low threshold voltage Vth, and as can be understood from the Id-Vg characteristics of FIG. 28 , it is susceptible to the back gate bias effect. , Corners of the lower layer of the silicon layer where electric field concentration is likely to occur (symbol A in FIG.
It is considered that a parasitic MOS transistor is present in the portion marked with ().

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/08 331 E 27/12 BF

Claims (4)

[Claims] 1. An SOI semiconductor device having an island-shaped thin film semiconductor portion formed on an insulating film, wherein a lower layer around the semiconductor portion has no corners. . 2. An insulating film is formed on a surface of a first semiconductor substrate, and a second substrate is bonded at least through the insulating film,
In a method of manufacturing an SOI type semiconductor device in which a back surface of a first semiconductor substrate is thinned by polishing to form a thin film semiconductor portion, isotropic etching is first performed at the time of forming an element isolation region in a back surface forming step, and then, A method for manufacturing an SOI type semiconductor device, wherein a structure without corners of a lower layer portion around a thin film semiconductor portion is obtained by etching silicon by anisotropic etching. 3. A method for manufacturing an SOI type semiconductor device, wherein an island-shaped thin film semiconductor portion is formed on an insulating film by partially insulating a semiconductor substrate to form an insulating film. At the time of formation, first perform anisotropic etching,
A method of manufacturing an SOI semiconductor device, characterized in that a structure without corners of a lower layer portion around a thin film semiconductor portion is obtained by subsequently etching silicon by isotropic etching. 4. The method for manufacturing an SOI semiconductor device according to claim 3, wherein the partial insulation treatment is ion implantation and / or heat treatment.