JPH07321190A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a highly reliable semiconductor device wherein defect generation in an isolation region in a silicon substrate is reduced. CONSTITUTION:After an oxide film 26 and a nitride film 27 are formed one by one on a silicon layer 24, ion implantation for isolation is carried out through the nitride film 27 and an isolation region (impurity diffusion layer) 30a is formed by carrying out thermal diffusion. Thereafter, LOCOS oxidation is executed and a semiconductor device such as a bipolar transistor wherein defect is reduced is acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar IC for element isolation by LOCOS technology.

[0002]

2. Description of the Related Art An example of a conventional method for manufacturing a bipolar IC is shown in FIGS. First, as shown in FIG. 5, an N-type impurity-embedded region 2 and a P-type impurity-embedded region 3 as an element isolation region are formed on a P-type silicon substrate 1, and then N
Type epitaxial silicon layer 4 is formed, the SiO ₂ film 6 is formed on the surface thereof by thermal oxidation, and the Si ₃ N ₄ film 7 is formed thereon.
Are formed (FIG. 5A).

Next, a resist is applied to the entire surface and LOCO is applied.
A resist pattern 9 for S (Local Oxidation of Silicon) is formed, and the Si ₃ N ₄ film 7 is formed by RIE (reactive ion etching) using the resist pattern 9 as a mask.
Is patterned (FIG. 5B). At this time, Si
The O ₂ film 6 is also slightly etched by RIE.

After that, the resist pattern 9 is removed,
Thermal oxidation is performed again in order to supplement the etched SiO ₂ film 6. After that, a resist is newly applied on the entire surface to form a resist pattern 10 for element isolation, and ions are implanted above the P-type impurity buried layer 3 through the SiO ₂ film 6 to form an ion implantation region 11 (FIG. 5). (C)).

After that, the resist pattern 10 is removed and LOCOS oxidation is performed at a high temperature (1000 ° C. or higher).
The COS SiO ₂ film 6a is formed (FIG. 6A), and the Si ₃ N ₄ film 7 as a mask is removed (FIG. 6B).

Thereafter, an annealing process is performed to diffuse the ion-implanted region 11 to form an impurity diffusion region 11a. The impurity diffusion region 11a partially overlaps the P-type impurity buried region 3 to form an element isolation region.

As another conventional method for manufacturing a bipolar IC, as shown in FIG. 7, the above-mentioned conventional example shown in FIG.
LOCOS oxidation is performed after the step shown by
A SiO ₂ film 6b is formed to form a resist pattern 9 and Si.
_{The 3} N ₄ film 7 is removed, a resist is applied on the entire surface, a resist pattern 12 for element isolation is formed, and ion implantation for element isolation is performed through the LOCOS SiO ₂ film 6b using the resist pattern 12 as a mask. The ion implantation region 13 is formed (FIG. 7A).

After that, the resist pattern 12 is removed,
Annealing is performed to diffuse the ion-implanted region 13 to form an impurity diffusion region 13a.

The impurity diffusion region 13a partially overlaps the P type impurity embedding region 3 to form an element isolation region as a P type diffusion layer.

[0010]

SUMMARY OF THE INVENTION Bipolar I described above.
In the first example of the conventional method of forming the element isolation region of C, LO
Ion (boron) implantation is performed before COS oxidation (Fig. 5).
(C)). Therefore, defects such as dislocation pits and OSFs (oxidation-induced stacking faults) occur when LOCOS-oxidizing the region after ion implantation (ion-implanted region 11) at a high temperature of 1000 ° C. or higher. In this method, Si ₃ a the Si ₃ N ₄ film 7 to form a mask for LOCOS during RIE etching
Since the SiO ₂ film 6 under the N ₄ film 7 is also etched to some extent,
It is necessary to thermally oxidize the supplemented portion of the etched SiO ₂ film 6 again.

Furthermore, in the second example of the conventional method for forming the element isolation region of the bipolar IC described above, as shown in FIG. 7A, the upper element isolation region is formed after the LOCOS SiO ₂ film 6b is formed. Is a LOCOS oxide film (SiO 2
₍₂ films) High energy ion implantation that can reach just under 6b is required. Furthermore, the annealing temperature after ion implantation must be increased, resulting in poor throughput.

In view of the above problems, it is an object of the present invention to provide a method of manufacturing a highly reliable semiconductor device in which the occurrence of defects in the element isolation region of a silicon substrate is reduced.

[0013]

In order to solve the above-mentioned problems, a method for manufacturing a semiconductor device according to a first aspect of the present invention is directed to a step of forming an element isolation region of one conductivity type in a silicon substrate, on the silicon substrate. A step of sequentially forming an oxide film and a nitride film, a step of forming a resist pattern on the nitride film, and using the resist pattern as a mask, impurity ions of the same conductivity type as one conductivity type are introduced into the silicon substrate through the nitride film and the oxide film. Implanting to form an ion-implanted region, removing the resist pattern, and then performing an annealing treatment to diffuse the ion-implanted region to form an upper element isolation region to be bonded to the element isolation region in the silicon substrate, nitride film And forming a nitride film pattern, and using the nitride film pattern as a mask to perform selective oxidation to form a LOCOS oxide film. The features.

A semiconductor device manufacturing method according to a second aspect of the present invention is characterized in that, in the first aspect, the impurity ions are implanted by a combination of medium and high energies.

Furthermore, a method of manufacturing a semiconductor device according to a third aspect of the present invention is the method of manufacturing the semiconductor device according to the first aspect, wherein the selective oxidation is performed.
It is characterized in that it is performed at a low temperature of about 0 ° C.

[0016]

According to the present invention, as shown in FIG. 1B, since the element isolation ion implantation is performed through the nitride film 27 on the silicon substrate (silicon layer) 24, high energy of about several hundred KeV and several tens of KeV. The intermediate energies can be combined in any order, and the total injection amount can be suppressed low. Therefore, the initial distribution of implanted ions becomes relatively deep in the silicon layer by the ion implantation using the medium and high energies, the thermal diffusion of the next process can be performed at a relatively low temperature in a short time, and the total ion implantation amount can be reduced. As a result, damage to the silicon substrate (layer) can be reduced.

Further, in the present invention, L is low at a low temperature of about 950.degree.
Since OCOS oxidation can be performed, the growth of defects can be suppressed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment in which the present invention is applied to manufacture of an NPN bipolar transistor will be described below with reference to the drawings. 1 and 2 are process cross-sectional views showing a method for manufacturing an NPN transistor according to the present invention. In the NPN transistor of the present invention, first, as shown in FIG. 1A, an N-type impurity buried region (diffusion layer) 22 and a P-type impurity buried region (diffusion layer) 23 are formed on a P-type silicon substrate 21, The epitaxial type epitaxial silicon layer 24 is grown and formed, and the surface of the N type epitaxial silicon layer 24 is thermally oxidized.
A SiO ₂ film 26 having a thickness of about 0 to 40 nm is formed, and a nitride film (Si ₃ N ₄ film) 27 having a thickness of about 40 to 60 nm is further formed by the CVD method.

Next, as shown in FIG. 1B, a resist pattern 29a for element isolation is formed by a photolithography process after applying a resist on the entire surface, and the Si ₃ N ₄ film is formed using the resist pattern 29a as a mask. 27, SiO
Ion implantation of boron (B ⁺ ) or the like is performed through the ₂ film 26 to form an ion implantation region 30. The energy used for this ion implantation is a combination of medium and high energies, for example, several hundred KeV + several tens KeV.

Compared to the case of ion implantation with energy of several tens KeV alone, when ion implantation is performed with a combination of medium and high energies as in this embodiment, the initial ion implantation distribution is a silicon substrate (N type epitaxial layer). Deepens at 24. Therefore, the heat diffusion step of the next step can be performed at a relatively low temperature in a short time (for example, 1000 ° C. for about 60 minutes),
Moreover, the total ion implantation amount can be suppressed to 1 × 10 ¹⁴ / cm ² or less. As a result, damage (damage) to the silicon substrate can be reduced, and the occurrence of defects during LOCOS oxidation can be prevented.

By implanting ions through the Si ₃ N ₄ film 27, a resist pattern 29 at the time of ion implantation is obtained.
It not only prevents knocking of act gas from a, but also prevents metal contamination. The resist pattern 29a is removed by chemical treatment such as ashing and sulfuric acid / hydrogen peroxide mixture.

Next, as shown in FIG. 1C, a plug-in region (PLG) for reducing collector extraction resistance is formed. First, after applying a resist, a PLG resist pattern 31 is formed by a photolithography process, and then P
⁺ Ion implantation energy 70 KeV to 200 KeV,
Ion implantation is performed at a dose of 10 ¹⁵ / cm ² to 10 ¹⁶ / cm ² to form a PLG ion implantation region 32. Ion implantation is not performed directly on the silicon layer 24, but on the Si ₃ N ₄ film 2
7, the damage to the silicon layer 24 during ion implantation can be reduced.

Therefore, the defects caused by the subsequent thermal diffusion thermal oxidation can be reduced. The resist pattern 31 is removed by the same method as described above. Since the ion implantation for forming the PLG region of the PNP transistor different from the NPN transistor of the present embodiment can be performed in the same step as the ion implantation for the element isolation region, the ion implantation for forming the PLG region is performed before the LOCOS formation. It can be carried out.

Next, as shown in FIG.
The impurity diffusion layers 30a, P
The LG diffusion layer 32a is formed. At this time, the Si ₃ N ₄ film 2
Since the diffusion is carried out in the presence of No. 7, it is not affected by the oxidation due to the atmospheric entrainment of the diffusion furnace. Then, a resist pattern 34 for LOCOS is formed by a photolithography process.
Then, the Si ₃ N ₄ film 27 is patterned by RIE and L
An OCOS pattern is formed. In this RIE process, S
Although a part of the SiO ₂ film 26 is etched together with the i ₃ N ₄ film 27, it is not necessary to re-grow an additional thin oxide film (20 to 40 nm) because the next step is LOCOS oxidation.

Next, after removing the resist pattern 34, as shown in FIG. 2B, thermal oxidation is performed at a low temperature of about 950 ° C. to form a LOCOS thermal oxide film 26a of about 600 nm. Since this LOCOS oxidation is performed at a low temperature, defects in the element isolation region 30a are reduced. This L
After the OCOS oxidation, the Si ₃ N ₄ film 27 is removed (see FIG.
(C)) An NPN bipolar transistor can be manufactured through a normal process.

FIG. 3 is a process sectional view showing a first application example of the present invention. In this application example, first, referring to FIG.
In the state shown in (b), that is, the Si ₃ N ₄ film 27 used for LOCOS formation is left as it is, and as shown in FIG. 3A, a base (Base) is formed by a photolithography process.
A region resist pattern 36 is formed, and ion implantation of the base is performed through the Si ₃ N ₄ film 27. In this ion implantation, if it is an NPN transistor similar to that of the above-described embodiment, P-type impurity ions such as B ⁺ , on the other hand, PNP.
If it is a transistor, N-type impurity ions such as P
⁺ , As ⁺ or the like is used and the implantation amount is set to about 10 ¹³ to 10 ¹⁵ / cm ² .

After ion implantation, thermal diffusion is performed at a temperature of about 900.degree. The Si ₃ N ₄ film 27 is removed by a chemical solution such as Hot phosphoric acid before or after the thermal diffusion. Figure 3
(B) shows a state in which the base region 40 is formed by performing thermal diffusion with the Si ₃ N ₄ film removed before thermal diffusion. In this application example, carbon-based contamination from the resist pattern 36 is knocked on to the emitter-base junction by performing ion implantation for the base region through the Si ₃ N ₄ film used for forming the LOCOS. To be prevented.

FIG. 4 is a process sectional view showing a second application example of the present invention. In the above embodiment, as shown in FIGS. 1C and 2A, the plug-in region (PLG) 39 is formed before forming the LOCOS oxide film (SiO ₂ film). However, if the NPN transistor, after forming the LOCOS oxide film as shown in FIG. 4, Si ₃ N ₄
After passing through the film or removing with a chemical solution such as Hot phosphoric acid (FIG. 4 shows an example after removing the Si ₃ N ₄ film), a resist pattern 38 for PLG is formed by a photolithography process and ion implantation ( For example, P ⁺ ions are implanted at an energy of 70 KeV to 200 KeV and an implantation dose of 10 ¹⁵ to 10 ¹⁶ /
(in cm ² ) is also conceivable. In this method PL
The G ion implantation region 39 can be formed in a self-aligned manner with respect to the LOCOS oxide film.

After PLG ion implantation, 100 for activation
Thermal diffusion is performed at a temperature of about 0 ° C. to form the PLG diffusion layer 39a. Unlike the present example, when the ions are implanted through the Si ₃ N ₄ film, the Si is injected before or after the thermal diffusion process.
_{The 3} N ₄ film is removed.

[0030]

As described above, according to the present invention,
In a semiconductor device such as a bipolar IC, ion implantation into a substrate for element isolation can be performed with a combination of medium and high energies, so that the total ion implantation amount can be reduced and the defects can be reduced accordingly. it can.

Further, in the present invention, since LOCOS oxidation can be performed at a low temperature (about 950 ° C.), defects in the element isolation region can be reduced. Moreover, in the present invention, since ion implantation can be performed through the Si ₃ N ₄ film, damage at the time of ion implantation can be reduced, and knock-on of outgas from the resist (pattern) and metal contamination can be prevented.

[Brief description of drawings]

FIG. 1 is a process sectional view (I) showing an embodiment of a method for manufacturing a semiconductor device (bipolar transistor) according to the present invention.

FIG. 2 is a process sectional view (II) showing an embodiment of a method for manufacturing a semiconductor device (bipolar transistor) according to the present invention.

FIG. 3 is a process sectional view showing a first application example of the present invention.

FIG. 4 is a process sectional view showing a second application example of the present invention.

FIG. 5 is a process sectional view (I) showing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a process sectional view (II) showing the conventional method for manufacturing a semiconductor device.

FIG. 7 is a process sectional view showing the method of manufacturing another conventional semiconductor device.

[Explanation of symbols]

1, 21 P-type silicon substrate 2, 22 N-type impurity buried region 3, 23 P-type impurity buried region (P-type diffusion layer) 4, 24 N-type epitaxial silicon layer 6, 26 SiO ₂ film 6a, 6b, 26a LOCOS SiO ₂ film 7,27 Si ₃ N ₄ film 9,10,12,29a, 38 resist pattern 11,13,30,34 ion implantation region 11a, 13a, 30a impurity diffusion region 31 PLG resist pattern 32 PLG ion implantation 32a, 39a PLG area (diffusion layer)

Claims (3)

[Claims] 1. A step of forming an element isolation region of one conductivity type in a silicon substrate, a step of sequentially forming an oxide film and a nitride film on the silicon substrate, a step of forming a resist pattern on the nitride film, A step of implanting impurity ions of the same conductivity type as the one conductivity type into the silicon substrate through the nitride film and the oxide film using the resist pattern as a mask to form an ion implantation region, and performing an annealing treatment after removing the resist pattern. A step of diffusing the ion-implanted area to form an upper element isolation region to be joined to an element isolation area in the silicon substrate, patterning the nitride film to form a nitride film pattern, masking the nitride film pattern Selective oxidation as
A method of manufacturing a semiconductor device, comprising the step of forming a COS oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity ions are implanted by a combination of medium and high energies. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the selective oxidation is performed at a low temperature of about 950 ° C.