JPH07319670A - Tree adder and multiplier - Google Patents

Abstract

PURPOSE:To provide a tree adder which is highly integrated and easily realizes the generation of an optional number of bits. CONSTITUTION:A cell 1 including a partial product generator and wires for shifting, a cell 2 including a partial product generator, a full-adder, and wires for shifting, a cell 3 including a unit adder and wires for fields, and a cell 4 including a half-adder are provided, and those cells 1-4 are arranged according to a specific arrangement algorithm to constitute tree adders 21 and 22. And, the full adder is included in the same cell with the partial product generator to increase the degree of integration of the tree adders 21 and 22, and since the tree adders 21 and 22 are constituted by using the specific arrangement algorithm, the tree adders consisting of the optional number of bits can easily be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tree adder and a multiplier for realizing high integration in a semiconductor integrated circuit and easily realizing generation of an arbitrary number of bits.

[0002]

2. Description of the Related Art In recent years, due to the development of CAD technology, LSI
In the case of realizing a circuit having a regularity such as a memory and a multiplier, a method of automatically generating from an arbitrary number of bits, a number of words, etc. has become the mainstream. To realize such a multiplier, Nikkei Electronics No. 1978.5.29, p.70-89 "L"
The carry save method described in "Looking at the circuit method of the multiplier by the parallel operation method which is progressing to SI" is usually adopted, and in order to realize high speed, the secondary booth described in the above document is used. The multiplier recoding method by the algorithm of is used. The carry-save method is suitable for automatic generation because of its high regularity, and is suitable for high integration of LSI because of its minimal wiring complexity, but has the drawback of slow operation speed. Therefore, in order to further increase the speed, the tree addition method is used instead of the carry save method, but there is a tendency that the regularity is reduced and the complexity due to the wiring is increased as the number of logic stages is reduced. As a tree addition method for maintaining the regularity and reducing the complexity due to wiring to realize high speed, there is disclosed in Japanese Patent Laid-Open No. 2-112.
There is a binary tree addition method described in Japanese Patent Laid-Open No. 020.

A tree adder of a 32-bit multiplier will be described below as an example of the conventional binary tree addition type multiplier with reference to the drawings.

FIG. 19 shows a structure of a tree adder of a conventional multiplier. In the figure, 201 to 216 are partial product generators, which generate 16 partial products by the second-order Booth algorithm. Reference numerals 221 to 236 denote complemented signal generators, which generate a complemented signal of each partial product. Two
51 to 257 are adders, and the adder 25 of the first stage
1, 252, 254 and 255 add four partial products, and thereafter, adders 253, 256 and 257 add binary partial products. 261, 271 to 274 are adders, which are added to add the partial products and the complemented signals of the partial products. The adder 251 shown in FIG.
~ 257 configuration is shown. Each of the adders 251 to 257 is configured by arranging unit adders 183 which receive four data and one carry respectively as inputs and output one sum and two carry in parallel by a required number of bits. The unit adder 183 can be configured by two stages of full adders using the full adders 181 and 182 as shown in the figure, but performs an equivalent operation.
It may be configured by an adder having three inputs and three outputs. Adder 26
1, 271 to 274 are configured by arranging full adders or half adders in parallel for a required number of bits.

The tree adder having the above-described structure is used as an LS.
A layout method to be realized on I will be described. As shown in FIG. 19, by using the second-order Booth's algorithm, the tree adder becomes a partial product generator 20.
1 to 216 are formed by shifting the adjacent partial product generators by 2 bits. As a result, the partial product generator 20
When 1 to 216 and adders 251 to 257 are arranged with their bit positions aligned, the tree adder has a parallelogram-shaped layout. However, since the layout on the LSI needs to be rectangular, it is divided into an upper bit tree adder 281 and a lower bit tree adder 282.
The layout is done so that it becomes a rectangle. Also,
Since the tree adder has regularity, it is laid out by dividing it into some 1-bit basic cells and arranging the basic cells. The tree adder for upper bits has a cell including a partial product generator and a cell including a unit adder as basic cells,
In the tree adder for lower bits, a cell including a full adder or a half adder and a cell including a unit adder are basic cells.

[0006]

However, in the above configuration, the unit adder at the first stage of the binary tree is 4
Since the basic cell including the partial product generator generates the partial products because it takes one partial product as an input, the basic cell for passing the maximum number of three partial products and the number of data necessary for forming the binary tree is passed. It is necessary to provide a wiring for feeding, and there is a problem that the area is increased by the wiring. Since the basic cell including the partial product generator is the basic cell of the upper-bit tree adder that occupies most of the area of the multiplier, the area of the entire multiplier is increased.

Therefore, an object of the present invention is to provide a tree adder which realizes high integration and easily realizes generation of an arbitrary number of bits.

[0008]

In order to solve the above problems, a tree adder according to the present invention comprises a first partial product generator and a first cell including a shift wiring, and a second partial product. A second cell including a generator, a first full adder, and a wiring for shifting, and a first unit adder which inputs four data and one carry and outputs one sum and two carry And a third cell including a wiring for feeding, and a fourth cell including a first half adder, and the total number of the first cell and the second cell arranged is n, and the number of partial products is If p1 is f1 (n) defined by (Equation 1) is 0 or 1, the first cell is arranged from the lower bit side to the upper bit side of the multiplier, and f1 (n) is 2 or 3 If so, the second cell is arranged from the lower bit side to the upper bit side of the multiplier, and n is set every time the first cell or the second cell is arranged. Increment by 1 and n is 8
If it is equal to a multiple of p or p, the third cells are arranged in succession by the number defined by f2 (n) in (Equation 2), and n is the p
If they are equal to each other, the cells 4 are successively arranged to finish the arrangement of cells in the bit direction of the multiplier, and the first cell and the second cell are arranged by the number of bits of the multiplicand so that adjacent cells are the same in the bit direction of the multiplicand. The third cell and the fourth cell are arranged side by side.

Another tree adder of the present invention is the second one.
6th cell including the full adder and the wiring for the feed, and
It is equipped with a second unit adder that inputs one data and one carry and outputs one sum and two carry, and a seventh cell that includes a wiring for feed, Let n be the number obtained by multiplying the number by 2 and then 1 and p be the number of partial products, and the 7th cell as many as the number defined by f2 (n) of the 6th cell and (Equation 2). The arranged cells are used as 1-bit addition cells. Two 1-bit addition cells are arranged from the lower bit side to the upper bit side, and n is set after arranging two 1-bit addition cells. The value is incremented by 1, and if n is equal to p + 1, the cell placement is completed.

[0010]

According to the present invention, with the above configuration, the first full adder of the tree adder adds three partial products, and then the second full adder adds one partial product to the first partial product. Four partial products are added by adding the two data output from the first-stage full adder. When divided into basic cells, it consists of a basic cell containing a partial product generator and a basic cell containing a partial product generator and a full adder, and these basic cells are the outputs of at most two partial products or full adders. And two wirings for feeding for passing the data necessary for forming the binary tree,
The number of wires can be reduced. As a result, the integration degree of the high-order bit tree adder, which occupies most of the area of the multiplier, can be increased.

Further, since the tree adder is constructed by arranging the basic cells by a specific arrangement algorithm, it is possible to easily realize the generation of the tree adder and the multiplier having an arbitrary number of bits.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A 32-bit multiplier will be described below as an example of a multiplier according to an embodiment of the present invention with reference to the drawings.

FIG. 1 shows the configuration of a tree adder of a multiplier according to the embodiment of the present invention. In FIG. 1, 1
Reference numerals 01 to 116 denote partial product generators, which generate 16 partial products by the second-order Booth algorithm. 121 ~
Reference numeral 136 denotes a complemented signal generator, which generates a complemented signal of each partial product. 141 to 148 and 151 to 153 are adders, and the first stage adders 141, 143, 145,
147 adds three partial products, and the second stage adders 142, 144, 146, and 148 add one partial product to the first partial product.
Add the two data output from the adder in the second stage,
After that, the adders 151 to 153 add the partial products in a binary tree shape. 161, 171-178 are adders,
This is an adder added to add a partial product and a complemented signal of a partial product. The adders 141 to 14 shown in FIG.
8 shows the configuration of No. 8. Each of the adders 141 to 148 is configured by arranging the full adders 184 in parallel by the required number of bits. FIG. 2 shows the configuration of the adders 151 to 153. Each of the adders 151 to 153 has four data and 1
A unit adder 183 that inputs one carry and outputs one sum and two carry is arranged in parallel by the required number of bits. The unit adder can be configured by two stages of full adders using the full adders 181, 182 as shown in the figure, but it may be configured by a 5-input 3-output adder that performs an equivalent operation. FIG. 4 shows the configuration of the adder 161. The adder 161 is configured by arranging half adders in parallel by the required number of bits. The adders 171 to 178 are configured by arranging full adders or half adders in parallel by the required number of bits.

The tree adder having the above-described structure is connected to the LS
A layout method to be realized on I will be described. As shown in FIG. 1, by using the second-order Booth's algorithm, the tree adder is a partial product generator 101.
˜116 are formed by shifting the adjacent partial product generators by 2 bits. As a result, the partial product generator 101
When 116 to 116 and adders 141 to 148 and 151 to 153 are arranged with their bit positions aligned, the tree adder has a parallelogram-shaped layout. However, in the layout on the LSI, it is divided into a tree adder 181 for upper bits and a tree adder 182 for lower bits, and the layout is performed so that it becomes a rectangle. The rectangular layout is realized by replacing a part of the feed wiring with a 2-bit shift wiring when the partial product generator and the adder are arranged with their bit positions aligned. Since the tree adder has regularity, it is laid out by dividing it into some 1-bit basic cells and arranging the basic cells.

FIG. 5 shows an example of the layout of the multiplier.
In the figure, reference numeral 23 is a multiplier recoding circuit according to the secondary Booth's algorithm, which performs recoding of the multiplier. 24
Is a code processing signal generation circuit, which generates a signal for performing the code processing of the partial product. Reference numeral 21 is a tree adder for upper bits, and 22 is a tree adder for lower bits. Using the recoding result of the multiplier recoding circuit 23, partial products are generated and partial products are added to perform partial sum and partial carry. Output. Reference numeral 25 denotes a carry propagation adder, which performs carry propagation addition of partial sum and partial carry output by the upper bit tree adder 21 and the lower bit tree adder 22, and outputs a product.

The upper bit tree adder is formed by arranging cells 1 to 5, and the lower bit tree adder is formed by arranging cells 6 to 8 and 10 to 12. The basic cells of the upper-bit tree adder and the lower-bit tree adder must have the same cell size in order to minimize the number of basic cells. Since the heights of the cells 1, 2 and 5 of the upper bit tree adder are equivalent to 2 bits of the lower bit tree adder, the heights of the cells 1, 2 and 5 are unified, The height of cells 6-8 of the tree adder is halved to cells 1, 2, 5. The height of the cell 3 of the tree adder for upper bits is aligned with the cells 10 and 11 of the tree adder for lower bits, and the height of the cell 4 of the tree adder for upper bits and the cell 12 of the tree adder for lower bits are increased. Arrange the same.

6 to 10 show the structure of the basic cell of the tree adder for upper bits. FIG. 6 shows a cell 1, which includes a partial product generator 31 and a wiring for 2-bit shift. Cell 1
Is the output of the multiplier recoding circuit BX1, BX2, BC and the multiplicand X1
And X2 which is the lower 1 bit of the multiplicand are input, the partial product generator 31 generates a partial product, and outputs the partial product to R5. Also, from T0
T4 is output to R4 to R0, L0 to L5 is output to R6 to R11, and L6 to L
11 is output to B5 to B0, and 2-bit shift is realized by arranging cells having similar wirings.

FIG. 7 shows a cell 2, which includes a partial product generator 32, a full adder 33, and wiring for 2-bit shift. Similarly to the cell 1, the cell 2 receives the partial products generated and T0 and T1 as inputs, performs addition by the full adder 33, and outputs the sum to R4 and the carry to R11. Also, output T2-T5 to R3-R0 and L0-L4 to R6.
.. to R10 and L6 to L11 to B0 to B5. By arranging cells having similar wirings, 2-bit shift is realized.

FIG. 8 shows a cell 3, which includes a unit adder 34 and a feed wiring. Cell 3 receives T0, T1, T2, T3, R0 as input, performs addition in the unit adder 34, outputs the sum to B1, outputs the carry to L0, L1, and outputs T4, T5 to B2, B3. , R1 to B
Output to 0.

FIG. 9 shows a cell 4 having a half adder 35. The cell 4 receives T0 and T1 as inputs, performs addition by the half adder 35, outputs the sum to B1, outputs the carry to L0, and outputs R0 to B0.

FIG. 10 shows a cell 5, which, like the cell 1, is provided with a partial product generator 36 and a wiring for 2-bit shift. The cell 5 has the wirings for outputting L6 to L11 in the cell 1 to B5 to B0 shifted, and the cell 5 sets B0 to a logical value of 0 to L7.
~ L11 is output to B5 ~ B1.

When cells 1 to 5 are arranged, X1, X2, BX1, BX2,
Connect BC to OX1, OX2, OBX1, OBX2, OBC respectively, and T0 to T5
Arrange adjacent cells so that B0 to B5 and L0 to L11 are connected to R0 to R11. If there are adjacent cells but there is no terminal to connect, arrange the cells without connecting them.

The layout of the tree adder for high-order bits is such that three partial products are added by the full adder at the first stage,
The partial adder in the second stage adds one partial product and the two data output from the full adder in the first stage, and is then divided into a binary tree with the unit adder as a constituent element. This is performed by arranging cells 1 to 5 so that the products are added and finally the half adder performs the addition.

FIG. 11 shows a flowchart of an arrangement algorithm of the cells 1 to 5 in the high-order tree adder. This placement algorithm will be described below.

First, supposing that the total number of the arranged cells 1, 2, and 5 is n and the number of partial products is p, the cells are arranged from the lower bit side to the upper bit side of the multiplier. If f1 (n) defined in (Equation 1) is 0 and n and p-1 are equal, cell 5 is arranged. If f1 (n) is 0 and n and p-1 are not equal, cell 1 is If f1 (n) is 1, cell 1 is arranged and f1 (n)
If is 2 or 3, cell 2 is arranged. Each time one cell is arranged, n is incremented by 1. n is 8
If it is equal to a multiple of or p, cells 3 are arranged by the number defined by f2 (n) in (Equation 2). If n is equal to p, the cells 4 are arranged, and the arrangement of cells in the bit direction of the multiplier is completed. Next, cells 1 to 5 are arranged by the number of bits of the multiplicand so that cells adjacent to each other in the bit direction of the multiplicand are the same, and the arrangement of the cells of the tree adder for higher bits is completed.

12 to 17 show the basic cells of the lower bit tree adder. FIG. 12 shows a cell 6, which includes a full adder 41 and a feed line. Cell 6 receives T0, T1 and T2 as inputs, performs addition in full adder 41, outputs the sum to B1, outputs the carry to L0, outputs T3 to T6 to B2 to B5, and R0 to B0.
Output to.

FIG. 13 shows a cell 7, which includes a unit adder 42 and a feed wiring. Cell 7 receives T0, T1, T2, T3, R0 as input, performs addition with the unit adder 42, outputs the sum to B1, outputs the carry to L0, L1, and outputs T4, T5 to B2, B3. , R1
Is output to B0.

FIG. 14 shows a cell 8 having a half adder 43 and a wiring for feed. The cell 8 receives T0 and T1 as input, performs addition by the half adder 43, outputs the sum to B1, outputs the carry to L0, outputs T2 to T5 to B2 to B5, and outputs R0 to B0.

FIG. 15, FIG. 16 and FIG. 17 show cell 1 respectively.
0, cell 11 and cell 12, which are provided with wiring for propagating the carry to the higher order. Cell 10 outputs R0 to T1,
B1 is output to T0 and B0 is output to L0. Cell 11 is R0, R1
To T1 and T0, and B0 and B1 to L1 and L0. Cell 12
Outputs R0 to T0.

When the cells 6 to 8 and the cells 10 to 12 are arranged, adjacent cells are arranged so that T0 to T5 are connected to B0 to B5 and L0 to L1 are connected to R0 to R1. If there are adjacent cells but there is no terminal to connect, arrange the cells without connecting them.

The layout of the tree adder for lower bits is such that the data output from the tree adder for upper bits and the complemented signal of the partial product are added, and subsequently, a binary tree shape including a unit adder as a constituent element. Is performed by arranging the cells 6 to 8 and 10 to 12 so that the data output from the high-order tree adder and the complemented signal of the partial product are added.

FIG. 18 shows a flow chart of an arrangement algorithm of the cells 6 to 8 and 10 to 12 in the lower bit tree adder. This placement algorithm will be described below.

First, assuming that the number of 1-bit addition cells arranged side by side is 2 + 1 and the number of partial products is p, cell placement is started from the lower bit side to the upper bit side. If f1 (n) defined in (Equation 1) is 1, cell 1 and the number of cells 7 defined by f2 (n) in (Equation 2) are arranged as a 1-bit addition cell, If f1 (n) is not 1, a 1-bit addition cell is formed by arranging the cells 6 and the number of cells 7 defined by f2 (n), and two 1-bit addition cells are arranged. After every two 1-bit addition cells are arranged, n is incremented by 1. If n-1 is a multiple of 8 or equal to p, the number of cells 11 and the number of cells 11 defined by f2 (n) are arranged as wiring cells, and the wiring cells are defined by f2 (n). Arrange as many as you want. If n-1 is equal to p, the cells 12 are arranged and the cell arrangement is completed.

In connecting the upper bit tree adder and the lower bit tree adder, the lower bit tree adder has an unconnected input, and normally the unconnected input is set to a logical value of 0.

As described above, according to this embodiment, the tree adder is configured by including the first and second full adders of the tree adder in the same basic cell as the partial product generator. Thus, the integration degree of the tree adder and the multiplier can be increased. Further, the tree adder is divided into a tree adder for upper bits and a tree adder for lower bits, and the tree adder is configured by arranging basic cells for each with a specific arrangement algorithm. The adder and the multiplier can be easily generated.

There is a cell 5 as a basic cell of a tree adder for upper bits, but this is for equalizing the number of stages of the adder in a binary tree. When the number of basic cells is reduced, the cell 5 is replaced with the cell 1. May be.

Similarly, there is a cell 8 as a basic cell of the tree adder for lower bits. This is to make the number of stages of the adder in the binary tree uniform. You may replace it.

In addition, in the connection of the tree adder for upper bits and the tree adder for lower bits, the unconnected input of the tree adder for lower bits has a logical value of 0. A low bit tree adder may be configured by adding a cell whose logical value is 0.

Further, when performing rounding processing, in the tree adder for high-order bits and the tree adder for low-order bits, data is placed at the bit position corresponding to the rounding position in the unconnected inputs of the low-bit tree adder. Round by inputting.

[0040]

As described above, according to the present invention, the tree adder is configured by including the full adders of the first and second stages of the tree adder in the same basic cell as the partial product generator. , Tree adders and multipliers can be integrated.
Further, since the tree adder is configured by arranging the basic cells by a specific arrangement algorithm, it is possible to easily realize the generation of the tree adder and the multiplier having an arbitrary number of bits.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a tree adder of a multiplier according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an adder used in the tree adder in the embodiment.

FIG. 3 is a configuration diagram of an adder used in the tree adder in the embodiment.

FIG. 4 is a configuration diagram of an adder used in the tree adder in the embodiment.

FIG. 5 is a layout diagram of a multiplier in the embodiment.

FIG. 6 is a configuration diagram of a basic cell of a tree adder for high-order bits in the embodiment.

FIG. 7 is a block diagram of a basic cell of a tree adder for high-order bits in the embodiment.

FIG. 8 is a configuration diagram of a basic cell of a tree adder for high-order bits in the embodiment.

FIG. 9 is a block diagram of a basic cell of a tree adder for upper bits in the embodiment.

FIG. 10 is a block diagram of a basic cell of a tree adder for high-order bits in the embodiment.

FIG. 11 is a flowchart showing an arrangement algorithm of a high-order tree adder in the same embodiment.

FIG. 12 is a block diagram of a basic cell of a tree adder for lower bits in the embodiment.

FIG. 13 is a block diagram of a basic cell of a tree adder for lower bits in the same embodiment.

FIG. 14 is a configuration diagram of a basic cell of a tree adder for lower bits in the same embodiment.

FIG. 15 is a configuration diagram of a basic cell of a lower-order tree adder in the same embodiment.

FIG. 16 is a block diagram of a basic cell of a tree adder for lower bits in the embodiment.

FIG. 17 is a block diagram of a basic cell of a tree adder for lower bits in the embodiment.

FIG. 18 is a flowchart showing an arrangement algorithm of a lower-bit tree adder in the embodiment.

FIG. 19 is a configuration diagram of a tree adder of a conventional multiplier.

[Explanation of symbols]

1-5 Basic cell of upper-bit tree adder 6-8, 10-12 Basic cell of lower-bit tree adder 21, 181, 281 Upper-bit tree adder 22, 182, 282 Lower-bit tree adder 23 multiplier recoding circuit 24 code processing signal generation circuit 25 carry propagation adder 31, 32, 36 partial product generator (1 bit) 33, 41, 181, 182, 184 full adder 34, 42, 183 unit adder 35 , 43, 185 Half adders 101-116, 201-216 Partial product generators 121-136, 221-236 Complementized signal generators 141-148, 151-153, 161, 171-1
78, 251-257, 261, 271-274 adder

Claims (5)

[Claims] 1. A first cell including a first partial product generator and a shift wiring, and a second cell including a second partial product generator, a first full adder and a shift wiring. And a third unit including a feed unit and a first unit adder that inputs four data and one carry and outputs one sum and two carry
And a fourth cell including a first half adder, where n is the total number of the first cells and the second cells arranged side by side and p is the number of partial products, ) Defined by
If f1 (n) is 0 or 1, the first cells are arranged from the lower bit side to the higher bit side of the multiplier, and f1 (n) is 2
Or 3, if the second cells are arranged from the lower bit side to the upper bit side of the multiplier, the n is incremented by 1 after the first cells or the second cells are arranged. If the n is a multiple of 8 or equal to the p, the third cells are sequentially arranged by the number defined by f2 (n) in (Equation 2),
Is equal to the p, the cells 4 are successively arranged to complete the arrangement of cells in the bit direction of the multiplier, and the first cells are arranged by the number of bits of the multiplicand so that adjacent cells in the bit direction of the multiplicand are the same. A tree adder in which the second cell, the third cell, and the fourth cell are arranged. [Equation 1] [Equation 2] 2. The output of the first cell is shifted to output 1
A fifth cell in which one of them has a logical value 0, and f1 (n) is 0
The tree adder according to claim 1, wherein the first cell is replaced with the fifth cell and arranged when the n is equal to p-1. 3. A sixth cell including a second full adder and a feed line, and a second unit which inputs four data and one carry and outputs one sum and two carry. A seventh cell including an adder and a feed line is provided, and after multiplying the number of aligned 1-bit addition cells by 2, it becomes 1
Where n is the number of partial products and p is the number of partial products, the 6th cell and the number of the 7th cells arranged by the number defined by f2 (n) of (Equation 2) As the cells for addition, two 1-bit addition cells are arranged from the low-order bit side to the high-order bit side, and each time the two 1-bit addition cells are arranged, n is incremented by 1, and A tree adder characterized by terminating cell placement if the value obtained by subtracting 1 from n is equal to p. 4. An eighth cell comprising a second half adder and a feed line, wherein when the f1 (n) is 0, the sixth cell is replaced with the eighth cell. The tree adder according to claim 3, wherein 5. A multiplier comprising the tree adder according to claim 1 or 2, and the tree adder according to claim 3 or 4.