JPH01103739A - Parallel multiplying circuit - Google Patents

Abstract

PURPOSE:To reduce the number of passing gates of a carry to quickly perform logical operation processing by outputting a negative logic carry to the last stage of a ripple carry type parallel multiplying circuit and providing an adder which inverts a negative logic to a positive logic in the high-order bit side. CONSTITUTION:Partial products between multiplicands X1-X4 and multipliers Y1-Y4 are obtained by AND gates and are inputted to full adders FA or half adders HA of the next stage. A positive logic carry is inputted to a full adder FA 31 in the last stage and a negative logic carry is outputted from this full adder, and the negative logic carry is inputted to a next full adder FA 32 and positive logic carries P7 and P8 are outputted from this full adder to the external. Consequently, the number of passing gates is reduced by one in each of adders FA 31 and FA 32 to shorten the signal passage time by a time corresponding to passing of two gates in the carry propagation route, and the processing is quickly performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ripple carry type parallel multiplier circuit.

[Conventional technology]

A multiplier is one of the most basic circuits in a digital arithmetic processing device, along with adders and delay circuits. Also,
It is becoming increasingly important as a basic circuit for digital filters, fast Fourier transforms, and digital PLL circuits that are essential for digital signal processing (DSP). The multiplication algorithm can be roughly divided into ■ multiplicand (ll1uH1plicant) and multiplier (ll1uH1plicant).
1ult1pHer) is multiplied in parallel and then shifted and added ■Series-parallel multiplication method that inputs the multiplicand in series, inputs the multiplier, and performs the multiplication in series ■Inputs both the multiplicand and multiplier in series, and multiplies them in series Pipeline calculation method that calculates % formula % According to the parallel multiplication method, it is possible to speed up several times compared to the serial multiplication method, but it has the disadvantage that more circuits are required for the calculation. Therefore, in the past, it was difficult to integrate them into ICs, but with recent advances in device technology, multipliers have become mainstream.

In this parallel multiplication circuit, a partial product of a multiplicand and a multiplier is first obtained using an AND gate or the like, and the product is obtained by sequentially adding these partial products. A typical method for adding partial products is a so-called carry-save method as shown in FIG.

FIG. 5(a) is a block diagram of a 4.times.4-bit parallel multiplication circuit using the carry-save method, and FIG. 5(b) shows a circuit in which partial products are determined using an inverter and a NOR gate. In the same figure (a), AND (not shown)
The results of addition of partial products by the gates are obtained by the full adder FA and the half adder HA, forming a critical path shown by the thick arrow in FIG. In such a parallel multiplication circuit, for example, the full adder FA shown in FIG. 5(a) is constituted by an AND/NOR gate as shown in FIG. 6. Here, carry C is inverted by inverter 1 and then AND
/NOR gate 2 to the next full adder FA.

[Problem that the invention seeks to solve]

Since the conventional circuit is configured as described above, signal propagation in the critical path is performed only by positive logic. That is, a positive logic carry is input to the full adder, and the positive logic carry is propagated to the next full adder. For this reason, gates such as the inverter 1 shown in FIG. 6 are required for each, and the number of gates through which carries pass in the critical path increases. As the number of passing gates increases, the signal propagation time becomes longer, resulting in slower logical operation processing.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a parallel multiplication circuit that can speed up logical operation processing by shortening the carry propagation time in the critical path.

= 3 - [Means for solving the problem] The parallel multiplication circuit according to the present invention shifts and adds the multiplicand multiplied by the multiplier in parallel, and in the final stage transfers the carry from the lower bit adder to the upper bit. In a ripple carry type parallel multiplication circuit in which bits are sequentially propagated to an adder, at least the final stage is a first stage that outputs a carry of negative logic.
, and on the upper bit side of this first adder,
It is characterized in that a second adder is provided which inputs a negative logic carry and outputs a positive logic carry.

[Effect]

According to the configuration of the present invention, carry propagation in the final stage is performed by inverting positive logic and negative logic, so the number of gates through which carry passes in the critical path can be reduced.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 to 4 of the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

FIG. 1(a) is a block diagram of a 4×4 bit parallel multiplication circuit using a carry-save method according to a first embodiment of the present invention.

The difference from the conventional example in FIG. 5(a) is that the full adder FA (31, 32) in the final stage inputs a positive logic carry, as shown by the broken line in the figure. The first one outputs a negative logic carry, and the second one inputs a negative logic carry and outputs a positive logic carry.

FIG. 2 is a detailed configuration diagram of such a full adder FA. FIG. 2A shows a first type of full adder, which inputs a positive logic carry C and outputs a negative logic carry C from an AND/NOR gate 20. On the other hand, the figure (b) shows a second type of full adder, which inputs a negative logic carry and an AN
A positive logic carry C is output from the D/NOR gate 21. As is clear from FIG. 2, there is no inverter on the critical path (carry propagation path), and therefore the number of gates through which carries pass is reduced accordingly. In addition, A in the same figure.

B is the data to be added (partial product), and S is the result (sum).

Next, the operation of the parallel multiplication circuit shown in FIG. 1(a) will be explained.

In the figure, the partial products of the multiplicand x −x and the multipliers y1 to y4 are obtained by an AND gate (not shown), and are input to the first stage full adder FA or half adder HA as data A and B to be added. Ru.

Then, the result (sum) is given as data to be added to the next-stage full adder FA or half adder HA, and when there is a carry, a carry C of "1" is output.

Here, the final stage full adder FA (31) inputs a positive logic carry and outputs a negative logic carry, and the next full adder FA (32) inputs a negative logic carry and outputs a negative logic carry. Outputs a logical carry. Therefore, when there is a carry in the full adder FA (31), a carry of "0" is output, and when there is no carry, a carry of "1" is output. The final stage full adder FA (32) receives the negative logic carry from the full adder FA (31), the addition result from the previous stage, and A (not shown).
Addition is performed based on partial products x4y4 by ND gates, etc., and outputs P and Pg are supplied to the outside.

In this way, in the circuit of FIG. 1(a), the full adder FA (3
In 1), by inputting a positive logic carry and outputting a negative logic carry, the number of gates is reduced by one, and the F of the full adder is
A In (32), the number of gates is reduced by one by inputting a negative logic carry and outputting a positive logic carry, so a total of two gates (
(inverter) will be reduced. Therefore, the speed can be increased by the time required for a signal to pass through two gates.

Note that the circuit in Figure 1(b) uses an inverter and a NOR gate to obtain partial products, but the carry propagation method in the final stage (repeating positive and negative logic) is the same as that in Figure 1(a). It is similar to Therefore, the same effect as that shown in FIG. 3(a) can be achieved.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a diagram showing its overall configuration. The difference from the first embodiment described above is that the first full adder F in the final stage inputs a carry of "0" and outputs a carry of positive logic.
It is composed of A. In this way, all of the parallel multiplier circuits can be constructed from full adders, making it easier to design a circuit pattern on a semiconductor substrate, for example.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, the final stage adder may be replaced with a type that outputs a negative logic carry. Specifically, Figure 1 (a
The half adder HA shown in ) and (b) is configured with an inverter 1 on the critical bus as shown in FIG. Replace with a half adder HA that outputs a carry. In this case, 2
The th full adder FA must input a negative logic carry and output a positive logic carry, as shown in FIG. 2(b). Furthermore, in the case of FIGS. 3(a) and 3(b), the first full adder FA may be configured to output a negative logic carry as shown in FIG. 2(a).

Furthermore, an adder that inputs a carry by changing the positive/negative logic may be provided not only in the final stage but also in the middle.

However, since the signal propagation time on the critical path in the final stage has the greatest effect on the calculation speed, it is still the most effective to do as in the embodiment. Further, the specific configurations of the full adder FA and half adder HA are as follows.
Data A and B to be added are not limited to AND/NOR gates as shown in FIGS. 4 and 6, but also for half adders.
Various configurations are possible, such as outputting it as an inverted carry through a NAND gate.

Furthermore, when a negative logic carry is output from the last full adder, an inverter may be provided here.

〔Effect of the invention〕

As explained above in detail, according to the present invention, carry propagation in the final stage is performed by inverting positive logic and negative logic, so the number of carry pass gates on the critical bus can be reduced. By shortening the carry propagation time in the critical path, there is an effect of speeding up logical operation processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a parallel multiplier circuit according to a first embodiment of the present invention, FIG. 2 is a detailed block diagram of a full adder shown in FIG. 1, and FIG. 3 is a block diagram of a parallel multiplier circuit according to a second embodiment of the present invention. 4 is a detailed configuration diagram of a half adder, FIG. 5 is a configuration diagram of a conventional parallel multiplier circuit, and FIG. 6 is a detailed configuration diagram of a full adder shown in FIG. 5. It is a diagram. FA...Full adder, HA...Half adder. Patent applicant Sumitomo Electric Industries Co., Ltd. Representative patent attorney

Claims (1)

[Claims] 1. A ripple carry in which a multiplicand multiplied by a multiplier in parallel is shifted and added, and in the final stage, the carry is sequentially propagated from an adder for lower bits to an adder for upper bits. In a parallel multiplication circuit of the form, at least the final stage includes a first adder that outputs a negative logic carry, and a negative logic carry is input to the upper bit side of the first adder to output a positive logic carry. A parallel multiplication circuit characterized in that a second adder outputting a carry is provided. 2. The parallel multiplier circuit according to claim 1, wherein the first and second adders are constituted by AND/NOR gates.