JPH07319669A - Window-managed image blending circuit and weighted mean circuit used for the same - Google Patents

Abstract

PURPOSE:To provide a superior window-managed image blending circuit which can set the blending rate with a small write information amount by blending superposed images into a translucent image in an area where windows overlap with each other when an information processor displays plural windows. CONSTITUTION:By pixel position information including the pixel clock of a pixel position information supply device 101, 1st and 2nd image memories 102 and 103 output respective pixels and a counter 105 is placed in counting operation, and, respective blending rates are read out of the counter 105 and a blending rate buffer 106, and those blending rates are selected by a data selector 107 with the control signal read out of an attribute buffer 108 and inputted to a pixel blending device 104, which puts pixels from the 1st and 2nd image memories 102 and 103 together into the translucent image at the blending rates or selects them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image blend circuit which is window-managed so that a semi-transparent composite image can be displayed in a window overlapping portion on a display screen in a multi-window type information processing apparatus and an image blend circuit thereof. It relates to an improvement of the weighted average circuit which is provided and has the function of actually blending two images.

[0002]

2. Description of the Related Art In recent years, in an information processing apparatus such as a personal computer or a workstation, information such as a plurality of documents is displayed on a rectangular display screen by using a plurality of windows, each of which is a rectangular area, and it is sufficient for an operator. Information is provided. Recently, a moving image signal such as a video signal is input to an information processing apparatus and displayed on a window.

In the above conventional information processing apparatus, when two windows overlap each other, the upper and lower relations of the windows are set and the contents of the upper window are displayed in the overlapping area. Therefore, the contents of the lower window are hidden and invisible, and the amount of information that can be displayed is limited by the size of the screen. In addition, in order to see the contents of the lower window, complicated operations such as changing the settings of the vertical relations of the windows and moving one of the windows are required.

In order to solve this problem, for example, it is conceivable to introduce a conventional translucent image synthesizing method in the field of television broadcasting into a multi-window type information processing apparatus. That is, the blend ratio α (0 ≦ α ≦ 1) is stored in the blend ratio buffer for each pixel over the entire display screen, and the blend ratio α is read from the blend ratio buffer for each pixel of the display screen to obtain two values. The pixels A and B of the window are blended by the pixel blending device according to α × A + (1−α) × B. If an image blending circuit including such a blend ratio buffer and a pixel blending device is introduced into a multi-window information processing device, a semitransparent composite image can be displayed in a window overlapping portion on the display screen. Moreover, since the blend ratio can be arbitrarily set on a pixel-by-pixel basis, the flexibility of setting the blend ratio is high.

A specific configuration of a circuit for blending two pixels in the image blending device, that is, a weighted average circuit will be described. This weight average circuit has conventionally been classified into three types.

In the first method, as shown in FIG. 46, two multipliers 632 and 63 are used to perform the calculation according to the above-mentioned calculation formula.
This is a method of blending images by being configured by three and one adder 634.

In the second method, as shown in FIG. 47, the calculation formula is modified into α × (A−B) + B, and a subtractor 635, a multiplier 636 and an adder 63 are used to calculate this.
This is a method of blending images by providing one 7 for each.

The third method is, as shown in FIG. 48, one adder circuit 638 and n (four in the figure) selectors 6.
39 to 642 are provided, and weights corresponding to the number of the selectors are 1/2, 1/4, ... 1 with respect to the adder circuit 638.
It is set so as to form a geometrical sequence with a common ratio of 1/2 in n ways of / 2 ⁿ , and one of the values of the inputs A and B expressed in a binary number is selected by each of the n selectors 639 to 642. After doing
In the adder circuit, the selected n values are respectively multiplied by the corresponding weights of the adder circuit (hereinafter, the multiplication with this weight is referred to as weighting), and the n multiplication results are added to obtain a total. Then, the image is blended.

[0009]

However, in the conventional image blending circuit, the blending ratio is set for each pixel constituting the entire screen of the display screen. You can set a large number of different types of images, and although the flexibility of image display is high,
When updating the blend ratio, it is necessary to update each blend ratio one by one from the first one to the last one in the window, and there is a problem that the blend ratio cannot be changed at high speed. As a result, there is a drawback that the response to an operation such as moving the window becomes slow. This disadvantage is that the blend ratio is expressed in binary when the number of steps of the change of the blend ratio is increased and the width of the change is reduced so that the change of the semi-transparent image when the blend ratio is changed smoothly progresses. This becomes more noticeable because the number of bits required to do so increases, and the responsiveness of updating the blend ratio is further reduced.

In the conventional weighted average circuit,
Since the first method uses two multipliers, there is a drawback that the circuit scale becomes large.

Further, in the second method, the number of multipliers is only one, and the circuit scale is a little small. However, because of the use of the subtractor, a negative number is expressed and transmitted in the middle of the circuit. Since there is a power point and an operation corresponding to a negative number is performed at this point, the circuit becomes a little complicated and the number of stages of the operation circuit is large, so the calculation time is long (specifically, the signal propagation delay is large. ), There is a drawback that the operation speed becomes slow.

In addition, in the third method, although it is composed of a selector and a multi-input adder circuit, the circuit scale and the operating speed of these components are the same as one multiplier. Although it is very excellent, the output value does not actually match exactly with α × A + (1-α) xB, and K × {α × A +
Since (1−α) xB} (K = (2 ⁿ −1) / 2 ^n, which is a value slightly smaller than 1), the video signal has a serious drawback of reduced brightness.

In any of the above methods, when the blend ratio α is α = 1 or α = 0, that is, when the blending of a plurality of input signals is unnecessary, any one of the input signals is input. Although it is sufficient to select and output as it is, the calculation is performed based on the blend ratio. Therefore, there is a drawback that wasteful power consumption is consumed and power consumption is increased.

Further, in the third method, when the number of bits of the blend ratio α is increased so that the value of the blend ratio α can be specified in fine intervals, and the number of bits of the adder circuit is increased accordingly, When the blending ratio of a multi-bit number expression is specified, the same blending operation may actually be performed even with a blending ratio of a small bit number expression. The disadvantage is that it consumes unnecessary power.

The present invention has been made in view of the above points, and an object of the window management image blending circuit of the present invention is to realize a high-speed response such as movement of a window that is semitransparently synthesized, It is an object of the present invention to provide a window managed image blending circuit which is preferably used in a multi-window information processing apparatus for the first time by effectively utilizing a display screen by transparent composition.

Further, an object of the weighted average circuit of the present invention is that the circuit scale and the operation speed are substantially the same as those of one multiplier, that is, the third method is basically adopted, and a plurality of circuits are accurately operated. The purpose is to blend input signals such as video signals to suppress a decrease in image brightness.

Further, another object of the weighted average circuit of the present invention is that when the blend ratio is a value equal to selecting any one input signal, the adder circuit is not operated and the power consumption is reduced accordingly. It is to try to realize.

In addition, another object of the weighted average circuit of the present invention is to add circuits in which the blending of a plurality of input signals at a predetermined blend ratio can be calculated in a portion of the adding circuit having a relatively small number of bits. It is intended to reduce the power consumption by not operating the redundant portion of the above.

[0019]

In order to achieve the above object in the window managed image blending circuit, the present invention provides a window management image blending circuit in which a blending ratio is set for each pixel over the entire display screen. Not only the blend ratio buffer means for storing the blend ratio is further provided, but the blend ratio holding means for storing one blend ratio is further provided, and one blend ratio stored by the blend ratio holding means is used for a plurality of pixels in the window overlapping portion. It will be used for the semi-transparent composition of.

In order to achieve the above object of the weighted average circuit, in the present invention, in the image blending device, by appropriately setting each weight in the addition circuit, input signals such as a plurality of video signals are accurately blended. To do.

Further, in order to achieve the above-mentioned other object of the weighted averaging circuit, in the present invention, when the blend ratio is a value equal to selecting any one of the input signals, a constant value is given to the adding circuit. A selection circuit that stops the operation and selects one of the plurality of input signals is provided.

In addition, in order to achieve the above-mentioned other object in the weighted average circuit, the present invention provides two adder circuits so that a plurality of input signals can be blended at a predetermined blend ratio in a relatively bit-wise manner. If the calculation can be performed using a small number of parts, the blending is executed only by one of the adder circuits.

Specifically, the solution means taken by the invention according to claim 1 is a window-managed image so that a translucent composite image can be displayed in a window overlapping portion on a display screen in a multi-window type information processing apparatus. A blending circuit, a pixel position information supplying means for outputting pixel position information including a pixel clock for synchronization so that an image is displayed on the display screen by a raster scan method, and the display screen, respectively. A plurality of image output means for sequentially outputting pixel information of images having the same size according to the pixel position information, and blend ratio information set for each pixel of the display screen are stored and stored. Blending ratio buffer means for sequentially outputting the blending ratio information according to the pixel position information One blend ratio information is stored, blend ratio holding means for repeatedly outputting the stored blend ratio information according to the pixel position information, and selection information set for each pixel of the display screen is stored. Whichever of the attribute buffer means for sequentially outputting the stored selection information according to the pixel position information, the blend ratio information from the blend ratio buffer means and the blend ratio information from the blend ratio holding means. The pixel position from each of the plurality of image output means and the blend ratio information from the data selection means, and the pixel position based on the pixel position. Synchronous input according to the information, and the input blend ratio information Pixel blending means for blending and outputting pixel information input from each of the plurality of image output means, and the plurality of pixel blending means for displaying the target image in each of the plurality of windows on the display screen. The position, shape size, and display target of each window are stored as management information of each window, the management information is updated according to an instruction from an operator, and the blend ratio is stored in correspondence with the stored management information. A buffer means and window management means for configuring and updating the stored contents of the attribute buffer means are provided.

According to a second aspect of the present invention, in the multi-window information processing device, there is provided a window managed image blending circuit capable of displaying a semi-transparent composite image in a window overlapping portion on a display screen. Pixel position information supplying means for outputting pixel position information including a pixel clock for synchronization so that an image is displayed on the display screen by a raster scan method, and an image having the same size as that of the display screen. A plurality of image output means for sequentially outputting the pixel information in accordance with the pixel position information, and the blend ratio information set for each pixel of the display screen is stored, and the stored blend ratio information is stored in the pixel. Blend ratio buffer means for sequentially outputting according to position information, and one blend Ratio information is stored and blend ratio holding means for repeatedly outputting the stored blend ratio information in accordance with the pixel position information, and a pixel ratio corresponding to the window arrangement on the display screen are set for each pixel area. From the blend ratio buffer means, window information storage means for storing selection information, selection information output means for sequentially outputting the selection information stored in the window information storage means in accordance with the pixel position information, From either one of the blend ratio information and the blend ratio information from the blend ratio holding means, a data selection means for selectively outputting according to the selection information from the selection information output means, and each of the plurality of image output means. And the blending ratio information from the data selecting means are used as the pixel position information. Pixel blending means for synchronously inputting the pixel information and blending and outputting pixel information input from each of the plurality of image output means according to the input blend ratio information, and a plurality of pixel blending means on the display screen. In order to display the target video in each of the windows, the position of each window, the shape dimension and the display target are stored as management information of each of the plurality of windows, and the management information is updated according to the instruction of the operator, Further, a window management means for configuring and updating the storage contents of the blend ratio buffer means and the window information storage means corresponding to the stored management information is provided.

Further, in the invention according to claim 3, the blend ratio holding means of the invention according to claim 1 or 2 is specified, and further one stored blend ratio information is stored in accordance with the pixel position information. It is configured to include means for automatically updating each time a certain period of time elapses.

In addition, in the invention of claim 4, the pixel blending means of the invention of claim 1 or 2 is specified,
It is configured to include a plurality of weight averaging means for blending pixel information input from each of the plurality of image output means for each color component, each of the plurality of weight averaging means,
j expressed as an i-ary number where i, j, and m are integers of 2 or more
Signals are input, the j signals are respectively multiplied by the weights corresponding to the j inputs, the respective multiplication results are added, and the addition result is regarded as a signal expressed in i-adic number. The adding means for outputting and j selecting means for selecting one from the m digital input signals expressed in i-adic number are provided, and the j signals respectively selected by the j selecting means. Is input to the adding means, a blend ratio is given, and a control means is provided for controlling the j selecting means so as to mix m digital input signals with the given blend ratio, J of adding means
The total sum of the weights is set to be an integral multiple of the integer i of the maximum weight value among the j weights.

According to the invention of claim 5, the pixel blending means of the invention of claim 1 or 2 is specified,
Further, a plurality of weight averaging means for blending the pixel information input from each of the plurality of image output means for each color component is provided, and each of the plurality of weight averaging means is i,
When j and m are integers of 2 or more, j signals expressed in an i-ary number are input, and the j signals are multiplied by weights respectively corresponding to the j inputs, and the multiplication results are obtained. Are added and the addition result is output as a signal expressed in i-adic notation, and j first first selecting one from the m digital input signals and constant value signals expressed in i-adic notation. Selecting means, the j signals respectively selected by the j first selecting means are input to the adding means, and the output signal of the adding circuit and the m signal are added.
A second selecting means for selecting and outputting one of the digital input signals, and the sum of the j weights of the adding means is the maximum value of the j weights. The weight value is set to an integral multiple of the integer i, and
A blending ratio is given, and a control means for controlling the j selecting means and one second selecting means is provided according to the given blending ratio.

Further, in the invention of claim 6, the pixel blending means of the invention of claim 1 or 2 is specified, and the pixel information input from each of the plurality of image output means is blended for each color component. A plurality of load averaging means are provided, each of the plurality of load averaging means i, j, m, n
Is an integer of 2 or more, k is a natural number, and a first set of signals consisting of k signals expressed in i-adic numbers and a second set of jk (j> k) signals expressed in i-adic numbers , J signals with the signals of the set are input, the j signals are respectively multiplied by the weights corresponding to the j inputs, the respective multiplication results are added, and the addition result is The apparatus further comprises a first adding means for outputting as a signal expressed in i-adic notation and k third selecting means for selecting one from m digital input signals expressed in i-adic notation. The k signals respectively selected by the third selecting means are input to the first adding means as the signals of the first set, and the n signals expressed in i-adic number are input, and the n signals are input. The signals are multiplied by the weights corresponding to the n inputs, and the multiplication results are added. , Second adding means for outputting the addition result as jk signals expressed in i-adic number, and jk corresponding to the number of output signals of the second adding means, and the corresponding The output signal of the second adding means and the fourth selecting means for selecting one from the m digital input signals, and j selected by the jk fourth selecting means. -K signals are input to the first adding means as the second set of signals, and n signals are selected from the m digital input signals and i-adic constant value signals. No. 5 signals are selected by the n number of fifth selecting means, the n signals are input to the second adding means, a blend ratio is given, and m digital inputs are provided. J to mix signals at the given blend ratio It is a equipped with a control means for controlling the selection means structure.

In addition, in the invention according to claim 7, the data selecting means of the invention according to claim 1 or 2 is specified,
In addition to the blend ratio information from the blend ratio buffer means and the blend ratio holding means, a function of selectively outputting fixed blend ratio information is further provided.

According to the weighted average circuit of the invention described in claim 8,
j expressed as an i-ary number where i, j, and m are integers of 2 or more
Signals are input, the j signals are respectively multiplied by the weights corresponding to the j inputs, the respective multiplication results are added, and the addition result is regarded as a signal expressed in i-adic number. The adding means for outputting and j selecting means for selecting one from the m digital input signals expressed in i-adic number are provided, and the j signals respectively selected by the j selecting means. Is input to the adding means, a blend ratio is given, and a control means is provided for controlling the j selecting means so as to mix m digital input signals with the given blend ratio, J of adding means
The sum of the weights is set to be an integral multiple of the integer i of the maximum weight value among the j weights.

Further, in the invention described in claim 9, the sum total of j weights of the addition means of the invention described in claim 8 is limited to one.

Further, in the weighted average circuit of the tenth aspect of the present invention, j signals expressed in i-adic notation are input with i, j, and m being integers of 2 or more, and the j signals are input to the j signals. Each of the j inputs is multiplied by a corresponding weight, each multiplication result is added, and the addition result is output as a signal expressed in i-adic notation, and m expressed in i-adic notation.
And j first selecting means for selecting one from among the digital input signals and the constant value signals, wherein the j signals respectively selected by the j first selecting means are It is provided with one second selecting means which is inputted to the adding means and which selects and outputs one from the output signal of the adding circuit and the m digital input signals, and j of the adding means. The sum of the weights is set to be an integral multiple of the integer i of the value of the maximum weight among the j weights, and a blend ratio is given, and the blend ratio is given according to the given blend ratio. The j first selection means and 1
A control means for controlling the second selection means is provided.

In addition, in the weighted averaging circuit of the present invention as defined in claim 11, i, j, m, n are integers of 2 or more, k is a natural number, and the first signal is composed of k signals expressed in i-adic numbers. Signal of the group of j and the signal of the second group consisting of jk (j> k) signals expressed in i-adic number are input, and the j signals are respectively inputted to the j signals. First input means for multiplying the respective inputs by corresponding weights, adding the respective multiplication results, and outputting the addition result as a signal expressed in i-adic notation, and m digital values expressed in i-adic notation. And k third selecting means for selecting one from the input signals, and k selected by the k third selecting means.
Number of signals are input to the first adding means as the first set of signals, n number of signals expressed in i-adic number are input, and each of the n number of signals is input to the n number of inputs. Corresponding to second adding means for multiplying respective corresponding weights, adding the respective multiplication results, and outputting the addition result as jk signals expressed in i-adic notation, and the second adding means. And a fourth selection means for selecting one from the output signal of the corresponding second addition means and the m digital input signals corresponding thereto. Fourth
The jk signals respectively selected by the selecting means are input to the first adding means as the second set of signals,
It comprises n number of fifth selecting means for selecting one from the m number of digital input signals and a constant value signal expressed in i-adic number, and is selected by each of the n number of fifth selecting means. Control means for controlling the j selection means so that n signals are input to the second addition means, a blend ratio is given, and m digital input signals are mixed at the given blend ratio. Is provided.

In addition, in the invention of claim 12, in the weighted average circuit according to claim 8, 9, 10 or 11, the output signal of the adding means or the first adding means represents the output signal thereof. The number of digits has been reduced from the minimum to a predetermined number,
The adding means or the first adding means is limited to the configuration for outputting the approximate value of the addition result.

According to a thirteenth aspect of the present invention, in the weighted average circuit according to the eighth, ninth, tenth, eleventh or twelfth aspect, the integer i is i = 2.

According to a fourteenth aspect of the present invention, in the weighted average circuit of the thirteenth aspect, when the value of the maximum digit among the digits to be reduced is "0", the value is truncated, and the maximum digit is reduced. The value is incremented when the value is "1".

Further, in the invention according to claim 15, in the weighted average circuit according to claim 13, each weight of the adding means or the first adding means is a sequence in which the weights are arranged in descending order. Except for the last term of the above, a geometric progression having a common ratio of 1/2 is formed, and the value of the last term of the sequence is equal to the value of the term immediately before the last term.

In addition, in the invention according to claim 16, in the weighted average circuit according to claim 13, the adding means or the first adding means is an input signal of the adding means or the first adding means. Number of signals, and outputs the addition result as two binary-displayed signals, and the two output signals of the first partial addition circuit are added, and the addition result is converted into one. A second partial adder circuit for outputting a binary-represented signal, and the output signal of the second partial adder circuit is the output of the adder means or the first adder means, and the first part The adder circuit is configured by connecting a plurality of carry-save adders in series, and the second partial adder circuit inputs from the least significant bit to a predetermined intermediate bit of the second partial adder circuit. Add the signals,
A first carry propagation adder for outputting the addition result and a carry result generated from the intermediate bit; and a case where the carry result of the first carry propagation adder is assumed to be 0, A carry carry adder for adding input signals of bits higher than the intermediate bit of the second partial adder circuit and outputting a result of the addition, and a carry carry for the first carry propagate adder. The second, assuming the result is 1.
The carry result of the third carry propagation adder for adding the input signals of the bits higher than the intermediate bit of the partial adder circuit and outputting the addition result and the carry result of the first carry propagation adder are 0. When the output of the second carry propagation adder is selected, and when the carry result is 1, the output of the third carry propagation adder is selected and output. It is configured as follows.

According to a seventeenth aspect of the invention, in the weighted average circuit of the tenth aspect, the integer i is i = 2.
And the adding means is the input signal j of the adding means.
Number of signals, and outputs the addition result as two binary-displayed signals, and the two output signals of the first partial addition circuit are added, and the addition result is converted into one. A second partial adder circuit for outputting a binary-represented signal, the output signal of the second partial adder circuit being the output of the adding means, and the first partial adder circuit having a plurality of outputs. A plurality of carry save adders are connected in series, and the second partial adder circuit adds input signals from the least significant bit to a predetermined intermediate bit of the second partial adder circuit, A first carry propagation adder for outputting an addition result and a carry result generated from the intermediate bit;
When the carry result of the first carry propagation adder is assumed to be 0, the input signals of the bits higher than the intermediate bit of the second partial adder circuit are added, and the addition result is output. Of the second carry propagation adder and the carry carry adder of the first carry propagation adder, which are higher than the intermediate bit of the second partial adder circuit. And a third carry propagation adder that adds input signals and outputs the addition result,
The second selection means includes a seventh selection means for selecting one from the m digital input signals, an output indicating an addition result of the first carry propagation adder, and a seventh selection means for the seventh selection means. Eighth selection means for selecting one of the least significant bit to the intermediate bit of the output, the output of the second carry propagation adder, and the third carry propagation adder. Any one of the output and the part of the bit higher than the intermediate bit in the output of the seventh selecting means is selected to constitute the ninth selecting means.

Further, in the invention according to claim 18, in the weighted average circuit according to claim 11, the number of signals (jk) belonging to the second set is two.

In addition, in the invention according to claim 19, in the weighted average circuit according to claim 18, the integer i is i =
2 and each weight of the first adding means is a geometric sequence having a common ratio of 1/2, except for the last term of the first sequence, in which the respective weights are arranged in descending order. And the value of the first term of this first sequence is 1/2, the value of the last term of the first sequence is equal to the value of the term immediately before its last term,
The weights of the last two terms of the first sequence are each multiplied by each of the two signals of the second set, and each weight of the second summing means is a second of the respective weights arranged in descending order. The sequence of numbers forms a geometric sequence with a common ratio of 1/2, except for the last term of the second number sequence, and the value of the first term of this second number sequence is the value of the last term of the first number sequence. The value of the last term of the second sequence is equal to the value of the immediately preceding term.

According to a twentieth aspect of the invention, in the weighted average circuit according to the nineteenth aspect, integers j, m, and n are used.
Are j = 6, m = 2, and n = 5, respectively.

Further, in the invention described in claim 21, in the weighted average circuit according to claim 10, the control means is limited, and the control means is instructed to mix digital signals having a given blend ratio of m. If so, the first selection circuit selects any one of the m digital signals and the second selection means selects the output of the first addition circuit. Controlling the selection means and the second selection means such that the first selection means selects a constant value if the given blend ratio is equivalent to selecting any one of the m digital signals. , The second selecting means controls the first selecting means and the second selecting means so as to select the instructed one of the m digital input signals.

In addition, in the invention described in claim 22, in the weighted average circuit according to claim 10, the control means is:
When an operation selection signal for selecting and instructing either operation or stop of the second adding means is input, and the operation selecting signal is a signal for selecting the operation of the second adding means,
All of the fourth selecting means select the output of the second adding means, and the third selecting means and the fifth selecting means each output 1 out of m digital input signals according to the given blend ratio. If the operation selection signal is a signal for selecting the stop of the second adding circuit, all of the fifth selecting means select the constant value signal. , The third selecting means and the fourth selecting means are configured to control each of the selecting means so as to select one of the m digital input signals according to the given blending ratio.

Further, in the invention of claim 23, in the weighted average circuit according to claim 8, 9, 10 or 11, each selecting means inputs a selection control signal, and the selected selection control signal is inputted to the selection control signal. One of the plurality of signals is selected according to the control signal, and the control unit is composed of a decoder to which a code describing the blend ratio is input, and the decoder outputs to each selection unit according to the input code. It is configured to generate a selection control signal.

Further, in the invention according to claim 24, in the weighted average circuit according to claim 23, the decoder selects the operation or stop of the second adding means and outputs the operation selection signal. Instead of the input, the operation selection signal is generated based on the input code.

[0047]

With the above construction, in the window managed image blending circuit according to claim 1, since all the pixels to be displayed are associated with the blending ratio stored in the blending ratio holding means or blending ratio buffer means, When an overlap occurs, the window management unit updates the contents of the blend ratio buffer unit and the attribute buffer unit, and sets the pixels in the overlapping region to perform the semi-transparent blending. Semi-transparent composition.

Then, if the value of the attribute buffer means of the overlapping portion is set so that the value stored in the blend ratio holding means is selected as the blending ratio of the overlapping portion, the overlapping portion is moved or deformed by moving the window. For this, the content of the attribute buffer means may be updated, and the number of bits per pixel of the attribute buffer means may be smaller than that of the blend ratio buffer means, so writing is performed rather than updating the content of the blend ratio buffer means. The amount of data is small. Further, when changing the blend ratio of the overlapping portion, it suffices to rewrite the value of the blend ratio holding means. Therefore, the above object is achieved.

In the window managed image blending circuit according to the second aspect of the present invention, the window information storage means and the selection information output means are adopted instead of the attribute buffer means, so that it is possible to cope with the movement or deformation of the window. The data to be updated in this way is a small amount of data regarding the moved or modified window in the window information storage means.

Further, in the window-managed image blending circuit of the present invention as defined in claim 3, the blending ratio holding means smoothly and automatically adjusts the blending ratio for translucent composition without rewriting the blending ratio information one by one. Change over time.

In addition, in the window managed image blending circuit of the present invention as defined in claim 7, some constant values can be selected for the value of the blend ratio selected by the data selecting means. By providing a value instructing to select one of the pixels sent from the plurality of image output means, that is, the semitransparent synthesis is not performed, the blend ratio buffer means is provided for the region where the semitransparent synthesis is not performed. When the value of is used as the blend ratio, the blend ratio buffer means need not be initialized, and only the attribute buffer means and the blend ratio holding means need be initialized, so that the amount of data to be rewritten is further reduced.

Further, in the weighted average circuit of the present invention according to claim 4, claim 8, claim 9, claim 13 and claim 15, the sum of each weight is an integer i of the maximum value among the values of all weights. It is set to an integer multiple of. The fact that the sum of the weights is an integral multiple of the integer i of the maximum value among the values of all the weights and that the sum of the weights is 1 is equivalent as a constraint condition when configuring the circuit. Indicates that there is. Since the weighting is performed by shifting the digit position, the maximum value of the weight can be expressed as 1 / i ^m, and when the sum of the weights is i ^s times the maximum value of the weight, the value becomes i ^(sm) and the output The value of is i ^(sm) × {α ×
A + (1-α) xB}. Here, the position of the decimal point of the output value can be freely determined, and the output value can be multiplied by an integer multiple of i, so that the output value is α × A +
The position of the decimal point can be determined so as to be (1-α) xB. In this case, to the output (only by shifting the digit position)
It can be regarded as being multiplied by the coefficient of i ^(ms) , but this is the same even if it is considered that all the weights of the input are multiplied by i ^(ms) . In this way, the circuit configuration remains unchanged,
By reviewing the digit positions of the weights, it is possible to redetermine the value of each weight so that the total sum of the weights becomes 1. Conversely, when the sum of weights is 1, it is the maximum weight value 1
Since / i ^m is i ^m times, the sum of the weights satisfies the condition that the maximum value of the weights is an integral multiple of the integer i. Therefore, that the total sum of weights is an integral multiple of the integer i of the maximum value of the weights and that the total sum of weights is 1 is equivalent as a constraint condition when configuring the circuit.

Therefore, claim 4, claim 8, claim 9,
In the weighted average circuit of the invention of claims 13 and 15, the sum of weights is set to an integral multiple of the integer i of the value of the maximum weight among the j weights, and the sum of weights is calculated. Since it can be set to 1, it is possible to accurately calculate α × A + (1-α) xB and prevent a decrease in brightness. Moreover, since the configuration of the present invention basically employs the third method, the circuit scale and operation speed are the same as one multiplier composed of an AND gate (multiplication for each bit) and a multi-input adder circuit. To have. Therefore,
The above object is achieved.

Further, claim 5, claim 10, claim 21.
In the weighted average circuit according to the twenty-second aspect of the present invention, when the digital input signal is selected and output, the second
If the output is determined by the selecting means and the constant value is input to all the inputs of the adding circuit, the input of the adding circuit is constant and constant even if the digital input signal changes. Therefore, the AC power consumption of the adder circuit becomes zero, the power consumption is reduced, and the other object of the present invention is achieved.

In addition, claim 6, claim 11, claim 1
In the weighted averaging circuit according to the present invention, the third and fourth selecting means are respectively provided in the first adding circuit when the blending ratio can be realized by the sum of only relatively large weights. Since one of the m digital input signals is selected and added to the input of, and all of the fifth selecting means select a constant value, the operation of the second adding circuit is stopped,
The power consumption can be reduced. On the other hand, when it is necessary to add inputs having small weights to realize a given blend ratio, all of the fourth selecting means select the output of the second adding circuit. And a second adder circuit is configured, and the third select means and the fifth select means select one from the m digital input signals, and Since it is equivalent to giving each input of one adder circuit and performing the addition operation in this one adder circuit, it is possible to specify the blending ratio with fine precision.

Further, in the weighted average circuit according to the invention of claims 12 and 14, the error is-(L / 2-d) ≤ε≤L / 2 because the rounding is performed at a predetermined intermediate digit. If the error ε is assumed to be uniformly distributed, the average value is d
/ 2, and the error and its average value are reduced.

Further, in the weighted average circuit according to the sixteenth and seventeenth aspects of the present invention, since the adder circuit is constituted by the carry select adder circuit, the delay time spent for carry propagation is reduced and the operating speed is increased. In addition to being faster, the delay time can be further delayed by changing the configuration of the selecting means, and the operating speed can be further accelerated.

Further, in the weighted averaging circuit according to the twenty-third and twenty-fourth aspects of the present invention, the decoder has a function of converting the sign of the fixed point binary number representing the blend ratio into the selection control signal supplied to each selection means. Since it has, it is possible to select a code that is easy to handle.

[0059]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Image Blending Circuit) FIG.
FIG. 3 is a configuration diagram of an image blending circuit managed by a window according to the present embodiment. In the figure, 100 is a pixel position information supply device, 102 and 103 are first and second image memories,
104 is the pixel blending device, 105 is a counter, 1
Reference numeral 06 is a blend ratio buffer, 107 is a data selector, 108 is an attribute buffer, and 109 is a central processing unit. In addition, in FIG. 1, a thick solid line with a bit width added indicates a pixel or information transfer corresponding to the pixel,
The dotted line represents the transfer of pixel position information including the pixel clock, and the thin solid line represents the transfer of other information. FIG. 2 shows a function table of the data selector 107.

FIG. 3 shows a block diagram of the pixel blending device 4. In the figure, 111 to 113 are first to third weighted average circuits, and 114 is a D flip-flop (D-F / F).
Is. FIG. 5 shows a configuration diagram of the weight averaging circuits 111 to 113. Details of the configuration of the figure will be described later, and in brief, here, 201 is an adder circuit, 202 to 206 are selectors arranged on the input side of the adder circuit 201, and 282 is a decoder.

The operation of the window-managed image blending circuit configured as described above will be described.

In this embodiment, a screen having a size of 1152 pixels in the horizontal direction and 900 pixels in the vertical direction is used as a rectangular screen for display. However, the display device having this screen and its control device are not shown in the figure. The digital RGB pixel signal output from the pixel blending device 104 is converted into an analog video signal by a display control device including a D / A converter and sent to the display device.

The pixel position information supply device 101 generates and outputs pixel position information including a pixel clock for sequentially transferring the information in which the pixels displayed on the screen are digitized by the raster scan method. In the raster scan method, one row of 1152 pixels is displayed in the horizontal direction in order from left to right, and then one row below it is displayed from left to right, for example. After displaying the bottom row,
Display back to the top row. In this way, the transfer of the pixels on the screen in order is repeated. In this raster scan method, the display position is distant from the display of the rightmost pixel in one column to the display of the leftmost pixel in the next column. Is required and is called the horizontal blank period. During this period, the pixel information is not transferred or is not displayed even if it is transferred. Further, it is also called a vertical blank period because it is also a delimiter for data transfer of one screen until the bottom one column is displayed and the top one column is displayed. The pixel position information supply device 101 outputs, as pixel position information, a signal indicating a horizontal blank period and a signal indicating a vertical blank period in addition to the pixel clock. The frequency of the pixel clock is 20 MHz.

First and second image memories 102, 10
3, the counter 105, the blend ratio buffer 106, and the attribute buffer 108 receive the pixel clock, the signal indicating the horizontal blank period, and the signal indicating the vertical blank period, and synchronously output information corresponding to the pixel at the same position. To do. The output timing of the pixel at a certain position is determined by counting the pixel clock and the change in the signal indicating the horizontal blank period and the signal indicating the vertical blank period.

First and second image memories 102 and 103
Outputs pixel information of an image having the same size as the screen of the display device. In this embodiment, the pixels of the image are the three primary colors of light: red (red), green (green), and blue (blue).
The strength of each component (hereinafter referred to as RGB) is represented by 24-bit digital information in which each bit is represented by an 8-bit unsigned binary integer. First and second image memories 102, 1
When the pixel output device 03 does not blend with the pixel blending device 104, either one is selected and displayed, and the other is not displayed. In that case, the pixel information may be an appropriate dummy value. For example, in the second image memory 103, when a signal of a video image captured by a video camera is digitized and captured and output, due to the resolution of the video signal and the displayed size, it is smaller than 1152 horizontal pixels × 900 vertical pixels. It can be considered to be included in the size.
In that case, the second image memory 103 may output dummy data when outputting pixels in a region other than the region assigned to the captured video camera image.

The pixel blending device 104 includes the first and second
The two systems of RGB pixel data that are transferred in synchronization from the image memories 102 and 103 are blended according to the blending ratio that is input in synchronization with them, and the pixel as a blending result is output. The blend ratio is a 5-bit fixed point binary number in this embodiment. The most significant bit is the ones digit. However, such a 5-bit fixed-point binary number can take a value larger than 1, but a value exceeding 1 is strange as a blend ratio. Therefore, when the fixed-point binary number is 1 or more, the blend ratio becomes 1. Shall be. The value of the given blend ratio is α, the value of an arbitrary color component of RGB of the output of the first image memory 2 is A, and the value of the same color component of the output of the second image memory 3 is B. Then, the pixel blending device 104 calculates α × A + (1−α) × B (1). However, since each component of the output value is also 8 bits, the value after the decimal point of the expression (1) is truncated and output.

Inside the pixel blending device 104, FIG.
As shown in, the first weighted average circuit 111 for the red component, the second weighted average circuit 112 for the green component, and the third weighted average circuit 113 for the blue component, according to the common blend ratio, the formula (1 ) Is calculated. Since the time required to calculate the formula (1) varies depending on the value of the blend ratio, the weighted average circuits 111 to 113
The output of is once received by the D flip-flop 114,
It is output so that the timing becomes constant regardless of the value of the blend ratio.

Each of the weight average circuits 111 to 113
Calculates the equation (1) with the configuration shown in FIG. Details thereof will be described later, and briefly described below, when the value of the blend ratio α is between 1 and 0, the addition circuit 201 and the input selectors 202 to 206 perform the calculation of the equation (1), The addition result is output from the addition circuit 201.

In this way, the pixel blending device 104
As a result, a composite image of the image output from the first image memory 102 and the image output from the second image memory 103 is generated. Each pixel of this composite image corresponds to the first image memory 1
02, a pixel output from the second image memory 103, or a semi-transparent composite pixel of both.

The blend ratio supplied to the pixel blend device 104 is generated by the counter 105, the blend ratio buffer 106, the data selector 107, and the attribute buffer 108.

The counter 105 stores the value of the blend ratio written by the central processing unit 109 and constantly sends the stored value to the data selector 107. Central processing unit 1
From 09, an initial value, an end value, and a speed are designated, and by receiving an instruction, for example, a signal indicating a vertical blank period is counted and automatically changed. If no instruction is received, the register holds a constant value.

The blend ratio buffer 106 stores a blend ratio value corresponding to each pixel on the screen of the display device. That is, 1152 × 900 blend ratios are stored. This makes it possible to realize an arbitrary blend ratio distribution on the screen. The blend ratio data in the blend ratio buffer 106 is sequentially read according to the pixel position information including the pixel clock and sent to the data selector 107.

The data selector 107 selects either the value output by the counter 105 or the value output by the blend ratio buffer 106 for each pixel according to the control signal sent from the attribute buffer 108, and outputs the selected value to the pixel blending device 104. .

The attribute buffer 108 determines whether the value of the control signal given to the data selector 107, that is, the output of the counter 105 or the output of the blend ratio buffer 106 is used as the blend ratio corresponding to each pixel. It is stored in a base number and sequentially outputs the control signal of a 1-bit binary number to the data selector 107 according to the pixel position information including the pixel clock.

The central processing unit 109 updates the contents of the blend ratio buffer 106 and the attribute buffer 108 according to the window operation of the operator.

Next, the operation when a window is displayed on the screen will be described.

Set the coordinates on the display screen to the upper left corner.
As (0,0), the position moved x pixels to the right and y pixels downward is
It is expressed as (x, y). As an example for explanation, the position and size of the window to be set are shown in FIG. In the figure, 125 to 127 are first to third areas, and 130 is a display screen. First to third areas 125-1
27 are display screens 30 with vertical and horizontal sides
It is a rectangular area parallel to. The first region 125 has a size of 480 with the upper left end at (50,50) and the lower right end at (529,349).
This is an area of × 300. The second area 126 has an upper left corner.
(450,400), the size of the lower right corner is (1089,879) 640 ×
It is an area of 480. The third area 127 has the upper left corner (3
00,200), the size of the lower right corner is (939,679) 640 × 4
There are 80 areas.

In FIG. 6, the fourth area 128 is an area where the first area 125 and the third area 127 overlap, and the size 230 is such that the upper left end is (300,200) and the lower right end is (529,349). This is a region of × 150. Fifth region 129
Is a region where the second region 126 and the third region 127 overlap, and the upper left end is (450,400) and the lower right end is (939,679).
It is a region of size 490 × 280.

Here, the first and second image memories 10
Reference numerals 2 and 103 store images corresponding to the display screen and output the pixels. Now, the document 131 is displayed in the first area 125 as shown in FIG.
It is assumed that the pattern 132 is displayed in the area 126 of 1. and the image composed of the document 131 and the pattern 132 is stored in the first image memory 102 and output as shown in FIG. The content of the blend ratio buffer 106 is a blend ratio of 1 for all pixels on the display screen 130. (If this blend ratio is simply arranged in a 2-digit hexadecimal number (originally 5 bits) on the display screen 130, As shown in FIG. 8, the contents of the attribute buffer 108 are the blend ratio buffer 1 for all pixels on the display screen 130 as shown in FIG.
The value 0 is an instruction to select the output of 06. As a result, the data selector 107 causes the blend ratio buffer 10
6, the pixel blending device 104 selects the output of the first image memory 102 for all the pixels and sends it to the display device. In this case, the value of the blend ratio stored in the counter 105 is not referred to.

Next, when the window in which the design 132 is displayed is moved to the third area 127, the document 131 and the design 1
Since 32 duplications occur in the fourth region 128,
As shown in FIG. 9, in the area 128, the document 131 and the design 132
And are semi-transparent. Explaining the operation of the semi-transparent composition, the portion of the pattern 132 that has moved to the fourth area 128 is not overwritten on the portion of the document 131 on the area 128, as shown in FIG. Then, the data is transferred to the portion of the second image memory 103 corresponding to the area 128. Thus, there is a portion of the document 131 in the area 128 of the images stored in the first image memory 102, and the area 12 of the images stored in the second image memory 103.
Since 8 has a part of the pattern 132, if the blend ratio is set to a value between 0 and 1 when the pixels of the regions 128 of the first and second image memories 102 and 103 are simultaneously output, As shown in FIG. 9, in the area 128, the document 131 and the pattern 132
Is semi-transparent.

At this time, there are two methods for setting the blend ratio in the fourth region 128 to a value between 0 and 1. One is a method of changing the contents of the area 28 of the blend ratio buffer 106 without changing the contents of the attribute buffer 108. 230 × 150 × 5 = 172,50
It is necessary to write 0-bit data. The other is that the content of the blend ratio buffer 106 is not changed,
A value between 0 and 1 is set in the counter 105, and the contents of the area 128 of the attribute buffer 108 are set in the counter 10
It is a method to change the output of 5 to the selected value, 230 ×
Since it is necessary to write data of 150 × 1 = 34,500 bits, one-fifth the data writing of the method of changing the content of the blend ratio buffer 106 is sufficient.

Therefore, in the present embodiment, as shown in FIG. 10, the content of the blend ratio buffer 106 is the blend ratio 1 for the pixels excluding the region 128 on the display screen 130 (the blend ratio shown in the same figure). Is a simple two-digit hexadecimal display similar to the blending ratio in Fig. 8. Since the pixels in the area 128 are not referred to, any value may be used as shown by hatching in the drawing), counter As shown in FIG. 10, the value of the blend ratio stored in 105 is 08 in the same simple 2-digit hexadecimal display as described above. The contents of the attribute buffer 108 are stored in the area 12 on the display screen 130 as shown in FIG.
The value 0 is an instruction to select the output of the blend ratio buffer 106 for pixels other than 8, and the value 1 is an instruction to select an output of the counter 105 in the area 128. As a result, the data selector 107 selects the output of the blend ratio buffer 106 for the area other than the area 128 on the display screen 130 as shown in FIG.
At 28, the output of the counter 105 is selected. as a result,
The pixel blending device 104 uses the first image memory 10 in the pixels excluding the area 128 on the display screen 130.
The output of 2 is selected, the output of the first image memory 102 and the output of the second image memory 103 are semitransparently synthesized in the pixels of the region 128, and the result is sent to the display device.

As shown in FIG. 9, of the 1152 × 900 = 1,036,800 pixels of the display screen 130, the area 128
230 × 150 = 34,500 pixels, the weighted average circuit 111 provided inside the pixel blending device 104 is used when blending is performed with a blending ratio between 0 and 1.
Each of the adder circuits 201 in each of
It operates only while the pixel of is output. Assuming that there is no power consumption when not operating, 34,500 / 1,036,800 × 100 = 3.3% of the power consumption when operating for all pixels is sufficient.

Further, by activating the counting operation of the counter 105, the blend ratio in the case of performing the semi-transparent composition can be gradually changed even if the central processing unit 109 does not come to write data one by one. Therefore, the smooth change of the blend ratio can be realized without burdening the central processing unit 109. When a moving image such as a video signal is displayed, scenes and channels can be switched by a change that gives a soft image. Even when the windows of the still images are overlapped as shown in FIG. 9, if the blend ratio is smoothly changed at an appropriate speed and the information of the overlapping portion is alternately displayed, the blend ratio is constantly displayed. The display contents are easy to read, and the eyes are less tired than when the display is switched instantaneously and alternately displayed.

(Second Embodiment of Image Blending Circuit) A second embodiment of the image blending circuit of the present invention will be described with reference to the drawings.

FIG. 11 shows the second part of the image blending circuit of the present invention.
It is a block diagram of the Example of. In the figure, 133 is a 2-bit selection input data selector, and 134 is a 2-bit output attribute buffer. The same components as those in FIG. 1 are designated by the same reference numerals. FIG. 12 shows a function table of the data selector 133.

In this embodiment, the data selector 107 of the first embodiment is selected and outputted from the output of the counter 105, the output of the blend ratio buffer 106, and the other two fixed blend ratios. 1
33, and the control signal of the data selector 133 is 2
Since it is a bit, the attribute buffer 108
This is replaced with an attribute buffer 134 that stores a 2-bit control signal for one pixel. Figure 1
As can be seen from 2, the value of the two fixed blend ratios is 0.
And 1. Therefore, the blend ratio is selected from four values obtained by adding two constant values to the output of the counter 105 and the output of the blend ratio buffer 106 by controlling the value of the attribute buffer 134 for each pixel. The other operation is the same as that of the first embodiment of the image blending circuit.

In the image blending circuit of the first embodiment, in the display state in which the translucent composition is not performed as shown in FIG. 7, the pixel blending device 104 makes the first image memory 1
Blend ratio buffer 1 to select 02 output
06 stores the value 1 for all pixels. Therefore, until the information display device including the image blending circuit is turned on and the display state as shown in FIG. 7 is entered,
It is necessary to write the values of all the pixels in the blend ratio buffer 106 once. This is 1152 x 900 x 5
= Write 5,184,000 bits of data.

On the other hand, in the image blend circuit of this embodiment, as shown in FIG.
Since 3 can select the value 1 of the blend ratio as a constant, in order to give the value 1 of the blend ratio to all the displayed pixels, the values corresponding to all the pixels of the attribute buffer 134 are set to binary numbers. 11, the blend ratio buffer 106 does not need to be rewritten as shown in FIG. Therefore, 1
152 × 900 × 2 = 2,037,600 bits of data can be written, and 2/5 data can be written.

When two pieces of information overlap only in a partial area 128 on the display screen 130 as shown in FIG. 9, the area excluding the area 128 on the display screen 130 as shown in FIG. To set the value of the attribute buffer 134 to binary 11, select the blending ratio value 1 with the data selector 133, select the output of the first image memory 102 with the pixel blending device 104, and display the display screen 130. In the area 128, the value of the attribute buffer 134 is set to binary 01, the data selector 133 is caused to select the blend ratio value 08 of the counter 105, and the pixel blending device 104 outputs the first image memory 102 and the second image. Memory 103
And the output of are combined with the blend ratio 08.

As described above, according to the second embodiment,
By replacing the 1-bit selection input data selector 107 of the first embodiment with the 2-bit selection input data selector 133 and replacing the attribute buffer 108 with the 2-bit output attribute buffer 134, a window corresponding to the window is obtained. When setting the blend ratio, the amount of data to be written can be smaller.

(Third Embodiment of Image Blending Circuit) A third embodiment of the image blending circuit of the present invention will be described below with reference to the drawings.

FIG. 15 is a block diagram of the third embodiment of the present invention. In FIG. 15, 135 is a window information storage device and 136 is a control signal determination device. The same components as those in FIG. 11 are designated by the same reference numerals.

In this embodiment, the attribute buffer 134 in the second embodiment is replaced with a window information storage device 135 and a control signal determining device 136.

The window information storage device 135 stores the selection of coordinates, priority (overlap information), and blend ratio of each window to be displayed. For example, the storage information of the window information storage device 135 in the states of FIGS. 7 and 9 is as shown in the tables of FIGS. 16 and 17, respectively. However, the information in the remarks column in FIGS. 16 and 17 does not need to be stored in the window information storage device 135. The information stored in the window information storage device 135 is always referred to by the control signal determination device 136.

The control signal determining device 136 receives the pixel clock, the signal indicating the horizontal blank period and the signal indicating the vertical blank period from the pixel position information supplying device 101, and counts the signal indicating the horizontal blank period and the pixel clock. And calculate the coordinates of the transferred pixel. This coordinate is compared with the coordinate of each window stored in the window information storage device 135 to determine in which window the pixel to be transferred is included. When it is included in two or more windows, it is included in the window having the highest priority. The control signal determination device 136 determines and outputs the control signal of the data selector 133 by selecting the blend ratio of the window thus determined. The contents of this output are displayed on the display screen shown in FIG.
It is the same as FIG. 13 and FIG. 14 both in the case of FIG. 9 where there is information overlap and in the case where there is no information overlap.

The information stored in the window information storage device 135 must be the only one window determined to be included in all the coordinates on the screen. That is, when the coordinates are included in two or more windows, only one window has the highest priority. The central processing unit 109 must obey this restriction when setting windows and updating the storage contents of the window information storage device 135.

Each window stored in the window information storage device 135 (corresponding to one row of data in the tables of FIGS. 16 and 17) does not necessarily match the window as a unit operated by the operator. For example, in the display state of FIG. 9, there are two windows as units operated by the operator: the document 131 displayed in the first area 125 and the pattern 132 displayed in the third area 127. However, in addition to these, the window information storage device 135 needs the root window representing the entire screen and the window data corresponding to the overlapping portion corresponding to the fourth area 128, and stores the information in FIG. In FIG. 17, for example, at the display position in the fourth area 128, the three registered windows other than the root window match in the coordinate calculation, but considering the priority, the document 131 and the pattern 132 of priority 2 Only the windows corresponding to the overlap with and are selected and satisfy the above constraints.

The method of determining the blend ratio of each pixel is as described above, and the other operations of this embodiment are the same as those of the second embodiment.

In the image blending circuit of the second embodiment, the pixel blending device 104 sets the pixel blending device 104 to the first state after the power is turned on and before the transition to the display state where the semitransparent composition is not performed as shown in FIG. The binary number 11 is written to all the pixels in the attribute buffer 134 so that the output of the image memory 102 of 1 is selected. Therefore, 1152 × 900 × 2 = 2,037,600 bits of data is written.

On the other hand, in the present embodiment, in order to shift to the display state of FIG. 7, instead of writing the data of the attribute buffer 134, the information of the table of FIG. 16 is stored in the window information storage device 135. Just write in. The number of bits of this data is 11 bits in the horizontal direction, 10 bits in the vertical direction, and the maximum priority depends on the number of windows that can be registered, but it is 0 to 511. If the control signal is used as it is and the selection of the blend ratio is 2 bits, 32 bits are required for one window, and since there are three pieces of window information in FIG. 16, 96 bits are sufficient.

Further, even when the window of the symbol 32 is moved from FIG. 7 to the state of FIG. 9, the area 128 of the attribute buffer 18 or 134, like the image blending circuits of the first and second embodiments. Counter contents 1
230 × 15 to change the output of 05 to the selected value
Instead of changing the information of 0 = 34,500 pixels, the information corresponding to the window of the pattern 132 in the window information storage device 135 may be updated, and the information of the window corresponding to the overlapping portion corresponding to the area 128 may be added. 64-bit data writing is sufficient.

In the third embodiment, when the number of windows and the number of overlapping portions are increased, the amount of information that needs to be stored in the window information storage device 135 increases, and the amount of information that needs to be updated by operating the window also increases. Therefore, the storage capacity of the window information storage device 135 limits the settable limit of the number of windows and the overlapping portion. Even in consideration of this, the amount of data to be written is small when the area (number of pixels) in the display state is large due to the window operation.

As described above, according to the third embodiment, the attribute buffer 134 in the second embodiment is used.
Is replaced by the window information storage device 135 and the control signal determination device 136, so that when the blend ratio is set corresponding to the window or the display state is updated in response to the window operation, the amount of data to be written becomes larger. It can be small.

The attribute buffer 108 in the first embodiment may be replaced with the same window information storage device and control signal determination device as in the present embodiment.

In all of the above embodiments, only one counter 105 also serving as a register is provided, but two or more counters may be provided. In particular, in the second and third embodiments, instead of the fixed values 0 and 1 selected by the data selector 133, the number of registers or counters may be increased to select the output. In that case, it is possible to increase the number of regions in which the blend ratio can be individually rewritten at high speed by the number of registers. However, if the number of registers is increased, the number of options selected by the data selector 107 or 133 is increased, the number of bits of the control signal is increased, the capacity of the attribute buffer 108 or 134 or the window information storage device 135 is increased, and the speed is increased. It must be noted that the effect of will become smaller. In the case where low speed is acceptable, it is necessary to consider that the blend ratio buffer 106 can realize an arbitrary blend ratio distribution.

(First Embodiment of Weighted Average Circuit) Integer i
An integer multiple of (binary number 2) Hereinafter, a first embodiment of the weighted average circuit of the present invention will be described with reference to FIG.

FIG. 4 is a block diagram of the first embodiment of the present invention. In the figure, 201 is an adder circuit (adding means), 2
02 to 206 are selectors (selection means). Each selector 2
A logic circuit diagram of 02 to 206 is shown in FIG. In the figure, 207 is an inverter, 208 to 215 are 2-input logical product circuits, and 216 to 231 are 2-input logical sum circuits.

The adder circuit 201 is constructed by continuously connecting the partial adder circuit 232 shown in FIG. 19 and the partial adder circuit 257 shown in FIG. The output Σ1 of the partial adder circuit 232 of FIG. 19 is connected to the input A of the partial adder circuit 257 of FIG. 20, and the output Σ2 of the partial adder circuit 232 is connected to the input B of the adder circuit 257. 19 and 20, 233 to 256
And 258 to 265 are 1-bit full adders. Figure 2
1 shows a truth table of the operation of the logic circuit.

The adder circuit 201 inputs 8-bit binary numbers weighted by 1/2, 1/4, 1/8, 1/16, and 1/16 by shifts, adds them, and sums them. It is designed to output. The sum of the weights is 1, and 1/2, 1/4, 1/8, 1 /
16 is a geometric progression with a common ratio of 1/2. The weight of the output is the sum of the weights, that is, 1 and has a relationship of being shifted by 4 digits from the minimum weight of 1/16, so that the output has 12 bits.
The selectors 202 to 206 are adapted to select which of the input signals A and B is given to the input of each weight.
The selection control signals of each selector are S2 to S6.

Next, the specific structure and operation of the weighted average circuit will be described. The selection control signal input S of the selector is 0 or 1. When S = 1, the output is Y = A, and when S = 0, the output is Y = B.
Can be expressed as Y = [S2xA + (1-S2) xB]. In this way, since the outputs of the respective selectors are weighted and summed, the value of the output of the adder circuit 201 is represented by A, B, and S2 to S6 as shown in the following formula (2). (3)
And is further transformed into the following equation (4).

[S1x A + (1-S2) xB] / 2 + [S3xA + (1-S3) xB] / 4 + [S4x A + (1-S4) xB] / 8 + [S5x A + (1 -S5) xB] / 16 + [S6x A + (1-S6) xB] / 16… (2) [S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16] x A + [ (1-S2) / 2 + (1-S3) / 4 + (1-S4) / 8 + (1-S5) / 16 + (1-S6) / 16] xB… (3) [S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16] x A + (1- [S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16]) xB… (4) , Blend ratio α = S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16
+ S6 / 16, the output is αx A + (1-α) xB. The first to fourth terms of α = S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16 + S6 / 16 are the 2 digits of the selection control signal (S2, S3, S4, S5) with 4 digits after the decimal point. It indicates that it represents a decimal number. Therefore, according to the first to fourth terms, 0.
It is possible to represent 16 different values in increments of 0625. When the selection control signal S6 = 0, the fifth term becomes 0, so the blend ratio α has the value as shown above, and the selection control signal S6 =
In the case of 1, the value of the fifth term is 0.0625, so the blending ratio α takes 16 different values in 0.0625 increments in the range of 0.0625 to 1. Therefore, the selection control signal S6 = 0
The number of cases where the blending ratio α can take in the case of S6 and the case of S6 = 1 overlaps 15 ways. After all, the selection control signal (S2, S
3, S4, S5, S6) 17 in 0.0625 increments in the range of 0 to 1
The value of the blend ratio α can be specified.

As described above, the value of αx A + (1-α) xB is accurately calculated by the weighted averaging circuit of this embodiment for 17 cases in which the value of the blend ratio α is in the range of 0 to 1. It was shown that it was possible.

Here, an example of the operation of inputting a specific numerical value will be shown. The values of input signals A and B are decimal numbers 217 and 38, respectively.
Then, if expressed in binary numbers, 11011001,00 each
100110. Here, select control signals (S2, S3, S4,
S5, S6) = (1,0,1,1,0), the following equation (5)
Becomes

Α = 1/2 + 1/8 + 1/16 = 11/16 = 0.6875 (5) With these inputs, the selectors 202, 204, 205
Selects the value of the input signal A, and the selectors 203 and 206 select the value of the input signal B. Therefore, the addition circuit 201 performs the following calculation.

[0117] The 12-bit binary number 10100001.0001 in the output is 161.0625 when converted to a decimal number, which is calculated as 217 x 0.687.
It turns out that 5 + 38 x 0.3125 is done correctly.

Another example will be shown. When the values of the input signals A and B are decimal numbers 25 and 131, respectively, the binary numbers are 00011001 and 10000011, respectively. When the selection control signals (S2, S3, S4, S5, S6) = (1,1,0,1,0), the following equation (6) is obtained.

Α = 1/2 + 1/4 + 1/16 = 13/16 = 0.8125 (6) With these inputs, the selectors 202, 203, 205
Selects the value of the input signal A, and the selectors 204 and 206 select the value of the input signal B. Therefore, the addition circuit 201 performs the following calculation.

[0120] The 12-bit binary number 00101100.1110 in the output is 44.875 when converted to decimal, which is 25 x 0.8125 +
It turns out that 131 x 0.1875 is done correctly.

Next, the weighted average circuit of this embodiment and the multiplier will be compared.

The weighted average circuit of this embodiment is constructed by connecting five 8-bit selectors 202 to 206 to each input of an adder circuit 201 having five 8-bit inputs. The 8-bit selector is a 2- and 2-input AN as shown in FIG.
It is composed of eight D-OR circuits and one inverter. Therefore, the weighted average circuit of this embodiment has 40 AND-OR circuits. A multiplier for multiplying a value of 8 bits and a value of 5 bits is a set of 8 bits of input, that is, 40 bits of input divided into several weights, each set of bits of multiplier and multiplicand (8 × It is configured by connecting 40 two-input AND gates for ANDing (5 = 40 ways). Thus, in the weighted average circuit of this embodiment and the 8-bit × 5-bit multiplier, the scale of the adder circuit is exactly the same. The circuit at the preceding stage is slightly larger in the present embodiment by the difference between the 40 AND gates and 40 AND-OR circuits, but since it is a scale that can be ignored in terms of the scale of the adder circuit, the entire circuits are It can be said that the calculation time and the circuit scale are almost the same.

As described above, in the present embodiment, the multi-input adder circuit is configured so that the total sum of the weights becomes 1, which is twice the maximum weight value 1/2, and the digital input signals A and B are added.
By having a selector that selects the signal to be input to the adder circuit for each weight, the circuit scale and operating speed are as small as the number of gates and the calculation speed is as high as one multiplier. A weighted average circuit can be provided that calculates A + (1-α) xB.

In this embodiment, four input signals represented by binary numbers are input to the adder 201, but the input signals are 2
The i-adic number representation is not required even if the i-ary number is used. This also applies to the following description.

(Second Embodiment of Weighted Average Circuit) A second embodiment of the weighted average circuit of the present invention will be described below with reference to the drawings.

FIG. 32 is a block diagram of the second embodiment of the weighted average circuit of the present invention. In the figure, reference numeral 266 is a circuit for rounding down to zero. The same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 33 shows a logic circuit diagram of the circuit 266 for performing the round-down. In the figure, 267 to 274 are 2-input exclusive OR circuits, and 275 to 281 are 2-input AND circuits.

The circuit 266 for performing the rounding-down operation truncates the lower 3 bits from the 12-bit input, ignores the 9th bit from the upper bit when it is 0, and outputs the upper 8 bits as they are, and outputs from the upper bit. If the 9th bit is 1, the higher 8
It carries out calculation by adding 1 to the bit position and outputs the upper 8 bits.

In this embodiment, A ≦ 11111111
(Binary number), B ≦ 11111111 (binary number), 0 ≦ α
Since ≦ 1, the value input to the circuit 266 for performing rounding down, that is, the output of the adder circuit 201 is α x A + (1-α) x
B ≦ 11111111.0000 (binary number). Therefore, in the circuit 266 for performing the round-down operation, carry carry does not cause overflow. Therefore, the logical product of the output of the logical product circuit 281 and the input signal IN [11] is taken and the digit to the upper bit is obtained. There is no need to raise it.

The specific configuration and operation of the weighted average circuit of this embodiment will be described. Up to the output of the adder circuit 201 is completely first
The description is omitted because it is the same as the embodiment described above. Adder circuit 20
The output of 1 is 12 bits, but the circuit 266 for performing the rounding down performs the rounding down at the 9th bit, rounding to 8 bits, and the output.

An example of the operation when a specific numerical value is input will be shown. For the sake of simplicity, the numerical values used as examples are the values shown in the first embodiment. First, the values of the input signals A and B are decimal numbers 217 and 38, respectively, and (S2, S3, S4, S5, S6) = (1,0,1,
1, 0), that is, α = 0.6875, the output of the adder circuit 201 is 10100001.0001 as a 12-bit binary number, which is 161.0625 when converted to a decimal number, as shown in the first embodiment. Circuit 2 for rounding down this value
When it is input to 66, since the first decimal place of the 9th bit from the higher order is 0, the part after the decimal point is truncated. Therefore, the output of the circuit 266 for performing the rounding down is 8 bits 2
It is 10100001 in decimal, and when converted to decimal 161
Is. In this case, the error is -0.625.

Another example will be shown. The input signals A and B are decimal numbers 25 and 131 respectively, and the selection control signals (S2, S3, S4,
When S5, S6) = (1,1,0,1,0), that is, α = 0.8125, the output of the adder circuit 201 is a 12-bit binary number 00101100.1110, as shown in the first embodiment. The decimal number is 44.875. When this value is input to the circuit 266 for rounding down to zero, since the first decimal place of the 9th bit from the higher order is 1, the decimal places are rounded up. Therefore, the circuit 266 for performing the rounding down.
Output is 8-bit binary number 00101101, 10
Converted to a base number, it is 45. In this case, the error is 0.125.

The error is compared with the case of the first embodiment. The position of the decimal point is between the 8th and 9th bits. In other words, the 8th bit is the ones digit. The error ε when the output of the first embodiment is rounded down to the 8th bit by cutting off the 9th bit and below is -0.9375≤ε≤0, and the average assuming a uniform distribution is -0.46875. In the case of this embodiment, the error ε is −0.4375 ≦ ε ≦ 0.5, and the average assuming a uniform distribution is 0.03125.

In this way, the weighted average circuit of this embodiment is
By providing a circuit for performing the rounding down, the average value of the error can be reduced.

The partial adder circuit 257 of the adder circuit 201.
The circuit may be modified to include the circuit 266 for performing the rounding down. In that case, there is an effect that the number of stages of the circuit is saved and the circuit amount and the calculation time are reduced.

(Third Embodiment of Weighted Average Circuit) A third embodiment of the weighted average circuit of the present invention will be described below with reference to the drawings.

FIG. 24 is a block diagram of the third embodiment of the weighted average circuit of the present invention. In the figure, 282 is a decoder as a control means for outputting a selection control signal for controlling each of the selectors 202 to 206. The same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

The circuit of the decoder 282 is shown in FIG. In the figure, reference numerals 283 to 286 are 2-input logical sum circuits.

As shown in the first embodiment, the adder circuit 201 shifts by 1/2, 1/4, 1 respectively.
An 8-bit binary number weighted to / 8, 1/16, and 1/16 is input and added, and the sum is output.

The specific configuration and operation of the weighted average circuit of this embodiment will be described. The decoder 282 converts the input r into selection control signals S2 to S6 of the selector and outputs the selection control signals S2 to S6. The operations of the selectors 202 to 206 and the adder circuit 201 are as described in the first embodiment. As shown there, the weights corresponding to the selectors 202 to 205 are 1/2, 1/4, 1
Since it is a geometric progression of / 8, 1/16 and a common ratio of 1/2, if the selection control signal S6 = 0, (S2, S3, S4, S5) is a binary number with 4 digits after the decimal point. Seen blend ratio α = S2 / 2
It works with + S3 / 4 + S4 / 8 + S5 / 16. The input r is a 5-bit fixed-point binary number, the most significant bit of which is 1,
It represents the range of 0.0000 to 1.1111. Therefore, when the highest bit is 0, the decoder 282 outputs the lower 4 bits of the input r as the selection control signals (S2, S3, S4, S5) as they are,
Select control signal S6 = 0. Most significant bit of input r is 1
In this case, the value is 1 or more, but for values exceeding 1, the blend ratio α = 1 is set. In other words, the blend ratio is saturated at 1. Therefore, if the most significant bit of input r is 1, S2 =
Set S3 = S4 = S5 = S6 = 1.

Specifically, the selection control signals S2 to S6 of the selector will be shown for several values of the input r.
For example, if the input r = 1.0110, the most significant bit is 1.
Therefore, (S2, S3, S4, S5, S6) = (1,1,1,1,
1). When r = 0.1001, the most significant bit is 0
Therefore, (S2, S3, S4, S5, S6) = (1,0,0,1,
0).

As described above, in this embodiment, the weights of the inputs of the adder circuit are 1/2, 1/4, 1/8, 1/16, 1/1.
6 except for the last 1/16, form a geometric progression with a common ratio of 1/2, and the last weight is equal to the previous weight,
Therefore, the fixed point number r representing the blend ratio in a certain range can be used as it is for the selection control signal of the selector, and further, a decoder for converting the input r into the selection control signal of the selector and outputting it is added. As a result, the selector can be controlled so that the fixed-point number r cannot be used as it is for the selection control signal of the selector, and the correct operation is performed with respect to the value of the input r. Therefore, the present embodiment operates correctly in all cases of the fixed point number r representing the blend ratio.

(Fourth Embodiment of Weighted Average Circuit) A fourth embodiment of the weighted average circuit of the present invention will be described below with reference to the drawings.

FIG. 26 is a block diagram of the fourth embodiment of the weighted average circuit of the present invention. In the figure, 287 to 29
Reference numeral 1 is a first selector (first selection means), 292 is a second selector (second selection means), and 601 is a decoder (control means). The same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. 27 shows a logic circuit diagram of the first selector, FIG. 28 shows a logic circuit diagram of the second selector, and FIG. 29 shows a circuit diagram of the decoder 601.

In FIG. 27, 293 to 318 are 2-input logical product circuits, 319 to 326 are 3-input logical sum circuits, and 32.
Reference numerals 7, 328 are inverters. In FIG. 28, 329-
Reference numeral 354 is a 2-input logical product circuit, 355 to 362 are 3-input logical sum circuits, and 363 and 364 are inverters.

The weighting of the adder circuit 201 is the same as that in the first embodiment. The output is 12 bits, but in this embodiment, 8 bits are required as an output, and the lower 4 bits are truncated and input to the selector 292. Selector 28
7 to 291 input the corresponding constant values C2 to C6 and the input signals A and B, and input the respective weights of the adder circuit 201 from the three values of the input signals A and B and the constant value. Operates to select and give one. Selector 292
Selects and outputs one of the three values of the output (upper 8 bits) of the adder circuit 201 and the input signals A and B.

Further, in the decoder 601 of FIG. 29,
Reference numeral 602 is a 4-input logical sum circuit, and 603 is a 2-input logical sum circuit.

Next, the specific structure and operation of this weighted average circuit will be described.

When the selection control signal SC = 0, the selector 287
To 291 select either of the input signals A and B according to the selection control signals S2 to S6, and the selector 292 selects the addition circuit 2
Select 01 output. Therefore, at this time, the operation of this circuit is similar to the conventional example, and the blend ratio α = S2 / 2 + S3 / 4 +
Calculation of composition by S4 / 8 + S5 / 16 + S6 / 16 α x A + (1-
Perform α) xB and output.

On the other hand, when the selection control signal SC = 1, the selectors 287 to 291 input the constant values C2 to C6 input thereto to the adder circuit 201. At this time, the selector 292 selects either the input signal A or B according to the selection control signal SAB and outputs it. When SAB = 1, the input signal A is SAB
When = 0, B is output respectively.

Next, the power consumptions of the weighted average circuit of this embodiment and the weighted average circuit of the first embodiment will be compared. As an assumption for calculating the power, both circuits use elements with very low DC power consumption, such as CMOS, and DC power consumption is negligible. It is assumed that it is consumed when the value is inverted at the output terminal of (including). However, there is no transitional inversion, and it is assumed that any output terminal is inverted at most once between the time when the input changes and the time when the next input changes, and becomes the correct value. The value of its power consumption is
Ignore the part that depends on the output load capacitance for simplicity.
Any terminal consumes 25 (μW) per 1 (MHz).

The operating frequency is 20 (MHz), both weighted average circuits have the blend ratio α = 1, and the control is fixed so as to output the input signal A. The input signal A is (0 , 0,0,0,0,0,0,0) and (1,1,1,1,1,1,1,1,1) are assumed to alternate.

In the weighted average circuit of this embodiment, when the blend ratio α = 1, the selection control signal SC = 1 is set, and the output terminals of the logic gates inside the selectors 287 to 291 and the adder circuit 201 are all constant. Since they are not inverted at, their power consumption becomes 0. In the selector 292, only the outputs of the eight AND circuits and the eight OR circuits corresponding to the path of the input signal A are inverted for each pixel, so that the power consumption is 25 (μ
W / MHz) × 20 (MHz) × 16 (pieces) = 8000 (μW) = 8
(mW).

In the weighted average circuit of the first embodiment, when the blend ratio α = 1, all the selection control signals S2 to S6 are set to 1, and the selectors 355 to 359 all pass the input signal A. . Therefore, with one selector, the selector 29
8 (mW) is consumed because the same operation as 2 is performed, and the selector 3
In 55 to 359, a total of 40 (mW) is consumed. Further, inside the adder circuit 201, the outputs of all full adders except the 4 bits of Σ [3: 0] are inverted for each pixel. Full adder 28
1 to 304 and 306 to 313 are 32 in total, and the number of output terminals is 64, and the number is inverted to 60, so the power consumption is 25 (μW / MHz) × 20 (MHz) × 60 (
) = 30000 (μW) = 30 (mW). Therefore, the total power consumption of the weighted average circuit of the first embodiment is 70 (mW).

When the blend ratio α is a value between 0 and 1, the adder circuit 201 also operates in the weighted average circuit of this embodiment. Therefore, in this case, the power consumption of the weight average circuit of this embodiment is larger than that of the conventional circuit because the selector 292 consumes power (8 (mW)). When the input signal A is given under the above condition and the input signal B is given so that B = A, the operation of the adder circuit 201 is such that the blend ratio α = 1.
The power consumption of the weighted average circuit of this embodiment is 70 + 8 = 78 (mW).

As described above, the weighted average circuit of this embodiment is
Compared to the first embodiment, when the blend ratio α = 1 or α = 0, similarly, the power consumption becomes very small. The control state of the blend ratio α = 1 is 1
If only pixels are maintained and switching is performed immediately, there is no effect of reducing power consumption, but such usage is rare, and even if the state of the blend ratio α = 1 is semi-fixed or switched, several hundreds. Since it is considered that the usage condition is such that it becomes different for each pixel, the effect of reducing the power consumption appears.

As described above, according to this embodiment,
In place of the selector of the weighted average circuit of the first embodiment, first selectors 287 to 291 capable of selecting and inputting from the input signals A and B and a constant value are adopted, and the adder circuit 201 is also adopted. By providing the second selector 292 which selects and outputs one of the digital input signals A and B and the digital input signals A and B, the addition is performed when the digital input signals A and B can be selected and output. Without operating the circuit 201,
A weighted average circuit that reduces power consumption can be provided.

(Fifth Embodiment of Weighted Average Circuit) Hereinafter, a fifth embodiment of the weighted average circuit of the present invention will be described with reference to the drawings.

FIG. 30 is a block diagram of a fifth embodiment of the weighted average circuit of the present invention. In the figure, 232 is the first
The partial adder circuit 365 is a second partial adder circuit.
The same components as those in FIG. 26 are designated by the same reference numerals, and the description thereof will be omitted. Also, the first partial adder circuit 2
The internal structure of 32 is shown in FIG.

FIG. 31 shows a block diagram of the second partial adder circuit 365. In the figure, 367 is a 4-bit second
Carry propagate adder, 368 is a first carry propagate adder for adding a 4-bit value and a 7-bit value, and 366 is a 4
The third carry carry adder for bits 369 is a sixth selector (sixth selecting means).

FIG. 32 shows a circuit diagram of the second and third carry propagation adders 366 and 367. In the figure, 370 to 373 are 1-bit full adders.

FIG. 33 shows the first carry propagation adder 36.
8 is a circuit configuration diagram of FIG. In the figure, 374 to 377
Is a 1-bit full adder.

The first carry propagation adder 368 performs addition on the input and output from the least significant bit to a certain intermediate bit, and outputs the carry generated from the intermediate bit. The second carry-propagate adder 367 is provided for the bits higher than the intermediate bit of the second partial adder circuit 232 when the carry of the first carry-propagate adder 368 is assumed to be 0. Add on input and output. Also, the third
Carry carry adder 366 of the second carry propagate adder 366, if the carry of the first carry propagate adder 368 is 1.
Addition is performed on the input / output of bits higher than the intermediate bit of the partial addition circuit 232. Sixth selection means 369
Selects the output of the second carry propagation adder 367 if the carry value of the first carry propagation adder 368 is 0,
If the carry value is 1, the output of the third carry propagation adder 366 is selected and output.

The sixth selector 369 selects two systems of 5-bit binary numbers, and has the same configuration as the selector shown in FIG. 18, except that the circuit for 3 bits is removed. . For example, from the circuit of FIG.
The third selector 369 can be configured by a circuit in which the 26-231 and 2-input logical sum circuits 213-215 are removed.

Next, the specific construction and operation of the weighted average circuit of this embodiment will be described.

This embodiment is the adder circuit 2 of the fourth embodiment.
The partial adder circuit 257 of No. 01 is replaced with the partial adder circuit 365, and the calculation function of the adder circuit is exactly the same. Therefore, the selection control signal is the same as that of the fourth embodiment.
When SC = 0, the composite calculation αxA + (1-α) xB is performed, and when the selection control signal SC = 1, either the input signal A or B is selected and output by the selection control signal SAB. = 1
When SAB = 0, the input signal A is output, and when SAB = 0, B is output.

Next, the weighted average circuit of this embodiment and the weighted average circuit of the first embodiment will be compared.

Regarding the power consumption, the weighted average circuit of this embodiment is similar to the first embodiment in that when the blend ratio α = 1 and α = 0, the first and second parts are used. Since both inputs of the adding circuits 232 and 365 are fixed, the power consumed by the selector 292 can be as small as 8 (mW).

On the other hand, when the blending calculation is performed with the blending ratio α between 0 and 1, both the first and second partial adder circuits 232 and 365 consume power.
In the present embodiment, the power consumption is slightly increased because the circuit amount is slightly increased as compared with the first embodiment. Since the weighted average circuit of this embodiment is larger than that of the first embodiment by four full adders, one inverter, ten AND circuits, and five OR circuits, these output terminals are Assuming that they are all inverted at 20 (MHz), the number of output terminals is 24, so 25 (μW / MH
z) × 20 (MHz) × 24 (pieces) = 12000 (μW) = 12
The power consumption increases by (mW), and the power consumption of the entire weighted average circuit of this embodiment becomes 90 (mW).

Subsequently, the respective operating speeds are compared.

In the fourth embodiment, the adder circuit 20
The longest path inside 1 is, for example, from the input of full adder 240 to full adders 248, 256, 265, 264, 263,
Full adder 2 via 262, 261, 260, 259
While 11 full adders have passed through the output of 58, in the present embodiment, in the first partial adder circuit 232 and the second partial adder circuit 365, the longest path is, for example, the full adder. From the input of 240, each full adder 248, 256, 37
6th selector 3 via 7, 376, 375, 374
Since one inverter, one logical product circuit, and one logical sum circuit are passed inside 29, the longest path in the weighted average circuit of this embodiment is 7 full adders, 1 inverter, and logical 1 product circuit,
It consists of one OR circuit.

Since the propagation delay of the full adder is about 3 (ns) and the propagation delay of the other logic circuits is about 1 (ns), the output of each adder circuit is fixed in the first embodiment. It takes about 33 (ns), but it is about 24 (ns) in this embodiment, and the calculation time can be reduced by about 9 (ns).

In the first embodiment, the maximum delay from the input signals A and B to the output is about 33 (ns) of the adder circuit 201 when the synthesis calculation via the adder circuit is performed in the weighted average circuit as a whole. Approximately 37 (ns) including the delay time of selector before and after
Therefore, in this embodiment, similarly, it becomes about 28 (ns).

Therefore, it is understood that the weighted average circuit of this embodiment can operate up to a higher frequency than that of the first embodiment.

In this embodiment, the adder circuit 2 of the first embodiment is used.
The second partial adder circuit 365 shown in FIG. 31 is used in place of the partial adder circuit 257 shown in FIG. A weighted average circuit having

(Sixth Embodiment of Weighted Average Circuit) Hereinafter, a sixth embodiment of the weighted average circuit of the present invention will be described with reference to the drawings.

FIG. 34 is a block diagram of a sixth embodiment of the weighted average circuit of the present invention. In the figure, 378 is the seventh
Selector (seventh selecting means), 380 is an eighth selector (eighth selecting means), and 379 is a ninth selector (ninth selecting means). The same components as those in FIGS. 30 and 31 are designated by the same reference numerals, and the description thereof will be omitted.

The internal structure of the first carry propagation adder 368 is as shown in FIG.

Second and third carry propagation adders 367, 3
The internal configuration of 66 is as shown in FIG.

The internal configuration of the seventh selector 378 is shown in FIG.
This is the same as the logic circuit diagram of the selector shown in FIG.

The eighth selector 380 is the seventh selector 37.
Since the function of selection is the same as that of 8 and the number of bits is reduced from 8 to 3, the internal configuration is the same as that of the logic circuit of the selector shown in FIG.
For example, the logical product circuits 222 to 231 and the logical sum circuits 211 to 215 are removed from FIG.

The ninth selector 379 is the first selector 28.
7 to 291 have the same selection function and the number of bits is 8 to 5
Since it has been reduced to, the internal configuration is the same as that of the logic circuit of the selector shown in FIG. For example, in FIG. 27, AND circuits 293 to 3
01, and OR circuits 319 to 321 are removed.

Next, the specific structure and operation of the weighted average circuit of this embodiment will be described.

When the selection control signal SC = 0, the selector 287
˜291 selects either of the input signals A and B according to the selection control signals S2 to S6, the selector 380 selects the output of the carry propagation adder 368, and the selector 379 outputs the output of the carry propagation adder 368. Carry carry adder 3 by carry of
Either the output of 67 or carry propagate adder 366 is selected.

Therefore, carry propagation adders 366 to 368.
And the selectors 379 and 380 operate as a carry select adder, and the carry select adder sums the two outputs of the first partial adder circuit 232 and outputs the result. Therefore, at this time, the operation of this weighted average circuit is similar to the conventional example, and the blend ratio α = S2 / 2 + S3 / 4 + S4 / 8 + S5 / 16
+ S6 / 16 is used to calculate the composite α x A + (1-α) x B and output.

On the other hand, when the selection control signal SC = 1,
The selectors 287 to 291 have constant values C2 to C6 input to them.
Is input to the first partial adder circuit 232. Since the first partial adder circuit 232 outputs a constant value regardless of the input signals A and B, the carry propagation adders 366-3 are provided.
The input and output values of 68 also take constant values.
The selector 380 selects and outputs the lower 3 bits of the selector 378, and the selector 379 selects and outputs the upper 5 bits of the selector 378. The selector 378 selects and outputs either the input signal A or B according to the selection control signal SAB regardless of the selection control signal SC.

Therefore, when the selection control signal SC = 1,
As the output of the weight averaging circuit of this embodiment, the input signal A is output if SAB = 1, and B is output if SAB = 0.

As described above, in terms of function, the weighted average circuit of this embodiment is exactly the same as that of the fourth and fifth embodiments.

Next, the operating speeds of the weighted average circuit of the present embodiment and the weighted average circuit of the fifth embodiment will be compared.

In the weighted average circuit of the fifth embodiment, the longest path of the portion where the adder circuit 232 and the adder circuit 365 are combined is, for example, from the input of the full adder 240 to each full adder 248, 256, 377, 376. , 375, 374, inside the third selector 369, one inverter, one logical product circuit, and one logical sum circuit are passed, so there are seven full adders and one inverter. , AND circuit 1 and OR circuit 1
It is an individual.

Therefore, the longest path of the entire weighted averaging circuit of the fifth embodiment is such that the adder circuit 232 and the selector parts before and after the adder circuit 365 are combined, seven full adders, one inverter, and a logical unit. It goes through three product circuits and three OR circuits, and its delay time is about 28 (ns).

On the other hand, the weighted average circuit of this embodiment is
Two selectors 369, 2 of the weighted average circuit of the fifth embodiment
92 is removed and selectors 378 to 380 are added. In the longest path, the part that has passed through the two selectors 369 and 292 is replaced by the part that passes through the selector 328. Therefore, the longest path is shortened by one stage of the selector, and goes through 7 full adders, 1 inverter, 2 AND circuits, and 2 OR circuits.

Therefore, in this embodiment, the delay time is about 2 (n
s) is reduced to 26 (ns).

As described above, the weight averaging circuit of this embodiment can operate in a shorter time than the weight averaging circuit of the fifth embodiment, and provides a weight averaging circuit with a reduced calculation time. be able to.

(Seventh Embodiment of Weighted Average Circuit) Hereinafter, a weighted average circuit of a seventh embodiment of the present invention will be described with reference to the drawings.

FIG. 35 is a block diagram of a weighted average circuit according to the seventh embodiment of the present invention. In the figure, 381 is the first
Adder circuit (first adding means), and 382 to 385 are third
Selector (third selecting means), 386 is a second adding circuit (second adding means), 387, 388 is a fourth selector (fourth selecting means), and 389 to 393 are fifth. The selector (fifth selection means) 394 is a decoder (control means). However, the fifth selectors 389 to 393 are divided into two types, the selectors 389 to 392 are the first type, and the remaining selectors 393 are the second type.

FIG. 36 shows an internal block diagram of the first adder circuit, and FIG. 37 shows an internal block diagram of the second adder circuit.
36 and 37, 396 to 402 are carry save adders and 195 are carry propagation adders.

Here, signals having bit widths are connected to each other in order of increasing number of subscripts. For example, in FIG. 37, the carry save adder 4
02 output OA [8: 1] is input I1 of carry save adder 401
Connected to A [7: 0], typically OA [8]-I1A [7], OA
Connected as [7]-I1A [6], ....., OA [1]-I1A [0]. Of course, the signals must have the same bit width.

FIG. 38 shows an internal configuration diagram of the carry save adder.
FIG. 39 shows an internal configuration diagram of the carry propagation adder.

38 and 39, 403 to 409
And 412 to 418 are 1-bit full adders, 410, 4
Reference numeral 19 is a 2-input AND circuit, and 411 and 420 are 2-input exclusive OR circuits. FIG. 21 shows a truth table of the operation of the logic circuit of the 1-bit full adder.

FIG. 40 shows a logic circuit diagram of the third selector. At the same time, this figure also serves as a logic circuit diagram of the first type of the fifth selector. In FIG. 40, 421 to 43
Reference numeral 6 is a 2-input logical product circuit, and 437 to 444 are 2-input logical sum circuits.

FIG. 41 shows a logic circuit diagram of the fourth selector. In the figure, 445 to 468 are 2-input logical product circuits and 469 to 476 are 3-input logical sum circuits.

FIG. 42 shows a logic circuit diagram of the second type of the fifth selector. In the figure, 477 to 484 are 2-input AND circuits.

FIG. 43 shows a logic circuit diagram of the decoder. In the figure, 485 to 489 are 2-input OR circuits, 49
0 is a 3-input OR circuit, 491 to 500 are inverters, 50
Reference numerals 1 to 513 are 2-input logical product circuits.

Next, the specific structure and operation of the weighted average circuit will be described.

The carry save adder shown in FIG. 38 inputs three 8-bit binary numbers, performs weighted addition of 2: 1: 1, and outputs the addition result to two bits of 8 bits and 9 bits. Two
Output in decimal.

The carry propagation adder shown in FIG. 39 inputs two 8-bit binary numbers, adds them with equal weights, and outputs the addition result as one 9-bit binary number.

The first adder circuit 381 cascades one carry save adder and one carry propagation adder to shift 1/2, 1/4, 1 respectively.
Six 8-bit binary numbers weighted to / 8, 1/16, 1/32, and 1/32 are input, added, and the sum is output. The sum of the weights is 1, and each weight is 1/2, 1/4, 1/8, 1/16,
1/32 and 1/32 are geometric progressions with a common ratio of 1/2.

The weight of the output is the sum of the weights, that is, 1 and has a relationship of being shifted by 5 digits from the minimum weight of 1/32, so that the output has 13 bits.

The second adder circuit 386 connects the three carry save adders 400 to 402 in cascade to obtain
Two binary numbers are input, weighted addition is performed, and the total is output as two binary numbers of 8 bits and 11 bits. If the output weights are 1/32, the input weights are 1/32, 1/64, 1/128, 1/256, 1/2, respectively.
56. 1/32, 1/64, 1/128, 1/2
56 is a geometric progression with a common ratio of 1/2.

The selector shown in FIG. 19 has input signals A, B,
It can be selected from three values of constant value 0. When the selection control signals SA = 1 and SB = 0, the output Y becomes Y = A,
When the selection control signals SA = 0 and SB = 1, the output Y becomes Y = B, and when SA = SB = 0, the output becomes Y = 0.

The selector shown in FIG. 41 has input signals A, B,
One can be selected from the three values of C (a constant value 0 can also be selected, but is not used in this embodiment). When the selection control signal SA = 1 and SB = SC = 0, the output Y becomes Y = A, and when the selection control signal SB = 1 and SA = SC = 0, the output Y becomes Y = B, and the selection control signal SC = 1 and SA = SB = 0, the output Y becomes Y = C.

In the selectors shown in FIGS. 40 and 41, the input patterns of the selection control signals SA, SB and SC are not given except for those described above.

The selector shown in FIG. 40 may be used as the selector 393, but since Y = A is not selected for the output Y, the selector shown in FIG. 42 is used by simplifying the circuit. Good. The selector shown in FIG. 42 has a selection control signal SB =
When it is 1, the output Y is Y = B, and when the selection control signal SB = 0, the output Y is Y = 0.

As described above, not all selectors need the function of switching and selecting all of the input digital input signals. Like the weighted average circuit of the conventional example, the blend ratio α realized by the combination of the selection control of the selectors
, There is a case where there is an overlap, and the selection function corresponding to the redundant part (combination not used) is removed, or the number of cases where the blend ratio α can be selected is reduced to reduce the circuit amount, etc. If so, some selectors can reduce the selectable digital input signal, simplifying the circuit.

The decoder 394 has a code R and a signal AC.
C is input. The code R is a code for designating the blend ratio α, and in this embodiment, a 9-bit binary fixed point number (8 digits after the decimal point) is used. The signal ACC is a 1-bit signal that specifies the accuracy of the blend ratio.

The operating state of the weighted average circuit of this embodiment is classified according to the input to the decoder 394 when any of the following equations (7), (8) and (9) is satisfied.

R [8] = 1 ... (7) R [8] = 0 and {ACC = 0 or R [2] = R [1] = R [0] = 0} ... (8) R [8] = 0 and ACC = 1 and {R [2] = 1 or R [1] = 1 or R [0] = 1} (9) The operation in each case will be described below.

In the case of the equation (7), the output of the decoder 394 is SA2, SA3, SA4, SA5, SA7, SA8 = 1, and SB2, SB3, SB
4, SB5, SB7, SB8, SC7, SC8, SA9, SB9, SA10, SB10, SA11, SB11,
Since SA12, SB12, SB13 = 0, selectors 382-38
5, 387 and 388 select the input signal A, and the other selectors 389 to 393 select the constant value 0. Therefore, since the input signal A is guided to all the inputs of the adder circuit 381, the calculation in the adder circuit 381 is A / 2 + A / 4 + A / 8 + A / 16 + A.
/ 32 + A / 32 = A, and the output is equal to the input signal A.
In this case, since the constant value 0 is given to all the inputs of the second adder circuit 386, the operation of the second adder circuit 386 is stopped.

Further, in the case of the above formula (7), the fixed point number of R [8: 0] is 1 or more, but when α> 1, the blend is not defined, and when α> 1, α is set. Treated as = 1.
That is, if R [8] = 1, regardless of the value of R [7: 0], α =
Calculate as 1.

In the case of equation (8), the output of the decoder 394 is SA2 =! , SB2 = R [7], SA3 =! , SB3 = R [6]
, SA4 =! , SB4 = R [5], SA5 =! , SB5 = R [4]
, SA7 =! , SB7 = R [3], SB8 = 1, SC7, SA
8, SC8, SA9, SB9, SA10, SB10, SA11, SB11, SA12, SB12, SB13 ＝
It is 0 (however, "!" Indicates a unary operator that inverts the logic). In this case, for example, the selector 382 is R
[7] controls to select either input signal A or B. When R [7] = 1, the output Y is Y = A, and R [7] =
When 0, the output Y becomes Y = B. Therefore, Y = {R [7] x
It can be represented as A + (1-R [7]) x B}. Similarly, the selectors 383, 384, 385 and 387 are respectively R [6].
, R [5], R [4], R [3], input signals A, B
, The selector 388 selects the input signal B, and the selectors 389 to 393 select the constant value 0.
Select. Therefore, the selectors 382-385, 387,
A value obtained by weighting and adding the output of 388 by the first adder circuit 381 is given by the following expression (10).

{R [7] xA + (1-R [7]) xB} / 2 + {R [6] xA + (1-R [6]) xB} / 4 + {R [5] xA + (1-R [5]) x B} / 8 + {R [4] xA + (1-R [4]) x B} / 16 + {R [3] xA + (1-R [3 ]) x B} / 32 + B / 32 (10) The above equation can be further transformed into the following two equations (11) and (12).

{R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32} x A + {(1-R [7] ) / 2 + (1-R [6]) / 4 + (1-R [5]) / 8 + (1-R [4]) / 16 + (1-R [3]) / 32 + 1 / 32} x B… (11) {R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32} x A + {1- (R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32)} x B (12) Therefore, the blend ratio α = R [7] / 2 + R [6] / 4 + R [5] /
8 + R [4] / 16 + R [3] / 32, the output is α x A + (1-
It is α) x B.

Therefore, in the case of the above formula (8), R [7:
It is possible to specify 32 blend ratios in 1/32 = 0.3125 increments in the range of 0 to 0.96875 by 5 bits of [3]. In other words, in the case of the formula (8), the blend ratio is a fixed point binary number, the integer part is 0, and the decimal part is 5
Matches the case where it can be expressed in digits or less. R [2: 0] is ignored (though it may be considered to be truncated). Also, at this time, the second
Since the constant value 0 is given to all the inputs of the adder circuit 386, the operation of the second adder circuit 386 is stopped.

In the case of the equation (9), the output of the decoder 394 is SA2 =! , SB2 = R [7], SA3 =! , SB3 = R [6]
, SA4 =! , SB4 = R [5], SA5 =! , SB5 = R [4]
, SA7 = SB7 = SA8 = SB8 = 0, SC7 = SC8 = 1, SA9
=! , SB9 = R [3], SA10 =! , SB10 = R [2], SA11
=! , SB11 = R [1], SA12 =! , SB12 = R [0], SB13 =
It becomes 1. Therefore, the selectors 382 to 385 are controlled by R [7: 4] to select one of the input signals A and B,
The selectors 387 and 388 select C (the output of the second adder circuit 386), and the selectors 389 to 392 are controlled by R [3: 0] to select either the input signal A or B. 393 selects the input signal B. Second adder circuit 386
Is output to the first adder circuit 381 via the selectors 387 and 388, it is possible to consider these four constituent elements as one adder circuit, and
2, 1/4, 1/8, 1/16, 1/32, 1/64,
It can be regarded as an adder circuit which inputs nine 8-bit binary numbers weighted to 1/128, 1/256, and 1/256, adds them, and outputs the total (strictly speaking, 16-bit output The lower 3 bits are truncated to 13 bits. If they are output without truncation, the functions are completely equivalent). Selectors 382-385, Selector 389
Since the outputs of ~ 393 are summed with the above weighting,
The output of the first adder circuit 381 is given by the following expression (13).

{R [7] xA + (1-R [7]) x B} / 2 + {R [6] xA + (1-R [6]) x B} / 4 + {R [5] xA + (1-R [5]) x B} / 8 + {R [4] xA + (1-R [4]) x B} / 16 + {R [3] xA + (1-R [3 ]) x B} / 32 + {R [2] xA + (1-R [2]) x B} / 64 + {R [1] xA + (1-R [1]) x B} / 128 + {R [0] xA + (1-R [0]) xB} / 256 + B / 256 (13) This equation can be further transformed into the following equations (14) and (15). it can.

{R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32 + R [2] / 64 + R [1] / 128 + R [0] / 256} xA + {(1-R [7]) / 2 + (1-R [6]) / 4 + (1-R [5]) / 8 + (1-R [4]) / 16 + (1- R [3]) / 32 + (1-R [2]) / 64 + (1-R [1]) / 128 + (1-R [0]) / 256 + 1/256} x B… (14) {R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32 + R [2 ] / 64 + R [1] / 128 + R [0] / 256} xA + {1- (R [7] / 2 + R [6] / 4 + R [5] / 8 + R [4] / 16 + R [3] / 32 + R [2] / 64 + R [1] / 128 + R [0] / 256)} xB (15) Therefore, the blend ratio α = R [7] / 2 + R [6] / 4 + R [5] /
8 + R [4] / 16 + R [3] / 32 + R [2] / 64 + R [1] / 128 + R
Assuming [0] / 256, the output is αxA + (1-α) xB.

Therefore, in the case of the above formula (9), R [7:
The blend ratio α is 0.00390625 by 8 bits of 0].
You can specify 1/256 = 0.00390625 as the minimum step size in the range of ~ 0.99609375. Although there are always 255 possible steps if 1/256 steps are used, there are 224 possible cases since the case of the above formula (8) is excluded. In other words, the formula
In the case of (9), the blend ratio is equivalent to a case where the integer part is 0 in the fixed-point binary number and the decimal part can be represented by 6 digits or more and 8 digits or less. At this time, the second adder circuit 386 also operates to contribute to the realization of a blending ratio with fine precision.

Next, the power consumption of the weighted average circuit of the present embodiment and that of the weighted average circuit of the first embodiment with the extended blend ratio precision is compared.

In the weighted average circuit of the first embodiment, the minimum step size of the blend ratio α is 1/256 = as in this embodiment.
Must be expanded to 0.000.00625. A block diagram of the weighted average circuit of the expanded first embodiment is shown in FIG. In the figure, 514 is an adder circuit, 5
Reference numerals 15 to 523 are selectors. The selector is similar to that shown in FIG.

FIG. 45 is an internal block diagram of the adder circuit 514.
Shown in. In the figure, 523 to 531 are carry save adders, and 524 is a carry propagation adder.

In the weighted average circuit of FIG. 44, the value of the blend ratio α is 1/256 in the range of 0 to 1 as in the case of this embodiment.
= 257 can be specified in increments of 0.00390625.

As an assumption for calculating the power consumption, it is assumed that both weighted averaging circuits use elements such as CMOS having very low DC power consumption, and the DC power consumption can be neglected. It is consumed when the value is inverted at the output terminal of the full adder (including the full adder).
However, there is no transitional inversion, and it is assumed that any output terminal is inverted at most once between the time when the input changes and the time when the next input changes, and becomes the correct value. The power consumption value is 25 (μ) per 1 (MHz) at any pin, ignoring the part that depends on the output load capacitance for simplicity.
W) shall be consumed.

The operating frequency is 20 (MHz), both weighted average circuits have a blend ratio α = 1, and the signals (S1 to S9, R, ACC) are fixed so that the value of the input signal A is output as it is. And

The input signal A is a pattern that consumes the maximum power under the above assumption (0,0,0,0,0,0,
It is assumed that (0,0) and (1,1,1,1,1,1,1,1,1) are input alternately for each pixel.

In the weighted average circuit of this embodiment, the blending ratio α = 1 is realized in the case of the equation (7). At this time, the selectors 382 to 385, 387 and 388 select the input signal A, and the selectors 389 to 393 select the constant value 0. Therefore, the selectors 382-385, 387, 38
The upper 8 bits of the output of 8 and the output of the first addition circuit 381 are inverted for each pixel, and the outputs of the selectors 389 to 393 and the second addition circuit 386 are all 0 and are constant.

Inside each of the selectors 382 to 385, 387 and 388, the outputs of eight AND circuits and eight OR circuits corresponding to the path of the input signal A are inverted for each pixel.

The inside of the first adder circuit 381 is composed of blocks of four carry save adders and one carry propagate adder, and each block is a full adder 7 of 1 bit.
In this operating state, all outputs other than the exclusive OR circuit are inverted for each pixel.
Five outputs are inverted.

Therefore, the number of outputs to be inverted is 16
(Per selector) x 6 + 15 (per adder block)
× 5 = 171 and power consumption is 25 (μW / MHz) × 2
0 (MHz) x 171 (pieces) = 85500 (μW) = 85.5
(mW).

On the other hand, in the weighted average circuit of the expanded first embodiment, the blend ratio α = 1 is realized by
(S1, S2, S3, S4, S5, S6, S7, S8, S9) ＝ (1,1,1,1,1,1,1,1,1)
In this case, the outputs of the selectors 515 to 523 are inverted pixel by pixel.

The inside of the adder circuit 514 is composed of blocks of seven carry save adders and one carry propagate adder.

Since the number of inverted outputs inside the selector and the adder block is the same as that of the embodiment, the number of inverted outputs is 16 (per selector) × 9 + 15 (per adder block). × 8 = 264, and the power consumption is 2
5 (μW / MHz) × 20 (MHz) × 264 (pieces) = 13200
It becomes 0 (μW) = 132 (mW).

Thus, when the blend ratio α = 1,
The maximum power consumption is 132 in the weighted average circuit of the first embodiment.
(mW), the weighted average circuit of the present embodiment is 85.
It becomes 5 (mW) and 46.5 (mW) less.

Next, consider the power consumption when the blend ratio α is not 1. In this case, what gives the maximum power consumption as an input is a signal equal to the input signals A and B,
This is the case where (0,0,0,0,0,0,0,0) and (1,1,1,1,1,1,1,1,1) are input alternately for each pixel.

In the weighted average circuit of the extended first embodiment, the blend ratio α =
As in the case of 1, the power consumption is 132 (mW). This is because the number of outputs to be inverted is the same, only the signal path in the selector is different.

In the weighted average circuit of this embodiment, there is a difference between the case of equation (8) and the case of equation (9).

In the former case, the selectors 382 to 385, 38
7, 388 selects the input signal A or B, and a selector 389
~ 393 selects the constant value 0, and the second addition circuit 386
Is stopped, the power consumption is 85.5 (mW) as in the case of the blend ratio α = 1.

On the other hand, in the latter case, the selectors 389-39.
The third and second adder circuits 386 also operate, so their power consumption must be added.

The number of inverted outputs of these added parts is 16 (per selector) × 4 (selectors 9 to 12).
+8 (selector 13) +15 (per adder block) x 3
= 117, and the increasing power consumption is 25 (μW / MHz) ×
20 (MHz) × 117 (pieces) = 58500 (μW) = 58.
Since it is 5 (mW), the power consumption of the weighted average circuit of the embodiment in this case is 85.5 + 58.5 = 144 (mW).

Restated about the maximum power consumption, in the expanded circuit of the first embodiment, the blend ratio is 132 (mW) regardless of the blending ratio α, and in the weighted average circuit of the present embodiment, the selectors 389 to 393 are In the case of formula (7) and formula (8) for selecting a constant value (that is, the second adder circuit 386 does not operate), it is 85.5 (mW), and the selectors 389 to 393 select the input signal. Expression (where the second adder circuit 386 operates)
In the case of (9), it is 144 (mW).

As described above, the weighted average circuit of this embodiment is
When the blend ratio is represented by a fixed-point binary number and can be represented by up to 5 digits after the decimal point, power consumption is about 2/3 (maximum value) compared to the weighted average circuit of the extended first embodiment. I'm done. In the case where the number of digits after the decimal point is 6 digits or more and fine weights need to be added, the power consumption (maximum value) is increased by a little less than 10% compared with the conventional circuit. Therefore, it is desirable to set the blend ratio within 5 digits after the decimal point.

Also, when the operation / pause state of the second adder circuit 386 is switched for each pixel or at a speed close thereto, power is consumed by the switching operation of the circuit at the time of switching,
It should be avoided as it will lose the effect of low power consumption in hibernation.

When used for translucent composition of images, the blending ratio is often switched every several hundred pixels even at the maximum speed. In this case, the effect of reducing the power consumption is not lost as described above.

Since it is difficult for human vision to accurately perceive and recognize the value of the blend ratio to a fine precision, when fixing the blend ratio, there is no problem in using a value that can be represented by up to five digits after the decimal point.

Since human vision is sensitive to changes in the blend ratio (and consequently changes in the image), unless the width of the blend ratio setting step is small, when changing the value of the blend ratio. The screen flickers.

For example, in the case where the blend ratio is expressed by 5 digits after the decimal point and changed, the minimum step size is 1/32, but when the contrast of the images of the input signals A and B is clear, When the blend ratio changes, the screen flickers and you perceive the stage of the change. When the blend ratio is expressed using up to 8 digits after the decimal point and is changed with the minimum step size, it changes by 1/256, the change of the screen is smooth, and the flicker of the screen is not perceived.

Therefore, if the second adder circuit 386 operates to realize a blending ratio with fine precision only in a transitional state when the blending ratio is changed, a change in screen due to a change in blending ratio is achieved. Can be perceived smoothly. Only in such a case, if the operation in the case of the above equation (9) is performed, the second adder circuit 3
It is possible to reduce the frequency of appearance of the state in which the 86 operates and increase the time ratio of the state in which the power consumption is low, thereby exerting the effect of low power consumption.

In this embodiment, the input signal ACC is given to the decoder 394 and the stop of the second adder circuit 386 is instructed by this signal ACC. However, R [2] = R [1] = R
Since control can also be performed by setting [0] = 0, ACC = 1 when control is not performed by the input signal ACC.
As a result, the redundant circuit (that is, the logical product circuit 313) can be removed.

In this embodiment, the first adder circuit 381
And a second adder circuit 386, but other 3
Of course, it may be divided into the above plurality.

As described above, according to this embodiment,
If a plurality of small bit addition circuits are provided and the value of the blend ratio can be represented by a fixed-point binary number with up to five digits after the decimal point, the blend ratio can be realized by the sum of relatively large weights. Since only a part of the adder circuit is used and the remaining adder circuit can perform the blend calculation while stopping the operation, it is possible to reduce the power consumption.

In the above description, the decoder is used as the control means for inputting the blend ratio and generating the selection control signal to each selector, but the present invention is not limited to this, and other control means may be used. For example, it may be configured by a ROM.
In this case, there is little variation in the delay time from the input of the blend ratio to the output of the selection control signal, and it is advantageous in that the maximum value of the delay time can be limited to a small value. Further, the control means may be composed of a CPU and its software, and in this case, if the processing capacity of the CPU has a margin, the amount of hardware can be reduced.

[0262]

As described above, according to the window managed image blending circuit of the invention described in claim 1,
When overlapping windows occur, the pixels in the overlapping areas are set to be blended so that the images can be displayed semi-transparently in that area, and the overlapping area due to the movement of the windows There is an advantage that the amount of data to be written is small with respect to movement and deformation, and when the blend ratio of the overlapping portion is changed, only the value of the blend ratio holding means is rewritten.

According to the window managed image blending circuit of the second aspect of the invention, the amount of data to be written can be further reduced when the blending ratio is set corresponding to the window.

Further, according to the window managed image blending circuit of the third aspect of the present invention, it is effective to smoothly change the blending ratio without imposing a load on the central processing unit in the portion for performing the semitransparent composite display. Can be displayed.

In addition, according to the window-blended image blending circuit of the present invention, the amount of data to be written can be further reduced when the blending ratio is set corresponding to the window.

Further, according to the weighted average circuit of the inventions of claim 8, claim 9, claim 13 and claim 15, in the adding means to which a plurality of i-adic signals are input, the sum of weights is Since the weight is set to an integral multiple of the maximum value integer i (i is i of i-ary number), accurate blend calculation is performed by a circuit having a circuit scale and operating speed equivalent to one multiplier. It has an excellent effect.

Further, according to the window-managed image blending circuit of the present invention as defined in claim 4, it is possible to accurately perform the blending calculation when the semi-transparent composition is performed, and at the same level as one multiplier. It is possible to perform the blend calculation with the circuit scale and the operation speed.

In addition, according to the weighted average circuit of the tenth, twenty-first and twenty-second aspects of the present invention, a first one is selected from a plurality of digital input signals and a constant value.
And the second selecting means for selecting and outputting one of the output of the adder circuit and the plurality of digital input signals, the blend ratio has a value indicating the selection of the digital input signal itself. In this case, useless operation of the adder circuit can be eliminated and power consumption can be reduced.

According to the window managed image blending circuit of the present invention, when the pixel at the position where the translucent composition is not performed is transferred, that is, the blending ratio selects the digital input signal itself. When the value is the instructed value, the useless operation of the adding means can be stopped to achieve low power consumption.

Furthermore, claim 11, claim 18, claim 1
According to the weighted average circuit of the invention described in claim 9 and claim 20,
When a plurality of small bit addition circuits are provided and the blend ratio can be realized by the sum of only relatively large weights, only a part of the plurality of addition circuits is used, and the remaining addition circuits stop the operation. You can enable blending calculations,
It is possible to reduce power consumption.

In addition, according to the window managed image blending circuit of the present invention, when the semitransparent composition is performed, the blending ratio of the semitransparent composition is realized by the sum of only relatively large weights. If possible, use only a part of the multiple adder circuits, and the rest of the adder circuits can stop their operations while enabling the blend calculation.
It is possible to reduce power consumption.

Further, according to the weighted average circuit of the invention of claims 12 and 14, since the output of the adder circuit is rounded down to zero when the binary number is handled, the binary number This has the effect of reducing the error in rounding the value.

Further, according to the weighted average circuit of the sixteenth aspect of the present invention, since the adder circuit is constituted by the carry selection adder, the propagation delay time of the signal of the weighted average circuit is reduced,
It has an excellent effect of having a high operation speed necessary for processing a video signal.

In addition, according to the weighted average circuit of the seventeenth aspect of the present invention, the propagation delay time of the longest path in the carry selection adder is further shortened, so that a faster and excellent weighted average circuit is realized. it can.

Further, according to the weighted average circuit of the invention described in claims 23 and 24, each weight in the addition means forms a geometric progression with a common ratio of 1/2, excluding the last weight, When the final weight is equal to the immediately preceding weight, a decoder for converting the input describing the blend ratio into the control signal of each selection means is provided. Therefore, even if the fixed-point binary number representing the blend ratio is input as it is, it is correct. An excellent weighted average circuit that operates can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a window managed image blend circuit of the present invention.

FIG. 2 is a diagram showing a function table of a data selector in FIG.

3 is a block diagram showing an internal configuration of a pixel blending device in FIG.

FIG. 4 is a circuit diagram showing an internal configuration of one weighted average circuit in FIG.

5 is a diagram showing an arrangement example of first to third windows on a display screen of an information processing device using the image blending circuit of FIG.

FIG. 6 is a diagram showing positions of window overlapping portions in FIG.

FIG. 7 is a diagram showing an example in which a document is displayed in a first window and a design is displayed in a second window in FIG.

FIG. 8 is a diagram showing stored contents of respective means in the case of FIG. 7 in which two pieces of information do not overlap on a display screen.

FIG. 9 is a diagram showing an example in which a document is displayed in a first window in FIG. 5 and symbols are displayed in a third window.

FIG. 10 is a diagram showing stored contents of respective means in the case of FIG. 9 in which two pieces of information overlap each other on a display display screen in a partial area.

FIG. 11 is a block diagram showing a configuration of a window managed image blending circuit according to another embodiment of the present invention.

12 is a diagram showing a function table of the data selector in FIG.

FIG. 13 is a diagram showing stored contents of each unit in the case of FIG. 7 in which two pieces of information do not overlap each other on the display screen.

FIG. 14 is a diagram showing stored contents of each unit in the case of FIG. 9 in which two pieces of information overlap each other on a display display screen.

FIG. 15 is a block diagram showing a configuration of a window managed image blending circuit according to still another embodiment of the present invention.

16 is a diagram showing a table showing an example of stored contents of the window information storage device in FIG. 15 when there is no overlapping of windows.

FIG. 17 is a diagram showing a table showing an example of stored contents of the window information storage device in FIG. 15 when windows overlap.

FIG. 18 is a logic circuit diagram of a selector included in the weighted average circuit in the first embodiment.

FIG. 19 is an internal block diagram of a first partial adder circuit included in the weighted average circuit.

FIG. 20 is an internal block diagram of a second partial addition circuit included in the weighted average circuit.

FIG. 21 is a diagram showing a truth table of the operation of the 1-bit full adder.

FIG. 22 is a block diagram of a weighted average circuit in the second embodiment of the present invention.

FIG. 23 is a logic circuit diagram of a circuit that performs rounding to zero.

FIG. 24 is a block diagram of a weighted average circuit according to the third embodiment of the present invention.

FIG. 25 is a logic circuit diagram of a decoder included in the weighted average circuit.

FIG. 26 is a block diagram of a weighted average circuit according to the fourth embodiment of the present invention.

FIG. 27 is a logic circuit diagram of a first selector included in the weighted average circuit.

FIG. 28 is a logic circuit diagram of a second selector included in the weighted average circuit.

FIG. 29 is a logic circuit diagram of a decoder included in the weighted average circuit in the second example.

FIG. 30 is a block diagram of a weighted average circuit in the fifth embodiment of the present invention.

FIG. 31 is a block diagram of a second partial adder circuit included in the weighted average circuit.

FIG. 32 is a block diagram of a 4-bit carry propagation adder included in the weighted average circuit.

FIG. 33 is a block diagram of a carry propagation adder for adding 4-bit and 7-bit values in the weighted average circuit.

FIG. 34 is a block diagram of a weighted average circuit in the sixth example of the present invention.

FIG. 35 is a block diagram of a weighted average circuit in the seventh embodiment of the present invention.

FIG. 36 is a block diagram of a first adder circuit included in the weighted average circuit.

FIG. 37 is a block diagram of a second adder circuit included in the weighted average circuit.

FIG. 38 is an internal configuration diagram of a carry save adder included in the weighted average circuit.

FIG. 39 is an internal configuration diagram of a carry propagation adder included in the weighted average circuit.

FIG. 40 is a logic circuit diagram of a third selector included in the weighted average circuit.

FIG. 41 is a logic circuit diagram of a fourth selector included in the weighted average circuit.

FIG. 42 is a logic circuit diagram of a fifth selector included in the weighted average circuit.

FIG. 43 is a logic circuit diagram of a decoder included in the weighted average circuit.

FIG. 44 is a block diagram of a weighted average circuit of another embodiment.

FIG. 45 is an internal configuration diagram of a first adder circuit included in a weighted average circuit of another embodiment.

FIG. 46 is a block diagram showing a first example of a conventional weighted average circuit.

FIG. 47 is a block diagram showing a second example of a conventional weighted average circuit.

FIG. 48 is a block diagram showing a third example of a conventional weighted average circuit.

[Explanation of symbols]

101 pixel position information supply device (pixel position information supply means) 10,103 image memory (image output means) 104 pixel blending device (pixel blending means) 105 counter (blend ratio holding means) 106 blend ratio buffer (blend ratio buffer means) 107,133 data Selector (data selection means) 108,134 Attribute buffer (attribute buffer means) 109 Central processing unit (window management means) 111-113 Weighted average circuit (weighted average means) 115 Addition circuit (addition means) 116-120 Input selector (input selection means) ) 121 output selector (output selection means) 122 decoder (decoding means) 135 window information storage device (window information storage means) 136 control signal determination device (selection information output means) 201 addition circuit (addition means) 202 to 206 selector ( Selection means) 282,601,394 Decoder (control means) 287 to 29 1 1st selector (1st selecting means) 292 2nd selector (2nd selecting means) 381 1st addition circuit (1st adding means) 382-385 3rd selector (3rd 386 second adding circuit (second adding means) 387,388 fourth selector (fourth selecting means) 389 to 393 fifth selector (fifth selecting means) 232 first part Adder circuit 365 Second partial adder circuit 368 First carry propagate adder 367 Second carry propagate adder 366 Third carry propagate adder 400-404 Carry save adder 369 Sixth selection means 378 7th selection circuit (7th selection means) 380 8th selection circuit (8th selection means) 379 9th selection circuit (9th selection means)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI technical display location G06T 1/00 11/00 G09G 5/14 C 9471-5G (31) Priority claim number 6-8960 (32) Priority Day Hei 6 (1994) January 31 (33) Country of priority claim Japan (JP)

Claims (24)

[Claims] 1. An image blending circuit managed by a window so that a translucent composite image can be displayed in a window overlapping portion on a display screen in a multi-window information processing device, the raster scanning method being used for the display screen. Pixel position information supplying means for outputting pixel position information including a pixel clock for synchronization so as to display an image; and pixel position information for an image having the same size as the display screen A plurality of image output means for sequentially outputting in accordance with the above, and for storing the blend ratio information set for each pixel of the display screen, for sequentially outputting the stored blend ratio information in accordance with the pixel position information. Blend ratio buffer means for storing one blend ratio information, and storing the blend ratio information. Blending ratio holding means for repeatedly outputting the blending ratio information according to the pixel position information, and selection information set for each pixel of the display screen is stored, and the stored selection information is stored in the pixel position information. According to the selection information from the attribute buffer means, one of the attribute buffer means for sequentially outputting according to the blend ratio information from the blend ratio buffer means and the blend ratio information from the blend ratio holding means is selected. Data selection means for outputting, pixel information from each of the plurality of image output means and blend ratio information from the data selection means are synchronously input according to the pixel position information, and the input blend ratio Input from each of the plurality of image output means according to information Pixel blending means for blending and outputting the created pixel information, and the position of each window as management information of each of the plurality of windows for displaying the target image in each of the plurality of windows on the display screen, The shape size and the display object are stored, the management information is updated according to the instruction of the operator, and the storage contents of the blend ratio buffer means and the attribute buffer means are configured corresponding to the stored management information. And a window managing means for updating and updating the window managed image blending circuit. 2. An image blending circuit managed by a window so that a semitransparent composite image can be displayed in a window overlapping portion on a display screen in a multi-window information processing device, the raster scanning method being used for the display screen. Pixel position information supplying means for outputting pixel position information including a pixel clock for synchronization so as to display an image; and pixel position information for an image having the same size as the display screen A plurality of image output means for sequentially outputting in accordance with the above, and for storing the blend ratio information set for each pixel of the display screen, for sequentially outputting the stored blend ratio information in accordance with the pixel position information. Blend ratio buffer means for storing one blend ratio information, and storing the blend ratio information. Blend ratio holding means for repeatedly outputting the blend ratio information according to the pixel position information, and window information storage for storing selection information set for each pixel region corresponding to the window arrangement on the display screen Means, selection information output means for sequentially outputting the selection information stored in the window information storage means in accordance with the pixel position information, blend ratio information from the blend ratio buffer means, and blend ratio holding means Data selection means for selectively outputting any one of the blend ratio information according to the selection information output means, pixel information from each of the plurality of image output means, and the data selection means from the data selection means. The blend ratio information is synchronously input according to the pixel position information, and Pixel blending means for blending and outputting the pixel information input from each of the plurality of image output means according to the input blend ratio information, and a target image in each of the plurality of windows on the display screen. The position, shape size, and display target of each window are stored as the management information of each of the plurality of windows for displaying, and the management information is updated according to the instruction of the operator, and the stored management information is stored. And a window management means for configuring and updating the storage contents of the blend ratio buffer means and the window information storage means corresponding to the above. 3. The blend ratio holding means is provided with means for automatically updating the stored one blend ratio information in accordance with the pixel position information every time a predetermined time has elapsed. The image-blending circuit managed by the window described in 1 or 2. 4. The pixel blending means includes a plurality of weight averaging means for blending pixel information input from each of the plurality of image output means for each color component, and each of the plurality of weight averaging means. , I, j, m are integers of 2 or more, j signals expressed in i-ary are input, and the j signals are multiplied by weights respectively corresponding to the j inputs, and Addition means for adding each multiplication result and outputting the addition result as a signal expressed in i-adic notation; and 1 out of m digital input signals expressed in i-adic notation.
And j selecting means for selecting one of the signals, and the j signals respectively selected by the j selecting means are input to the adding means, a blend ratio is given, and m digital inputs are provided. The control means controls the j selection means so as to mix the signals at the given blend ratio, and the sum of the j weights of the addition means is a maximum value of the j weights. 3. The window managed image blending circuit according to claim 1, wherein the weight value is set to an integral multiple of the integer i. 5. The pixel blending means includes a plurality of weight averaging means for blending pixel information input from each of the plurality of image output means for each color component, and each of the plurality of weight averaging means. , I, j, m are integers of 2 or more, j signals expressed in i-ary are input, and the j signals are multiplied by weights respectively corresponding to the j inputs, and Addition means for adding each multiplication result and outputting the addition result as a signal expressed in i-adic notation, and j selecting one from m digital input signals and constant value signals expressed in i-adic notation The first selection means of j, the j signals respectively selected by the j first selection means are input to the addition means, and the output signals of the addition circuit and the m Select one from the digital input signals A sum of j weights of the adding means is an integral multiple of the integer i of the value of the maximum weight among the j weights. And a blending ratio is given, and a control means for controlling the j selecting means and one second selecting means is provided according to the given blending ratio. The window-blended image blending circuit according to claim 1. 6. The pixel blending means includes a plurality of weight averaging means for blending pixel information input from each of the plurality of image output means for each color component, and each of the plurality of weight averaging means. , I, j, m, n are integers of 2 or more, k is a natural number, and the first set of signals consisting of k signals expressed in i-adic number and j−k signals expressed in i-adic (j> k signals of the second set of signals consisting of k) signals are input, the j signals are multiplied by weights respectively corresponding to the j inputs, and the multiplication results are First adding means for adding and outputting the addition result as a signal expressed in i-adic notation, and 1 out of m digital input signals expressed in i-adic notation
And k third selecting means for selecting one of the signals, and k signals respectively selected by the k third selecting means are added to the first adding means as the first set of signals. And n number of signals expressed in i-adic notation are input, the n number of signals are respectively multiplied by weights corresponding to the n number of inputs, and the respective multiplication results are added, Second adding means for outputting the addition result as j-k signals expressed in i-adic number, and j-k corresponding to the number of output signals of the second adding means are provided, and corresponding second It comprises a fourth selecting means for selecting one from the output signals of the two adding means and the m digital input signals, and j selected by the jk fourth selecting means.
-K signals are input to the first adding means as the second set of signals, and n signals are selected from the m digital input signals and i-adic constant value signals. No. 5 signals are selected by the n number of fifth selection means and are input to the second addition means, a blend ratio is given, and m digital inputs are provided. 3. The window managed image blending circuit according to claim 1, further comprising control means for controlling the j selection means so that signals are mixed at the given blending ratio. 7. The data selecting means further comprises a function of selectively outputting fixed blend ratio information in addition to the blend ratio information from the blend ratio buffer means and the blend ratio holding means. 1 or 2
The described window-managed image blending circuit. 8. When i, j, and m are integers of 2 or more, j signals expressed in an i-ary number are input, and weights corresponding to the j inputs are respectively applied to the j signals. Multiplying, adding the respective multiplication results, and outputting the addition result as a signal expressed in i-adic notation, and 1 out of m digital input signals expressed in i-adic notation.
And j selecting means for selecting one of the signals, and the j signals respectively selected by the j selecting means are input to the adding means, a blend ratio is given, and m digital inputs are provided. The control means controls the j selection means so as to mix the signals at the given blend ratio, and the sum of the j weights of the addition means is a maximum value of the j weights. A weighted averaging circuit, characterized in that the weight value is set to an integral multiple of the integer i. 9. The weighted average circuit according to claim 8, wherein the sum of j weights of the adding means is 1. 10. An i-adic representation of j signals is input, where i, j, and m are integers of 2 or more, and weights corresponding to the j inputs are given to the j signals, respectively. Multiply, add each multiplication result, and output the addition result as a signal expressed in i-adic notation; and one of the m digital input signals and constant value signals expressed in i-adic notation. J number of first selecting means for selecting, j number of signals respectively selected by the j number of first selecting means are input to the adding means, and an output signal of the adding circuit and It is provided with one second selecting means for selecting and outputting one of the m digital input signals, and the sum of the j weights of the adding means is the maximum among the j weights. When the value weight value is set to an integral multiple of the integer i, A weighted average, wherein a blending ratio is given, and a control means for controlling the j first selecting means and the one second selecting means according to the given blending ratio is provided. circuit. 11. i, j, m, and n are integers of 2 or more,
Let k be a natural number, and j of the first set of signals consisting of k signals expressed in i-adic number and the second set of signals consisting of jk (j> k) signals expressed in i-adic number. Signals are input, the j signals are respectively multiplied by the weights corresponding to the j inputs, the respective multiplication results are added, and the addition result is regarded as a signal expressed in i-adic number. 1st adding means for outputting and 1 out of m digital input signals expressed in i-adic number
And k third selecting means for selecting one of the signals, and k signals respectively selected by the k third selecting means are added to the first adding means as the first set of signals. And n number of signals expressed in i-adic notation are input, the n number of signals are respectively multiplied by weights corresponding to the n number of inputs, and the respective multiplication results are added, Second adding means for outputting the addition result as j-k signals expressed in an i-adic number, and j-k corresponding to the second adding means are provided. An output signal and a fourth selection means for selecting one from the m digital input signals are provided, and j selected by the jk fourth selection means.
-K signals are input to the first adding means as the second set of signals, and n signals are selected from the m digital input signals and i-adic constant value signals. No. 5 signals are selected by the n number of fifth selection means and are input to the second addition means, a blend ratio is given, and m digital inputs are provided. A weighted averaging circuit comprising control means for controlling the j selection means so as to mix signals at the given blending ratio. 12. The output signal of the addition means or the first addition means is reduced in the number of digits expressing the output signal from the minimum digit by a predetermined digit, and the addition means or the first addition means approximates the addition result. Is output.
Alternatively, the weighted average circuit according to item 11. 13. The weighted average circuit as claimed in claim 8, wherein the integer i is i = 2. 14. A value is rounded down when the value of the maximum digit is “0” among the digits to be reduced, and is rounded up when the value of the maximum digit is “1”. 13. The weighted average circuit described in 13. 15. The weights of the adding means or the first adding means are such that a number sequence in which the weights are arranged in descending order forms a geometrical sequence having a common ratio of 1/2, except for the last term of the number sequence. 15. The weighted average circuit of claim 13, wherein the value of the last term of the sequence is equal to the value of the term immediately preceding the last term. 16. The adder or the first adder adds j signals which are input signals of the adder or the first adder, and outputs the addition result as two binary-displayed signals. And a second partial adder circuit for adding the two output signals of the first partial adder circuit and outputting the addition result as one binary-represented signal, The output signal of the second partial adder circuit is used as the output of the adder means or the first adder means, and the first partial adder circuit is configured by connecting a plurality of carry save adders in series in a plurality of stages. The second partial adder circuit adds the input signals from the least significant bit to the predetermined intermediate bit of the second partial adder circuit, and outputs the addition result and the carry result generated from the intermediate bit. A first carry propagation adder for outputting, Note When the carry result of the first carry propagation adder is assumed to be 0, the input signals of the bits higher than the intermediate bit of the second partial adder circuit are added, and the addition result is output. A second carry-propagate adder, and a bit higher than the intermediate bit of the second partial adder circuit, assuming that the carry result of the first carry-propagate adder is 1. A third carry propagation adder for adding input signals and outputting a result of the addition; and a carry result of the first carry propagation adder being 0,
And a sixth selecting means for selecting the output of the second carry propagation adder and, when the carry result is 1, selecting and outputting the output of the third carry propagation adder. 14. The weighted average circuit according to claim 13, wherein: 17. The integer i is i = 2, and the adding means adds the j signals which are the input signals of the adding means, and outputs the addition result as two binary-displayed signals. And a second partial adder circuit that adds the two output signals of the first partial adder circuit and outputs the addition result as one binary-represented signal. The output signal of the partial adder circuit is the output of the adding means, and the first partial adder circuit is configured by connecting a plurality of carry save adders in series in a plurality of stages, and the second partial adder circuit Is a first carry propagation addition which adds the input signals from the least significant bit to the predetermined intermediate bit of the second partial adder circuit, and outputs the addition result and the carry result generated from the intermediate bit. And a carry of the first carry propagation adder A second carry propagation adder for adding input signals of bits higher than the intermediate bits of the second partial adder circuit, assuming that the result is 0, and outputting the addition result; When it is assumed that the carry result of the first carry propagation adder is 1, the input signals of the bits higher than the intermediate bit of the second partial adder circuit are added, and the addition result is output. And a third carry propagation adder, wherein the second selection means comprises: seventh selection means for selecting one from the m digital input signals; and the first carry propagation adder. Output showing the addition result of
Eighth selecting means for selecting one of the least significant bit to the intermediate bit of the output of the seventh selecting means, the output of the second carry propagation adder, and the third Of the carry propagating adder and the output of the seventh selecting means, and the ninth bit selecting means for selecting any one of the upper bits of the intermediate bits. The weighted average circuit according to claim 10. 18. The number of signals (jk) belonging to the second set.
12. The weighted average circuit according to claim 11, wherein is 2. 19. The integer i is i = 2, and each weight of the first adding means has a first number sequence in which the respective weights are arranged in descending order except for the last term of the first number sequence. , A geometric progression with a common ratio of ½, the value of the first term of this first sequence is ½, and the value of the last term of the first sequence is immediately before the last term. Equal to the value of the terms, the weights of the last two terms of the first sequence are each multiplied with each of the two signals of the second set, and each weight of the second summing means increases its respective weight by The second numerical sequence arranged in order forms a geometric progression having a common ratio of 1/2, except for the last term of the second numerical sequence, and the value of the first term of the second numerical sequence is the first numerical value. 19. The weighted average circuit according to claim 18, wherein the value of the last term of the number sequence is equal to the value of the last term of the second number sequence is equal to the value of the immediately preceding term. 20. The integers j, m and n are j = 6 and m =, respectively.
20. The weighted average circuit according to claim 19, wherein n = 5. 21. The control means selects, when the given blend ratio indicates mixing of m digital signals, the first selection circuit selects any one of the m digital signals. , The first selecting means and the second selecting means are controlled so that the second selecting means selects the output of the first adding circuit, and the given blending ratio is any one of the m digital signals. In the equivalent case of selecting one, the first selecting means selects the constant value and the second selecting means selects the indicated one of the m digital input signals. 11. The weighted average circuit according to claim 10, further comprising: controlling the first selecting means and the second selecting means. 22. The control means is inputted with an operation selection signal for selecting and instructing either operation or stop of the second adding means, and the operation selecting signal selects the operation of the second adding means. If it is a signal, all of the fourth selecting means select the output of the second adding means, and the third selecting means and the fifth selecting means each have m number of outputs depending on the given blending ratio. All of the fifth selecting means are controlled by controlling each of the selecting means so as to select one of the digital input signals, and when the operation selecting signal is a signal for selecting stop of the second adding circuit. Selects a constant value signal, and the third selecting means and the fourth selecting means select each one of the m digital input signals in accordance with the given blending ratio. The load level according to claim 10, wherein the load level is controlled. Equalizer circuit. 23. Each selection means inputs a selection control signal and selects one from a plurality of signals according to the input selection control signal, and the control means has a code for describing a blend ratio. 12. The decoder according to claim 8, wherein the decoder is configured to generate a selection control signal to each selection unit according to the input code. Weighted average circuit. 24. The decoder generates the operation selection signal based on an input code, instead of inputting an operation selection signal for selecting and instructing either operation or stop of the second adding means. The weighted average circuit according to claim 23, wherein: