JP2011123894A - Antialiasing using multiple display heads of graphics processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the antialiasing of image data using multiple display heads of one graphic processor. <P>SOLUTION: Two display heads 206 of the same graphics processor 122 are coupled to each other in a master/slave configuration via a pixel transfer path. The "master" display head receives pixels from the "slave" display head in addition to its own pixels, and pixel selection logic in the master display head blends the two pixels or select one to the exclusion of the other. When the two pixels correspond to different sampling locations in the same display pixel, the blended pixel is an antialiased pixel. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

Cross-reference of related applications

[0001] This application is filed on May 12, 2006, entitled “Antialiasing Using Multiple Display Heads of a Graphics.
US Provisional Application No. 60 / 747,154 entitled "Processor" and "Distributed Antialiasing in a Multiprocessor Graphics" filed May 12, 2006, co-pending by the same applicant.
Claims the benefit of US patent application Ser. No. 11 / 383,048 entitled “System”.

Background of the Invention

  [0002] The present invention relates generally to computer graphics, and more particularly to anti-aliasing of image data using multiple display heads of a graphics processor.

  [0003] As is known in the art, computer-generated images are susceptible to various visual artifacts that result from the finite sampling resolution used to convert image data into an array of discrete color samples (pixels). Such artifacts commonly referred to as “aliasing” include smooth line jaggy, regular pattern irregularities, and the like.

  [0004] To reduce aliasing, colors are often "oversampled", that is, sampled at a number of sampling locations that exceeds the number of pixels that make up the final (eg, display or storage) image. For example, an image may be sampled at twice or four times the number of pixels. In this field, super-sampling in which each sampling position is treated as a separate pixel, or one color value is calculated for each basic shape covering at least a part of the pixel. The pixel coverage by this basic shape is calculated at a plurality of positions. Various oversamplings are known, including multisampling to determine.

  An anti-aliasing (AA) filter mixes multiple samples per pixel to determine one color value. Conventionally, AA filters are applied either in a rendering pipeline that generates pixels and stores them in a frame buffer, or in a display pipeline that reads pixels from the frame buffer and sends them to a display device.

  [0006] Embodiments of the present invention provide systems and methods that utilize multiple display heads of a single graphics processor to perform anti-aliasing and other processing tasks. In one embodiment, two display heads of the same graphics processor are coupled together in a master / slave fashion via a pixel transfer path. The “master” display head receives pixels from the “slave” display head in addition to its own pixels, and the pixel selection logic in the master display head mixes the two pixels and selects one of them. Exclude the other. When two pixels correspond to different sampling positions of the same image, the mixed pixel is an AA filter processing pixel.

  [0007] According to one aspect of the invention, a graphics processing apparatus includes a first display head, a second display head, and a pixel transfer path. The first display head is configured to generate a first output pixel and is disposed in the integrated circuit. The second display head is configured to generate a second output pixel, which is also disposed in the integrated circuit. The second display head includes a first input path configured to receive external pixels, a second input path configured to receive internal pixels, the first input path, and the first input path. A pixel synthesizer coupled to two input paths and configured to mix the external pixel and the internal pixel to generate the mixed pixel; and one of the external pixel, the internal pixel, or the mixed pixel And a selection circuit configured to select one as the second output pixel. The pixel transfer path moves the first output pixel from the first display head to the second display head such that the first output pixel is received as the external pixel by the first input path. To the first input path.

  [0008] In some embodiments, the pixel transfer path is also located in an integrated circuit. In other embodiments, at least a portion of the pixel transfer path is external to the integrated circuit. For example, the pixel transfer path includes a removable connector.

  [0009] According to another aspect of the invention, a graphics subsystem includes a graphics adapter having a pixel output connector and a pixel input connector. A graphics processor may be implemented on the graphics adapter, but has a pixel output port communicatively coupled to the pixel output connector and a pixel input port communicatively coupled to the pixel input connector. . The graphics subsystem also includes a removable connector unit adapted to connect the pixel output connector of the graphics adapter to the pixel input connector of the graphics adapter.

  [0010] According to yet another aspect of the invention, a method for generating an image renders a first set of input pixels and a second set of input pixels for an image using a graphics processor's rendering pipeline. Including the steps of: The first rendering operation used to render the first set of input pixels differs from the second rendering operation used to render the second set of input pixels at least at one point. For example, the two rendering operations may differ with respect to the sampling pattern applied to each pixel or with respect to the field of view offset of the rendered image. The first set of input pixels is sent to the first display head of the graphics processor, and the second set of input pixels is sent to the second display head of the graphics processor. The first set of input pixels is further sent from the first display head to the second display head. In the second display head, corresponding pixels of the first set of input pixels and the second set of input pixels are mixed to generate a set of output pixels.

  [0011] The following detailed description, together with the accompanying drawings, will provide a better understanding of the nature and advantages of the present invention.

Detailed Description of the Invention

  [0020] Embodiments of the present invention provide systems and methods that utilize multiple display heads of a graphics processor to perform anti-aliasing and other processing tasks. In one embodiment, two display heads of the same graphics processor are coupled together in a master / slave fashion via a pixel transfer path. The “master” display head receives pixels from the “slave” display head in addition to its own pixels, and the pixel selection logic in the master display head mixes the two pixels and selects one of them. Exclude the other. When two pixels correspond to different sampling positions of the same image, the mixed pixel is an AA filter processing pixel. [System overview]

  [0021] FIG. 1 is a block diagram of a computer system 100 according to an embodiment of the invention. The computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 that communicates via a bus path including a memory bridge 105 such as a north bridge chip. The memory bridge 105 is connected to an I / O (input / output) bridge 107 such as a south bridge chip via a bus or other communication path 106. The I / O bridge 107 receives user input from one or more user input devices 108 (keyboard, mouse, etc.), and transfers the input to the CPU 102 via the bus 106 and the memory bridge 105. The visual output is provided on a pixel-based display device 110 (conventional CRT or LCD-based monitor) that operates under the control of a graphics subsystem 112 coupled to the memory bridge 105 via a bus or other communication path 113. The The system disk 114 is also connected to the I / O bridge 107. The switch 116 connects between the I / O bridge 107 and other components such as the network adapter 118 and various add-in cards 120 and 121. Other components (not explicitly shown) such as USB or other port connection, CD drive, DVD drive, etc. can also be connected to the I / O bridge 107. The communication path between the various components may be implemented using PCI (Peripheral Component Interconnect), PCI Express (PCI-E), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point protocol. The connection between different devices can use different protocols known in the art.

  The graphics subsystem 112 includes N (one or more) graphics processing units (GPUs) 122. (In this document, examples of similar objects are indicated by a reference number identifying the object and, optionally, parenthesized numbers identifying the example.) Each GPU 122 is associated with an associated graphics memory 124. Have GPU 122 and graphics memory 124 may be implemented using one or more integrated circuit devices such as, for example, programmable processors, application specific integrated circuits (ASICs), and memory devices. In some embodiments, the GPU 122 and graphics memory 124 are implemented with one or more expansion cards or other adapters that can be inserted into or removed from expansion slots (such as PCI-E slots) in the system 100. The Any number N of GPUs 122 may be used.

  [0023] Each GPU 122 is associated with generating pixel data (also referred to herein as "pixels") from graphics data supplied from CPU 102 and / or system memory 104 via memory bridge 105 and bus 113. It can be configured to perform various tasks, and exchanges information with each graphics memory 124 to store or update pixel data or the like. For example, the GPU 122 can generate pixel data from 2D or 3D scene data provided by various programs executed on the CPU 102. The GPU 122 can also write pixel data received via the memory bridge 105 into the graphics memory 124 with or without further processing. Each GPU 122 also includes a scan-out module (also referred to herein as a display pipeline) that can be configured to send pixel data from the graphics memory 124 to an output port of the GPU 122 described below. The output port may or may not be connected to a monitor or another GPU 122.

  [0024] For operation in a distributed rendering mode, one GPU (eg, GPU 122 (0)) is preferably configured to send scanned out pixels to another GPU (eg, GPU 122 (N-1)). The latter GPU (eg, GPU 122 (N-1)) selects between the internal pixels from its own display pipeline and the external pixels received from GPU 122 (0). More than two GPUs 122 can be interconnected in a “daisy chain” fashion so that the slave GPU 122 sends its pixels to the intermediate GPU 122, which selects between its own internal pixels and external pixels from the slaves. Thus, the selected pixel is transferred to another GPU or the like until the final master GPU (that is, the GPU connected to the monitor) sends the final selected pixel to the display device.

  [0025] In some embodiments, GPUs 122 can be interconnected with each other by adjusting the configuration settings of GPUs 122 without changing any physical connection so that any GPU 122 can be a slave of any other GPU 122. is there. For example, the GPU 122 can be connected in a unidirectional or bidirectional ring topology.

  [0026] Various distributed rendering modes can be supported. For example, in split frame rendering, different GPUs 122 are assigned to render different portions of the same image, and in alternating frame rendering, different GPUs 122 are assigned to different images in the displayed sequence of images. The invention does not require a particular distributed rendering mode.

  [0027] According to embodiments of the present invention, GPU 122 is also operable in "externally distributed" AA mode. In this mode, the pixel selection logic of the GPU 122 selects one of the internal and external pixels and mixes them instead of excluding the other. When the internal pixel and the external pixel represent the same image at different sampling positions, the result of pixel mixing corresponds to an AA resolution operation (also referred to as an AA filter in this specification). According to another embodiment of the invention, one GPU 122 can also operate in “internally distributed” AA mode. In this mode, the pixel selection logic of the GPU 122 mixes the pixels generated by two display heads of the same GPU 122. Examples of distributed AA modes (including external and internal distribution modes) and associated pixel selection logic are described below.

  [0028] In some embodiments, some or all of the GPUs 122 may be operable in an "independent rendering" mode in which different ones of the plurality of GPUs 122 render images for different display devices. Images rendered by different GPUs 122 in independent rendering mode may or may not be related to each other. Of course, the GPU 122 can be configured to operate in any of the above or other modes.

  [0029] The CPU 102 operates as a master processor of the system 100 and controls and coordinates the operation of other system components. In particular, the CPU 102 issues a command for controlling the operation of the GPU 122. In some embodiments, CPU 102 writes a command stream for GPU 122 to a command buffer, which may be system memory 104, graphics memory 124, or another storage location accessible to both CPU 102 and GPU 122. it can. The GPU 122 reads the command stream from the command buffer and executes the command asynchronously with the operation of the CPU 102. The commands include conventional rendering commands for generating images and general-purpose computer commands that allow applications running on the CPU 102 to take advantage of processing capabilities for data processing that are not related to GPU 122 image generation. be able to.

  [0030] It will be appreciated that the system shown herein is illustrative and that changes and modifications are possible. The interconnect topology, including the number and arrangement of bridges, can be modified as desired. For example, in some embodiments, system memory 104 is connected directly to CPU 102 rather than via a bridge, and other devices communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, the graphics subsystem 112 is connected to the I / O bridge 107 instead of the memory bridge 105. In another embodiment, the I / O bridge 107 and the memory bridge 105 can be integrated in one chip. The particular components shown herein are optional, and may support any number of add-in cards or peripheral devices, for example. In some embodiments, switch 116 is eliminated and network adapter 118 and add-in cards 120, 121 connect directly to I / O bridge 107.

  [0031] The connection of the GPU 122 to other parts of the system 100 may also be changed. In some embodiments, graphics system 112 is implemented as one or more expansion or add-in cards that can be inserted into expansion slots of system 100. In other embodiments, the GPU is integrated on a single chip with a bus bridge such as the memory bridge 105 or I / O bridge 107.

  [0032] Each GPU can be provided with any amount of local graphics memory (including situations without local memory), and local memory and system memory can be used in any combination. For example, in a unified memory architecture (UMA) embodiment, no dedicated graphics memory device is provided, but some or all of the GPUs use system memory exclusively or almost exclusively. In UMA embodiments, the GPU can be integrated into a bus bridge chip, or it can be provided as a separate chip with a high speed bus (eg, PCI-E) that connects the GPU to the bridge chip and system memory.

  [0033] In addition, GPUs embodying aspects of the present invention may be used in various devices such as general purpose computer systems, video game consoles and other special purpose computer systems, handheld devices such as DVD players, mobile phones or personal digital assistants. Can be incorporated. [GPU with multiple display heads]

  [0034] FIG. 2 is a block diagram of a pixel output path within GPU 122 that can be used to implement the present invention. Although a multi-GPU graphics system may not be required for embodiments of the present invention, GPU 122 is preferably configured for use in such a system.

  In particular, as shown in FIG. 2, GPU 122 includes a display (or scan-out) pipeline 202 coupled to memory interface 204. Display pipeline 202 is also coupled to display head 206a ("Head A") and display head 206b ("Head B"). The GPU 122 has a plurality of output ports 210 to 213 including digital output ports 210 and 211 and analog output ports 212 and 213. The GPU 122 also has two multipurpose input / output (MIO) ports 214a ("MIOA") and 214b ("MIOB") that can be configured for a variety of purposes, including communication with another GPU or another external digital device. is doing. The display heads 206a and 206b are connected to the output ports 210 to 213 and the MIO ports 214a and 214b via the crossbar 220, respectively.

  [0036] The memory interface 204 is coupled to a memory (not shown in FIG. 2) that stores pixel data generated by the GPU 122, such as the graphics memory 124 of FIG. Display pipeline 202 communicates with memory interface 204 to access stored pixel data. The display pipeline 202 sends pixel data to either or both display heads 206a, 206b. In some embodiments, the display pipeline 202 performs various processing operations on the pixel data before sending it to the display heads 206a, 206b. The pixel data that is sent to the display head 206a includes pixel data addressed to the display head 206b and May or may not be treated differently. In addition, the pixel data provided to the display pipeline 202 for processing and delivery to the display head 206a is the same or different from the pixel data provided to the display pipeline 202 for processing and delivery to the display head 206b. Also good. In the present invention, specific configurations of the display pipeline 202 and the memory interface 204 are not essential, and a detailed description thereof will be omitted.

  [0037] The digital output ports 210, 211 may generally be of conventional design and may include circuitry that modifies pixel data to comply with a digital output standard. For example, in one embodiment, each of the ports 210 and 211 implements TMDS (Transition Minimized Differential Signaling) for a standard DVI (Digital Video Interface) connector. Similarly, the analog output ports 212, 213 may generally be of conventional design and may include, for example, digital to analog converters, many examples compliant with any analog video standard known in the art. It will be appreciated that the present invention does not require the presence, number or nature of a particular digital or analog output port.

  [0038] The MIOA port 214a and the MIOB port 214b can be set as output ports that send pixel data generated by either of the display heads 206a, 206b onto the output line of the GPU 122. The MIOA port 214a and the MIOB port 214b can also be set as input ports for sending external pixel data to the display head A 206a or the display head B 206b. In some embodiments, the MIOA port 214a and the MIOB port 214b can each be individually configured as either an input port or an output port. The settings of the MIOA port 214a and MIOB port 214b can be determined during system startup or dynamically modified at various times during system operation. For example, each MIO port can include a control register that stores a value that specifies the port setting, and a new value can be written to the register at system startup or at other times as desired.

  [0039] Head A 206a and Head B 206b are coupled to output ports 210-213 as well as MIO ports 214a, 214b, respectively, via crossbar 220. In this embodiment, crossbar 220 supports any connection from head A 206a to any one of ports 210-213, 214a or 214b, and at the same time from head B 206b by crossbar 220 to head A 206a. Can be configured to support any connection to any one of ports 210-213, 214a, or 214b that are not connected to. For example, GPU 122 can send pixel data simultaneously from heads 206a, 206b to two different monitors (eg, via any two of digital output ports 210, 211 and / or analog output ports 212, 213). It is. Alternatively, the GPU 122 can send pixel data simultaneously to a monitor via one of the ports 210-213 and to another GPU via the MIOA port 214a or MIOB port 214b. In some examples, one or both of the display heads 206a, 206b can be idle, i.e., not sending pixels to any output port.

  [0040] The MIO ports 214a, 214b can also be configured to receive pixel data from another one of the GPUs 122 and communicate the received pixel data into the display heads 206a, 206b. Each GPU 122 has an “external” pixel received from one of the MIO ports 214a, 214b in each display head 206a, 206b, an “internal” pixel received from its own display pipeline 202, or a combination of internal and external pixels. A pixel selection logic circuit (to be described later).

  [0041] In some embodiments, the crossbar 220 is configured at system startup, and in other embodiments, the crossbar 220 can be dynamically configured so that connections can be changed during system operation. Crossbar 220 may also be configurable to couple input pixel data received on one of MIO ports 214a, 214b to either display head 206a, 206b.

  [0042] FIG. 3A is a block diagram of a pixel selection logic circuit 300 in the display head 206a of GPU 122 according to an embodiment of the present invention. Of course, the display head 206b can have a similar design of pixel selection logic. In some embodiments, each display head 206 a, 206 b of GPU 122 has its own pixel selection logic 300.

  [0043] The pixel selection logic 300 receives internal pixels from the display pipeline 202 of FIG. If the MIOA port 214a of FIG. 2 (or MIOB port 214b in some embodiments) is configured as an input port, the pixel selection logic 300 also receives external pixels on the second path 304.

  [0044] The external and internal pixels are each propagated to the pixel composition circuit 306, which mixes the external and internal pixels to produce a mixed pixel. The pixel synthesis circuit 306 can be implemented using, for example, a conventional arithmetic logic circuit. In one embodiment, the pixel synthesis circuit 306 includes a first divider circuit 308 that divides the internal pixel by one of a number of candidate divisors (eg, 1, 2, 4, etc.) and the internal pixel (after division) as an external An addition circuit 310 that adds to the pixels to generate a total pixel, a selection circuit 312 that selects between the internal pixels and the total pixels in response to a control signal (PSEL1), and a number of candidate divisors (for example, And a second divider circuit 314 that divides by one of the two, and gives the result as a mixed pixel on path 316.

  [0045] External pixels on path 304 and mixed pixels on path 316 are passed to selection circuit 318 (such as a multiplexer). In response to the control signal (PSEL2), the selection circuit 318 selects either the internal pixel, the mixed pixel, or the external pixel to send to the output path 320 connected to the crossbar 220 of FIG.

  [0046] The PSEL1 and PSEL2 signals are preferably generated by control logic (not explicitly shown) in the display head 206a. In some embodiments, this control logic, which may be of a generally conventional design, is responsive to control information generated by a graphics driver program executing on the GPU 102 of FIG. For example, similar control information can also be used to control the operation of the pixel synthesizer 308 by selecting between candidate divisors for the divider circuits 308, 314 to generate a suitable weighted average for a particular application. it can. Those skilled in the art who can utilize the teachings of the present invention can implement control logic suitable for generating PSEL and pixel synthesizer control signals, and thus a detailed description of the control logic is omitted.

  [0047] FIG. 3B is a block diagram of pixel selection logic 350 according to an alternative embodiment of the present invention. The pixel selection logic circuit 350 is generally similar to the pixel selection logic circuit 300 of FIG. 3A, but is suitably designed with the ability to mix gamma correction pixels. Pixel selection logic 350 receives internal pixels from display pipeline 202 of FIG. 2 on first path 352. Internal pixels are propagated to the pixel synthesizer 358. If the MIOA port 214a is set as an input port, the pixel selection logic circuit 350 also receives external pixels on the second path 354. This external pixel is also propagated to the pixel synthesizer 358.

[0048] The pixel synthesizer 358 mixes the internal and external pixels, resulting in a mixed pixel on a single pass 360. Pixel synthesizer 358 may include a divider circuit similar to divider circuit 306 in FIG. 3A and / or an adder similar to adder circuit 308 in FIG. 3A. In addition (or alternatively), pixel synthesizer 358 may also include arithmetic logic that mixes the gamma correction pixels received on paths 352 and 354. As is known in the art, gamma correction adjusts pixel values to a non-linear scale that produces a linear intensity response at the display device, for example, by converting pixel value P to P ^γ for a constant γ. (For a typical display device, the constant γ is approximately 2.0 to 2.5.) In such an embodiment, for γ≈2.2, the γ corrected output pixel P _o ^γ is It is possible to calculate using
P _o ^γ = (4P _i ^γ + 4P _e ^γ + | P _i ^γ -P _e ^γ |) / 4

[0049] where P _i ^γ and 4P _e ^γ represent the gamma correction pixels provided on paths 352 and 354. One skilled in the art will recognize that Equation 1 provides an acceptable approximation using simple hardware rather than the calculations required for exact results. (For example, multiplication and division by 4 can be implemented as a bit shift.) It will also be appreciated that other approximations can be substituted.

  [0050] Referring back to FIG. 3B, the selection multiplexer 362 receives internal pixels on path 352, external pixels on path 354, and mixed pixels on path 360. In response to the pixel selection signal (PSEL), the selection multiplexer 362 selects one of these candidate pixels for transmission to the output path 364 that connects to the crossbar 220 of FIG. The output path 364 can include a second divider circuit 366, which may be similar to the divider circuit 314 of FIG. 3A. In an alternative embodiment, two selection multiplexers similar to those shown in FIG. 3A are used for output pixel selection, but a divider circuit 366 may be placed in front of the second selection multiplexer. Other selection circuit configurations can also be used.

  [0051] In some embodiments, the pixel synthesizer 350 operates on either a gamma corrected pixel and a non-gamma corrected (linear) pixel using simple addition if the pixel is not gamma corrected. It can be set. This setting is advantageously performed by the graphics driver during the startup operation (system startup). Of course, no gamma correction filter is required, but in some embodiments, any gamma correction can be applied after final pixel selection. [Distributed anti-aliasing using multiple GPUs]

[0052] The GPU 122 of FIG. 2 with the pixel selection logic 300 or the pixel selection logic 350 can be suitably used for distributed anti-aliasing operations in a system with more than one GPU 122. FIG. 4A is a simplified block diagram of a graphics subsystem 400 having two GPUs 122 (0) and 122 (1) in a master / slave read configuration. (For clarity, only active ports and display heads are shown. In this example, only one display head is used per GPU.) Slave GPU 122 (1) has its MIOA port 214a (1) as its output port. The master GPU 122 (0) has its MIOA port 214a (0) set as an input port. MIOA port 214a (1) is coupled to the MIOA port 214a (0), passing the output pixel _{P o1} from the slave GPU 122 (1) and to the master GPU 122 (0).

[0053] The head A 206a (1) of the slave GPU 122 (1) transfers the pixel P _i1 provided by the display pipeline 202 (1) of the slave GPU 122 (1) to the MIOA port 214a (1) as an output pixel. The output pixel P _o1 from the slave GPU 122 (1) is received by the MIOA port 214a (0) of the master GPU 122 (0), which transfers the pixel to the display head A 206a (0). In the head A 206 a (0), the pixel selection logic circuit 300 (0) (an example of the pixel selection logic circuit 300 in FIG. 3) is connected to the internal pixel Pi 0 and the slave GPU 122 from the display pipeline 202 (0) of the master GPU 122 (0). It operates to select the external pixel P _o1 derived from the display pipeline 202 (1) of (1) or the sum (eg, P _i0 + P _o1 ) supplied by the adder circuit 308.

[0054] Head A 206a (0) of master GPU 122 (0) sends the selected pixel (P _final ) to an output port, in this case, digital output port 210 (0). The head A 206a (0) of the GPU 122 (0) can also be set to send pixel data to the MIOA port 214b (0) (not explicitly shown in FIG. 2C), which is connected to the MIO port of the third GPU 122. Thus, it will be appreciated that the third GPU 122 is mastered by GPU 122 (0). In this way, any number of GPUs 122 can be connected in a daisy chain manner.

  [0055] According to embodiments of the present invention, GPUs 122 (0) and 122 (1) may be used in an external distributed anti-aliasing (AA) mode. In this mode, each GPU 122 renders the same image with some change in display parameters or sampling parameters such that the sampling position used by GPU 122 (0) is different from the sampling position used by GPU 122 (1). For example, a slightly different display area or display surface normal may be defined for the two GPUs 122 to create a small offset at the pixel boundary of the two images. Alternatively, if the sampling position within a pixel can be set (eg, by a graphics driver), each GPU 122 can be set to use the same set of display parameters and a different sampling position within each pixel.

[0056] In the distributed AA mode, the external pixel P _o1 and the internal pixel P _i0 received by the pixel selection logic circuit 300 (0) at the display head 206a of the GPU 122 (0) are different sampling positions for the same pixel of the final image. Corresponding to By averaging the internal and external pixels, anti-aliasing twice the display resolution is obtained. More specifically, the selection multiplexer 310 is set to select the pixel sum P _o1 + P _i0 provided by the addition circuit 308, and the division circuit 316 is set to divide the selected pixel sum by two. _Therefore , the final pixel is P _final = (P _o1 + P _i0 ) / 2. In this way, the pixel selection logic circuit 300 can implement a 2 × AA filter.

  [0057] Note that GPUs 122 (0) and 122 (1) are also operable in other distributed rendering modes, including a mode in which one of the internal or external pixels is selected to exclude the other. The particular choice will depend on details of the distributed rendering mode, for example whether different GPUs 122 render different parts of the same frame or different consecutive frames, but are not relevant to the present invention. If there are three or more GPUs 122, more advanced anti-aliasing can be achieved. For example, any number of GPUs 122 can be daisy-chained using their respective MIOA and MIOB ports, and each GPU in the daisy chain uses its appropriate weighting factor to transmit its own internal image to the upstream GPU. Can be mixed with external images received from

  [0058] It will be appreciated that the display head, pixel selection logic, and distributed AA operation described herein are exemplary and can be changed and modified. For example, the division circuit of the present specification supports division by a small number of discrete divisors. In other embodiments, the divider circuit may support more discrete divisors (including arbitrarily selected divisors) so that a wide range of anti-aliasing filters are supported. In addition, the division circuits can be arranged at positions different from those described in this specification, and the number of division circuits can be modified. For example, a divider circuit can be placed on the external pixel path in addition to or instead of the internal pixel path.

  [0059] The particular configuration of the selection circuit 318 may be modified. A person skilled in the art can use any circuit element or combination of circuit elements that can be controllably selected between internal pixels, external pixels and mixed pixels obtained from both internal and external pixels as a selection circuit. You will understand.

  [0060] As used herein, a "pixel" is generally any representation of a color value sampled at a location in an image or such value (eg, as generated by the adder circuit 308 of FIG. 3). ). By rendering the pipeline with the GPU, pixels are generated at a nominal resolution (where resolution refers to the number of pixels in the image), which may or may not match the resolution of the display device. In some embodiments, the display pipeline performs any up-filtering or down-filtering required to convert nominal resolution to display resolution.

  [0061] The labeling of the MIO port and display head herein as "A" and "B" herein is for convenience of description only. Of course, any MIO port can be connected to any other MIO port, and any display head can drive any MIO port when that port is configured as an output port. In addition, some GPUs may include more than two or less than two MIO ports and / or more than two or less than two display heads.

  [0062] In general, the present invention can be implemented using any one port or multiple ports allowing one GPU to communicate pixel data with another GPU as an I / O port. In some embodiments, as described above, the MIO port can also be configured for purposes other than communicating with another GPU. For example, the MIO port can be set to communicate with various external devices such as a TV encoder. Some embodiments may support DVO (Intel Digital Video Output Interface) or other video output standards. In some embodiments, the settings for each MIO port are determined when assembling the graphics adapter. At system startup, the adapter informs the system about its MIO port settings. In other embodiments, the MIO port can be replaced with a dedicated input or output port.

  [0063] Aspect settings for I / O ports, display heads, and other graphics subsystems can be accomplished by a system settings unit configured to communicate with all graphics processors. In some embodiments, the system configuration unit is implemented in a graphics driver program that runs on the CPU of a system that includes a multiprocessor graphics subsystem. Any other suitable agent including any combination of hardware and / or software components can be used as the system configuration unit. [Internally distributed anti-aliasing]

  [0064] According to embodiments of the present invention, two display heads 206a, 206b of one GPU 122 can be coupled together in a master / slave fashion. In this format, the GPU 122 can perform “internally distributed” AA filtering using the pixel selection logic 300 of the display head (eg, display head A 206a) operating as a master.

  [0065] FIG. 4B is a block diagram of GPU 122 showing display head 206a connected to display head 206b in a master / slave format in accordance with an embodiment of the present invention. Of course, the GPU 122 of FIG. 4B is identical to the GPU 122 of FIG. In FIG. 4B, only active I / O ports are shown, and the crossbar 220 is not shown. The display pipeline 202 of FIG. 4B is shown having two parallel sections. A display pipeline A 402a that sends pixels to the display head 206a and a display pipeline B 402b that sends pixels to the display head 206b. The display pipelines A 402a and B 402b can each be a conventional design, and each can perform various pixel processing operations. Display pipelines 402a and 402b can perform the same or different operations as desired.

  [0066] The MIOB port 214b is coupled to the MIOA port 214a of the same GPU 122 via the pixel transfer path 400. The pixel transfer path 400 transfers the pixels generated by the display head B 206b from the MIOB port 214b to the MIOA port 214a. The MIOA port 214 a sends the received pixel to the display head A 206 a of the GPU 122. The pixel transfer path 400 can be implemented using any suitable signal transfer technique. An example is described below.

[0067] From the perspective of display head A 206a, pixels received from display head B 206b are indistinguishable from pixels received from different GPUs. Thus, for example, any of the “internal” pixel (P _A ) derived from the head _A 206 a, the “external” pixel (P _B ) derived from the head _B 206 _b , or a mixed pixel created from the pixels P _A and P _B by the pixel synthesis circuit 308 The pixel selection logic circuit 300 of the display head A 206a is operable to select one as the output pixel. (Pixel P _B is “external” to display head A 206a in the sense that pixel P _B is not provided to display head A 206a by display pipeline _A 402a, unlike pixel PA.)

  [0068] In this configuration, the GPU 122 can be used to perform "internal dispersion" AA by two display pipelines 402a, 402b that supply sample values that are mixed by the pixel selection logic 300 of the display head A206. In operation, the rendering pipeline (not explicitly shown) of the GPU 122 renders two images of the same scene with some change in display parameters or sampling parameters so that the sampling positions used for the two images are different from each other. To do. For example, a slightly different display area or display surface normal may be defined for the two GPUs 122 to create a small offset at the pixel boundary of the two images. Alternatively, if the sampling position in the pixel can be set (for example, by a graphics driver), each GPU 122 can generate each image using the same set of display parameters and a different sampling position in each pixel.

  [0069] One of the rendered images is stored in frame buffer “A” 404 and the other is stored in frame buffer “B” 406. Frame buffers A 404 and B 406 may be implemented in any one or more memory devices, including GPU 122 on-chip memory, graphics memory 124 and / or system memory 104 of FIG. The two frame buffers can be located in the same memory device or in different devices as desired.

[0070] The display pipeline B 402b reads the pixels from the frame buffer B 406, performs various processing operations (generally of conventional nature) on the pixels, and transfers the resulting pixels P _B to the display head _B 206b. The display head _B 206b has a pixel selection logic circuit 300 that operates to select the pixel P _B and these pixels are transferred to the MIOB port 214b via the crossbar 220 (not explicitly shown in FIG. 4). Is done. Pixel P _B is transferred via pixel path 400 to MIOA port 214a of the same GPU 122, which transfers pixel P _B to display head A 206a.

[0071] In parallel with this operation, the display pipeline A402a reads the pixel from the frame buffer A, pixel (generally may be of conventional nature) performs various processing operations, the pixel P _A obtained display Transfer to head A 206a. Display pipeline B 402b, display head B 206b, and pixel path 400 send pixel values P _A and P _B corresponding to the same screen pixel to pixel selection logic 300 of display head A 206a simultaneously (eg, in the same clock cycle). Thus, it is suitably set at an appropriate timing.

[0072] Within the pixel combining circuit 308, adding circuit 310 adds the pixel _{P A} and _{P B,} the multiplexer 312 selects the sum pixel, the division circuit 314 by dividing the total of 2, thus mixed on the path 316 pixel is the average of the pixel _{P a} and _{P B.} The multiplexer 318 selects the mixed pixel as the output pixel P _final . Display head A 206a sends output pixel P _final to an output port (eg, digital output port 210) for transmission to the display device.

  [0073] Since the rendering pipeline of the GPU 122 renders each frame twice, the maximum frame rate of the GPU 122 when operating in the internally distributed AA mode described herein is the maximum frame rate when operating in the non-AA mode. Note that it is generally lower than. In some embodiments, the frame rate of this internally distributed AA mode is approximately half that of the non-AA mode. For real-time animation, if the frame rate of the internal distributed AA mode is about 30 frames per second (or more), a decrease in the frame rate has little or no adverse effect on the smoothness of the animation. Also, the image quality generated in the non-AA mode is generally lower than the image quality generated in the internal dispersion AA mode. In this way, the internal dispersion AA has a reduced frame rate in exchange for higher image quality.

  [0074] The frame rate obtained using the internally distributed AA mode described herein can be achieved using conventional AA techniques (eg, filtering in the rendering pipeline and / or the display pipeline) on a single GPU. Note also that it is comparable to the resulting frame rate. Conventional AA using a single GPU generates a single image, but requires a GPU rendering pipeline that uses multiple samples per pixel. By processing more samples per pixel, the frame rate for the non-AA mode is also reduced in exchange for improved image quality. A two-image rendering method manages in the rendering pipeline and the throughput of the GPU using the internal distributed AA mode can be comparable to the throughput of the GPU using the conventional AA.

  [0075] Although higher order AA filters may be implemented, such filters may employ a combination of single pipeline and internal distributed anti-aliasing operations. In one embodiment, display pipeline A 402a and display pipeline B 402b each include a filter on scan (FOS) module (not explicitly shown) that implements an internal N × AA filter. More specifically, for each version of the rendered image, the GPU 122 renders a pipeline of N (e.g., 2, 4, or 1 per pixel) using, for example, conventional supersampling and / or multisampling techniques. Generate any other number of samples). Samples for one version of the image are stored in frame buffer A 404, and samples for the other version of the image are stored in frame buffer B 406.

[0076] Display pipeline A 402a receives all N samples for each pixel from frame buffer A. Within the display pipeline A 402a, a first filter-on-scan (FOS) module (not explicitly shown in FIG. 4) implements an N × AA filter, mixing N samples, one color per pixel. Generate a value. The color value determined by the FOS module is supplied to the display head _A 206a (possibly after further processing) as a pixel PA.

[0077] Similarly, the display pipeline 402b receives all N samples for each pixel from the frame buffer B406. Within the display pipeline 402b, a second FOS module (also not explicitly shown in FIG. 4) performs an N × AA filter and mixes N samples to determine one color value per pixel. To do. The color value determined by the second FOS module is supplied to the display head _B 206b (possibly after further processing) as a pixel P _B.

[0078] Thus, the pixel P _A and P _B respectively generated by the display pipes 402a and 402b, it is possible respectively to filtered pixels from N × oversampling image. As long as the sampling points used to fill frame buffer A 404 do not match those used to fill frame buffer B 406, combine the N × AA filters in each display pipe 402a, 402b with the internal variance AA filter technique described above. (2N) × AA filter is obtained. For example, if the FOS module in each display pipe 402a, 402b is a 4 × AA filter, the GPU 122 can provide 8 × AA.

  [0079] The present invention does not require a specific FOS module or AA filtering algorithm, and conventional modules and algorithms can be used. Therefore, detailed description is omitted. In some embodiments, the FOS modules in display pipelines A 402a and 402b are adapted to the same filter algorithm so that the final image obtained does not depend on the version of the image processed by a particular display pipeline. It is also possible to perform N × AA filtering early in the image generation process. For example, in an alternative embodiment, N × AA filtering may be performed within the rendering pipeline of GPU 122 using conventional techniques.

  [0080] In some embodiments, sampling points that fill different frame buffers are selected such that there are no matching sampling points. For example, FIG. 5A illustrates a “grid” sampling pattern applied to pixel 500. Pixels are sampled four times at positions 501-504 (shown as circles) within the pixel. FIG. 5B illustrates a “rotating grid” sampling pattern applied to pixel 500. The pixels are sampled four times at positions 511-514 (indicated by diamonds) that are different from the positions 501-504 within the pixels.

[0081] In one embodiment, pixel data in frame buffer A 404 is generated using the grid sampling pattern of FIG. 5A, and pixel data in frame buffer B 406 is generated using the rotated grid sampling pattern of FIG. 5B. FOS module display pipe A402a may filter the four sample values (501 to 504) as a single value _{P A,} FOS module displays pipe B402b filters the four sample values (511 to 514) a single value _{P B} Te. Pixel selection logic 300 in display head 206a is a mixture of values P _A and P _B as described above, to obtain a final image corresponding to an average of eight samples in total. This procedure results in the same anti-aliasing power as a single rendering process that samples each pixel using the 8-point pattern of FIG. 5C.

  [0082] It will be appreciated that the internally distributed AA technique described herein is exemplary and that changes and modifications are possible. For example, the GPU 122 described herein has exactly two display heads each capable of driving a maximum of one output port, so that both display heads can be used for internal distributed anti-aliasing. , GPU 122 can send a maximum of one pixel stream to the display device. However, embodiments of the present invention can be implemented with any GPU having at least two display heads and appropriate pixel selection logic and I / O ports. If the GPU has more than two display heads, the GPU can support internally distributed AA and can supply individual pixel streams to more than one display device. In addition, if the GPU has more than two display heads, all of the GPU display heads can be connected together in a master / slave daisy chain fashion to further increase the AA power of the GPU.

  [0083] Also, the GPU 122 described in this specification has two MIO ports, both of which are used for internal distributed AA. In this embodiment, neither head A 206a nor head B 206b can be used as a master or slave to any other GPU or display head. In other embodiments, the GPU can have an additional MIO port that allows one port to simultaneously receive and transmit pixels and combine with internal distributed AA to interconnect with other GPUs. Can have an operation mode. For example, if there is a third MIO port, that port should be set as an input port that sends external pixels from another GPU to display head B 206b or an output port that sends pixels generated by display head A 206a to another GPU. You can also. In such embodiments, other GPUs may or may not be configured to perform their own internal distributed AA filtering. [Pixel transfer path]

  [0084] An example of a pixel transfer path implementation according to an embodiment of the present invention will be described. As is apparent, the pixel transfer path may be external or internal to the GPU.

  [0085] FIG. 6 illustrates a graphics adapter 600 implemented as a printed circuit board card according to an embodiment of the invention and configured with an external pixel transfer path. Graphics adapter 600 is implemented as an expansion card using a printed circuit board (PCB) 602 that conforms to PCI-E or another interconnect standard. The GPU 122 is mounted on the PCB 602 and electrically coupled to the system connector 604 on the PCB 602 through wiring (not shown). System connector 604 is designed to be insertable into a PCI-E expansion slot (or any other type of expansion slot) to allow communication between GPU 122 and other portions of a computer system such as system 100 of FIG. To. The GPU 122 is also electrically coupled to the display output connector 606 via wiring (not shown) on the PCB 602. Display output connector 606 is preferably coupled to one of digital output ports 210, 211 or analog output ports 212, 213 (see FIG. 2) of GPU 122. In some embodiments, as is known in the art, the PCB 602 can provide multiple display output connectors 606, each coupled to a different one of the output ports 210-213.

  [0086] The PCB 602 also includes two graphics edge connectors 614a, 614b that can be designed identically. The graphics edge connector 614a is connected to the MIOA port 214a of the GPU 122 via a wiring 616, and the graphics edge connector 614b is connected to the MIOB port 214b of the GPU 122 via a wiring 618. Each graphics edge connector 614a, 614b is configured for electrical and mechanical connection with a removable interconnect device. In some embodiments, graphics edge connectors 614a, 614b have the same configuration and can be used interchangeably.

  [0087] The graphics adapter 600 of one embodiment is designed for use in a distributed rendering system in which two or more GPUs cooperate to perform different parts of a rendering task. Such a system can be operated, for example, in a split frame mode where each CPU renders a different portion of the image, an alternate frame mode where each CPU renders a different image in a series of images, or a distributed anti-aliasing mode. . In each of these modes, one GPU (master) receives pixels from another GPU (slave), and the pixel selection logic circuit 300 in the master GPU selects pixels for display as described above. The GPUs of different graphics adapters 600 are advantageously connected through their respective graphics edge connectors 614a, 614b using a suitable interconnect device.

  [0088] In an embodiment of the present invention, a removable interconnect device 620 is configured and configured to be connectable to graphics edge connectors 614a, 614b of the same graphics adapter 600, as shown in FIG. Yes. The interconnect device 620 can be, for example, a ribbon cable having a receptacle on one side for receiving graphics edge connectors 614a, 614b or a PCB with wiring printed along its length, such as two graphics edges. Connectors 614a and 614b are connected to each other.

  [0089] In this embodiment, the interconnect device 620 builds the pixel transfer path 400 (FIG. 4) utilizing the timing characteristics of the distributed rendering system supported by the graphics adapter 600. More specifically, in a distributed rendering configuration, a pixel transfer path from the MIOB port 214b of the GPU 122 to the MIOA port (or MIOB port) of the GPU on a different graphics adapter 600 is included along any segment of the transfer path. As well as any electronic components that can be (FIFO, latches, etc.), the length of the wiring 618 and / or 616 and the characteristic transfer time from the interconnect device between the two adapters. In a distributed rendering operation, the pixels from the slave GPU display head to the master GPU display head so that the pixels from the slave GPU and master GPU reach the master GPU display head almost simultaneously (eg, during the same clock cycle). The transfer is advantageously adjusted.

  [0090] The interconnect device 620 provides transmission time matching with distributed rendering interconnect devices that connect different GPUs, and the pixel transfer path provided by the interconnect device 620 sends the signal to the MIOA port 214a at the correct timing. . Thus, implementation of internal distributed AA using external interconnect devices does not require any internal modifications to GPU 122 or adapter card 600 originally designed for distributed rendering.

  [0091] It will be appreciated that the graphics adapters and interconnect devices described herein are illustrative and that changes and modifications are possible. The shape, layout, and material composition of the adapters and interconnect devices can be modified from those shown and described herein, and any communication protocol can be implemented for data transfer between MIO ports.

  [0092] In an alternative embodiment, the interconnect device 620 may be implemented as part of the PCB 602, for example using wiring connecting paths 618 to 616. In this embodiment, a control device (eg, a removable jumper or driver control switch) is advantageously used to enable or disable data transfer from path 618 to path 616 or in the reverse direction.

  [0093] Note also that in some embodiments, the presence of an interconnect device 620 or other external connection between two MIO ports of the same GPU does not automatically enable internal distributed AA. . As described above, the operation of the pixel selection logic circuit 300 determines whether or not to perform internal distribution AA, but the operation of the pixel selection logic circuit 300 is controlled via the graphics driver.

  [0094] In another alternative embodiment, the pixel transfer path used for internal distribution AA is built in the GPU. FIG. 7 is a block diagram of a GPU 700 according to one such embodiment of the invention. GPU 700 is substantially similar to GPU 122 of FIG. 4, and the same reference numerals are used to identify corresponding components. Unlike GPU 122, GPU 700 includes an internal pixel transfer path that connects output path 702 of display head B 206b to external pixel input path 704 of display head A 206a.

  [0095] In this embodiment, the pixel transfer path selects between pixels from display head B 206b and pixels received on path 708 from one of the MIO ports (eg, MIOA port 214a) via crossbar 220. A selection unit (eg, multiplexer) 706 is included. The selected pixel is provided to the external pixel input path 704 of the display head A 206a.

  [0096] The selection unit 706 operates in response to a control signal (not explicitly shown). The control signal is such that when the GPU 700 is operating in the internal distributed AA mode, the display head A 206a of the GPU 700 operates as a master for another GPU so that the selection unit 706 selects a pixel on the path 702. If so, the pixel on the path 708 is set to be selected. This control signal can be generated in response to a command issued from the graphics driver, enabling the user (or application developer) to enable the internal distributed AA through an appropriate software interface without having to access the graphics software. Enable to disable.

  [0097] In this embodiment, the path from the display head B 206b to the selection circuit 706 so that the pixel from the display head B 206b reaches the selection circuit 706 at the same timing as the pixel arrives from the external GPU in the distributed rendering mode. Note that 702 can include FIFOs, latches, and other timing control devices. In this case, the operation timing of the display head B 206b and the display head A 206a does not depend on the GPU in the distributed rendering mode or the internal distributed AA mode.

  [0098] Although the internal pixel transfer path requires modification to the GPU, it does not require the use of any of the GPU's I / O ports. Thus, for example, while GPU 700 continues to perform internal distributed AA filtering, GPU 700 display head A 206a can be slaved to another GPU display head, or GPU 700 display head B 206b can be another GPU display head. Can be mastered.

  [0099] It will be appreciated that the internal pixel transfer paths described herein are exemplary and can be changed and modified. For example, a “reverse” pixel transfer path (from display head A 206a to display head B 206b) may be provided in addition to the path indicated. [Other embodiments]

  [0100] As noted above, embodiments of the present invention use readout techniques and components that are widely associated with distributed rendering across multiple GPUs, not just one GPU, to generate AA filtered images. To provide distributed anti-aliasing technology for multi-GPU systems. Appropriately configured GPU end-users enable internal distributed AA, regardless of the AA (or lack thereof) given to the program itself for any graphics program via the appropriate graphics driver interface You can choose that. If the program provides AA, the internally distributed AA described herein can be used to increase (eg, double) AA resolution.

  [0101] Although the present invention has been described with reference to particular embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, although the present invention has been described with reference to AA filtering, the coupling between single GPU display heads or multiple GPU display heads described herein may be used in other ways.

  [0102] In an alternative embodiment, distributed filtering can be used to generate stereo anaglyphs. As is known in the art, stereo anaglyphs superimpose the left and right eye views of a scene to create a single image. Normally, different color filters are applied to the left eye pixel and the right eye pixel. For example, the right eye pixel can be filtered with a red pass filter, and the left eye pixel can be filtered with a blue / green pass filter. Due to the field of view or viewpoint offset between the left and right eye fields, the left and right eye pixels corresponding to the same point in the scene are at different positions in the anaglyph. Therefore, the naked eye can see an anaglyph double-distorted color image. In order to view the image accurately, the observer wears special glasses for the left lens that excludes the color used for the right eye pixel with a filter and the left lens that excludes the color used for the left eye pixel with a filter.

  [0103] Referring to FIG. 4A, the rendering pipeline (not shown) of GPU 122 (0) is used to generate the right eye view of the scene, and the rendering pipe of GPU 122 (1) is used to generate the left eye view of the scene. A line (not shown) can be used. Known techniques can be used to determine the rendering parameters for the right and left eye views.

[0104] The right eye pixel P _i1 and the left eye pixel P _i0 are advantageous in either the rendering pipeline of GPU 122 (0) and GPU 122 (1) or in the respective display pipelines 202 (0) and 202 (1). Color filter processing. In one embodiment, pixel colors are identified using different red, green and blue components. The right eye pixel can be filtered, for example, by reducing the red component to zero and leaving the green and blue components unchanged. Similarly, the left eye pixel can be filtered by reducing the green and blue components to zero and leaving the red component unchanged.

[0105] The right-eye pixel P _i1 is sent to the display head A 206a of the GPU 122 (1). The display head 206 (a) transfers the pixel P _i1 to the MIOA port 214a (1), which sends the pixel as P _{o1 to} the MIOA port 214a (0) of the GPU 122 (0). In this way, the display head 206a (0) receives the right eye pixel as an external pixel.

[0106] The left-eye pixel P _i0 is sent to the display head 206a (0) as an internal pixel. In general, the corresponding left eye pixel and right eye pixel reproduce different positions in the scene, but the corresponding left eye processed by the pixel selection logic 300 depending on the field of view or viewpoint offset used to generate the right eye field and the left eye field. Note that the pixel and the right eye pixel are the pixels at the same position in the anaglyph frame.

[0107] In one embodiment, the display head 206a (0) includes the pixel selection logic 300 of FIG. To generate an anaglyph, both divider circuits 306 and 314 are set to select a divisor of one. The addition circuit 308 adds the left eye pixel P _i0 and the right eye pixel P _i1 , and generates a total pixel on the path 310 having the red component of the left eye pixel and the blue and green components of the right eye pixel as a result of the initial color filtering. . The selection multiplexer 312 selects the total pixels from the path 310, and the selection multiplexer 316 selects the mixed pixels as output pixels on the path 315.

[0108] In other embodiments, the color filter in front of the pixel selection logic circuit 300 is not used. For example, the selection multiplexers 312 and / or 316 can be set such that the selection can be controlled independently for each color component. In one such embodiment, the selection multiplexer 312 passes all the color components of the left eye pixel P _i0 from the path 302, and the selection multiplexer 316 passes the red component of the left eye pixel P _i0 and the blue and green components of the right eye pixel P _i1. pass. The result is an output pixel having a red component of the left eye pixel and a blue and green component of the right eye pixel on path 318.

  [0109] One skilled in the art can appreciate that more than two GPUs can be used for anaglyph rendering. In an embodiment of four GPUs (eg, FIG. 4B), two GPUs can be used for right eye field generation and two GPUs can be used for left eye field generation. The two GPUs that generate each field of view can employ distributed anti-aliasing techniques as described above to enhance the image quality of anaglyphs.

[0110] Stereo anaglyphs can also be rendered using internal distributed filtering. Referring to FIG. 4B, the rendering pipeline (not shown) of GPU 122 (0) can generate both views, the left eye view into frame buffer A and the right eye view into frame buffer B (or vice versa). Remember. Display pipeline _B 402b and display head _B 206b send right eye field of view as pixel P _B to display head A 206a, and display pipeline _A 402a sends left eye field of view as pixel PA to display head _A 206a. In display head A 206a, pixel combiner 308 (FIG. 3) mixes the pixels appropriately to produce an anaglyph.

[0111] Distributed filtering can also be used to generate transition effects such as fade-in, fade-out, or dissolve. For example, in the case of internal dispersion, the frame buffer B can store an image that fades out, and the frame buffer A stores an image that fades in. For each frame, the pixel synthesizer 308 adjusts the relative weights of the pixels from frame buffer A and frame buffer B, so that the image from frame A gradually increases to maximum intensity and the image from frame buffer B is zero. It weakens to strength. (If the image in the frame buffer B is a solid color area, the effect is fade-in, and if the image in the frame buffer A is a solid color area, the effect is fade-out.) depends on the number of different weighted average of the synthesizer 308 is capable of forming pixel P _a and the pixel P _B, which is a matter of design choice. Multiple GPUs with external distributed filtering can be used to achieve the same effect.

  [0112] In another embodiment, such transition effects can be achieved by using distributed filtering in combination with a look-up table for each display head. As is known in the art, display heads often include a look-up table that converts the internal pixel representation to a color intensity suitable for the display device, sometimes loading and reloading different values into the look-up table. It is possible to Fade out (or fade in) can be achieved by lowering (or increasing) the color intensity of values in the lookup table from one frame to the next. Thus, to dissolve from the image in frame buffer B to the image in frame buffer A, a conventional fade-out look-up table can be applied to display head B, and the conventional fade-in look-up table is displayed. Applies to head A. The pixel synthesizer 308 synthesizes two images with a constant (eg, equal) weight to create a dissolve effect.

  [0113] In other embodiments, pixel transfers between display heads of the same GPU are used to implement display characteristics that are independent of mixing. For example, pixel transfer between display heads can be used to control LCD overdrive (also referred to in the art as “LCD feedforward” or “response time correction” (RTC)) functions. As is known in the art, LCD screens are based on a frame-by-frame basis where the signal driving the pixel is based in part on the desired new intensity or in part on the difference between the desired new intensity and the previous intensity. It is possible to respond faster when adjusted.

  [0114] To implement the LCD overdrive function, the frame buffer B can store the pixels of the previous image, whereas the frame buffer A can be used to store the pixels of the new image. Display head B sends the previous pixel value to display head A, and pixel synthesizer 308 of display head A is based on the new value and the previous value using, for example, a description for calculating a conventional LCD overdrive signal. Can be set to calculate the overdrive value.

  [0115] Pixel transfer between display heads of a GPU can also be used to generate a composite image. For example, the frame buffer B can include pixels for an overlay image that is overlaid on a portion of the image stored in the frame buffer A. The display head B sends an overlay pixel to the display head A, and the pixel selection logic circuit 300 of the display head A selects an internal pixel outside the overlay region where the external pixel is selected.

  [0116] Thus, while the invention has been described with reference to specific embodiments, the invention is intended to cover all modifications and equivalents within the scope of the claims. It will be understood.

1 is a block diagram of a computer system according to an embodiment of the present invention. FIG. 3 is a block diagram of a pixel output path within a graphics processing unit (GPU) that can be used with embodiments of the present invention. FIG. 3 is a block diagram of a pixel selection logic circuit in a GPU display head that can be used in embodiments of the present invention. FIG. 3 is a block diagram of a pixel selection logic circuit in a GPU display head that can be used in embodiments of the present invention. 1 is a block diagram of a graphics subsystem having two GPUs according to an embodiment of the invention. FIG. FIG. 3 is a block diagram of a GPU showing two display heads combined in a master / slave format according to an embodiment of the present invention. FIG. 3 illustrates a sampling pattern that can be used in some embodiments of the present invention. FIG. 3 illustrates a sampling pattern that can be used in some embodiments of the present invention. FIG. 3 illustrates a sampling pattern that can be used in some embodiments of the present invention. 1 is a graphics adapter implemented as a printed circuit board card according to an embodiment of the present invention and configured using an external pixel transfer path. 2 is a block diagram of a GPU having an internal pixel transfer path according to an embodiment of the present invention; FIG.

DESCRIPTION OF SYMBOLS 100 ... Computer system, 102 ... Central processing unit (CPU), 104 ... System memory, 105 ... Memory bridge, 106, 113 ... Bus, 107 ... I / O (input / output) bridge, 112 ... Graphics subsystem, DESCRIPTION OF SYMBOLS 110 ... Display apparatus, 114 ... System disk, 122 ... Graphics processing unit (GPU), 124 ... Graphics memory, 202, 402 ... Display pipeline, 206a, 206b ... Display head, 210, 211 ... Digital output port, 212 213 ... Analog output port, 214a, 214b ... Multi-purpose input / output (MIO) port, 220 ... Crossbar, 300, 350 ... Pixel selection logic, 302, 352 ... First pass, 304, 354 ... Second Path, 306, 358 Pixel synthesis circuit, 308... First division circuit, 310... Addition circuit, 312... Selection circuit, 314, 366... Second division circuit, 316, 360. 362 ... selection multiplexer, 400 ... pixel transfer path, 404 ... frame buffer A, 406 ... frame buffer B.

Claims (18)

A display head for a graphics processor,
A first input path configured to propagate a gamma corrected first pixel generated by a first graphics processor;
A second input path configured to propagate a gamma corrected second pixel generated by the second graphics processor;
Coupled to the first input path and the second input path and configured to mix the gamma corrected first pixel and the gamma corrected second pixel to generate a mixed pixel. A pixel synthesizer,
And a selection circuit configured to select one of the gamma corrected first pixel, the gamma corrected second pixel, or the mixed pixel as an output pixel.   The graphics processor of claim 1, wherein the display head further comprises a divider circuit configured to divide the mixed pixel by a divisor.   The graphics processor of claim 2, wherein the divisor is selected from candidate divisors including 1 and 2 as divisors.   The graphics processor of claim 1, wherein the divisor is selected from candidate divisors including 1, 2, and 4 as divisors.   The graphics of claim 1, wherein the pixel synthesizer is configured to generate the mixed pixel by adding the gamma corrected first pixel and the gamma corrected second pixel. Processor. The first pixel and the second pixel are gamma correction pixels;
The graphics processor of claim 1, wherein the pixel synthesizer is configured to generate the blended pixel by calculating a gamma correction blend of the first pixel and the second pixel. The gamma correction approximation of mixing, the gamma-corrected first pixel _{P i,} the gamma-corrected second pixel when _{P e,} and the following formula _{(4P i + 4P e + |} P i -P _e |) / 4
The graphics processor of claim 6, calculated by:   The pixel synthesizer may divide the gamma corrected first pixel using a divisor prior to mixing the gamma corrected first pixel and the gamma corrected second pixel. The graphics processor of claim 1, comprising a configured divider circuit. A display pipeline configured to generate a gamma corrected first pixel;
An input port configured to receive a gamma corrected second pixel from a source of external pixels;
With a display head,
The display head is
A first input path coupled to the display pipeline and configured to receive the first gamma corrected pixel from the display pipeline;
A second input path coupled to the input port and configured to receive the second gamma corrected pixel from the input port;
Coupled to the first input path and the second input path and configured to mix the gamma corrected first pixel and the gamma corrected second pixel to generate a mixed pixel. A pixel synthesizer,
A graphics processor comprising: a selection circuit configured to select one of the gamma corrected first pixel, the gamma corrected second pixel, or the mixed pixel as an output pixel.   The graphics processor of claim 9, wherein the display pipeline includes a filter unit adapted to an anti-aliasing filter for a plurality of sample values associated with the gamma corrected first pixel. Multiple output ports,
An external circuit coupled between the display head and a plurality of output ports;
The graphics processor of claim 9, wherein the external circuit is configured to selectively transfer an output pixel to one of the output ports.   The graphics processor of claim 11, wherein the plurality of output ports includes a first output port configured to be connected to an input port of another graphics processor. A method for generating an image, comprising:
Rendering a first set of gamma corrected input pixels for an image using a first graphics processor;
Rendering a second set of gamma corrected input pixels for an image using a second graphics processor, each rendering of the first graphics processor and the second graphics processor The operation differs in at least one point and
Sending the first set of gamma corrected input pixels and the second set of gamma corrected input pixels to a first display head;
Mixing corresponding pixels of the first set of gamma corrected input pixels and the second set of gamma corrected input pixels with the first display head to generate a first set of output pixels. And a method comprising:   The method of claim 13, wherein the first display head is provided in the first graphics processor.   The method of claim 13, wherein a rendering operation of each of the first graphics processor and the second graphics processor is different with respect to a sampling pattern applied to each pixel.   The method of claim 13, wherein the rendering operation of each of the first graphics processor and the second graphics processor is different with respect to a field of view offset of the rendered image.   The rendering operation of each of the first graphics processor and the second graphics processor is such that the rendering operation by the first graphics processor generates a left eye field of stereo anaglyph, and the second graphics processor 14. The method of claim 13, wherein the rendering operation according to is different in that it produces a right eye field of stereo anaglyphs. The method of claim 13, further comprising sending the first set of output pixels to a display device.

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