JPH07319588A - Runaway prevention control system - Google Patents

Abstract

PURPOSE:To prevent the runaway of a microprocessor from happening with comparatively simplified constitution in a runaway prevention control system which prevents the runaway of the microprocessor from occurring. CONSTITUTION:A modem 2 is equipped with the microprocessor 3, a modulation/ demodulation part 4, a power-on reset circuit 6 and a reset signal generation circuit 7, etc., and a reset signal can be generated by detecting the trailing edge of a ready signal ER representing the feasibility of the operation of terminal equipment 1 in data transfer between the terminal equipment 1 and the modem 2 by the reset signal generation circuit 7. The power-on reset circuit 6 makes the microprocessor 3 perform a reset operation by adding the reset signal on the reset terminal RST of the microprocessor 3 by the detection of start of a power supply voltage when a power source is applied and the reset signal from the reset signal generation circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway prevention control system for preventing runaway of a microprocessor. Various devices generally have a configuration in which a microprocessor is provided for control. Such a microprocessor controls each part according to a program stored in a read-only memory (ROM) or the like, but if a predetermined program cannot be executed due to a bug in the program, noise from the outside, or the like. May be. When the microprocessor goes into a runaway state, normal control becomes impossible and it is necessary to perform a reset to return to the initial state. It is desired to prevent such a microprocessor runaway.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example, 31 is a microprocessor (MPU), 32 is a read only memory (ROM) storing programs and the like, 33 is a random access memory (RAM), and 34 is a watch. Dock timers (WTM) and 35 are OR circuits (OR), and show a case where a watch dock timer 34 is provided to prevent runaway of the microprocessor 31.

The microprocessor 31 controls each part of the device (not shown) in accordance with a program stored in the read-only memory 32, and has a reset input terminal RSTin from which an external reset signal RESET or a power-on reset circuit (see FIG. When a reset signal from (not shown) or a reset signal from the watchdog timer 34 is applied via the OR circuit 35, the microprocessor 31 masks other interrupts and performs the reset operation.

The watchdog timer 34 counts a clock signal from a clock generator (not shown), and resets the reset output terminal RSTo due to overflow.
ut to the reset input terminal R of the microprocessor 31
Although a reset signal is added to STin via the OR circuit 35, the watchdog timer 3 is provided at every predetermined step of the program executed by the microprocessor 31.
Reset signal for resetting 4 is reset output terminal WR
The reset input terminal WRTin of the watchdog timer 34 is input from Tout to reset the watchdog timer 34 and control so that overflow does not occur.

Therefore, when the microprocessor 31 is operating normally, the watchdog timer 34 is reset by the microprocessor 31 so as not to overflow. And the microprocessor 31
If, due to some reason, the watchdog timer 34 cannot be reset, the microprocessor 31 is reset by a reset signal due to the overflow of the watchdog timer 34 to prevent the runaway.

[0006]

In the conventional example in which the watchdog timer 34 is used to prevent runaway of the microprocessor 31, a step for resetting the watchdog timer 34 within a predetermined time is inserted in the program. However, there is a problem that the burden on the program creation is large. Further, when a runaway occurs, it is reset so that the runaway state does not continue, and it is impossible to prevent the runaway in advance. An object of the present invention is to prevent a runaway by resetting a microprocessor by using a ready signal indicating that data can be transferred when transferring data between devices.

[0007]

A runaway prevention control system according to the present invention will be described with reference to FIG. 1. A device such as a modem 2 for transferring data with a terminal device 1 such as a personal computer (personal computer). In the runaway prevention control method for preventing runaway of the microprocessor, the reset signal generation for detecting the falling of the ready signal indicating the operation of the terminal device 1 from ON to OFF and generating the reset signal of the microprocessor 3 is generated. The circuit 7 is provided and the reset signal generation circuit 7
Thus, the microprocessor 3 is reset each time the ready signal falls from ON to OFF.

Further, the reset signal generating circuit 7 is provided in the terminal device 1.
The counter is provided with a counter for starting the counting of the clock signal when the ready signal falls from the above, and a pulse generation circuit for generating the reset signal of the microprocessor 3 based on the overflow signal of this counter.

[0009]

Data transfer between the terminal device 1 and the device such as the modem 2 including the microprocessor 3 or between the terminal device 1 and the device such as the printer including the microprocessor 3 takes a relatively long time. It has been stopped. Further, before transferring data, a ready signal indicating that the operation is possible is transferred from the terminal device 1 to a device including a microprocessor of a device such as a modem or a printer. Since the completion of data transfer can be confirmed by the fall of the ready signal from ON to OFF, the fall of the ready signal is detected by the reset signal generation circuit 7 and the microprocessor 3 is detected.
To reset. That is, the microprocessor 3 is forcibly reset each time the data transfer end is confirmed to prevent runaway.

Further, the reset signal generation circuit 7 has a problem of malfunction due to noise if a reset signal is immediately applied to the microprocessor 3 at the fall of the ready signal from ON to OFF. After the time from the falling edge until the clock signal is counted and overflowed, the reset signal for the microprocessor 3 is generated by the pulse generation circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of an embodiment of the present invention, in which 1 is a terminal device such as a personal computer (personal computer), 2
Is a modem, 3 is a microprocessor (MPU), 4 is a modulator / demodulator, 5 is a line such as a public telephone line, 6 is a power-on reset circuit, 6A is a power supply terminal, 6B is an external reset terminal, 7 is a reset signal generation circuit, 8 is a read only memory (ROM), 9 is a random access memory (RA)
M), 10 is an interface unit, 11 is a 4-wire / 2-wire conversion unit, 12 is a line transformer, and 13 is a line interface unit.

This embodiment shows a case in which data is transferred between a terminal device 1 and a modem 2 as a device including a microprocessor 3, the modem 2 via a line 5 and a switching network (not shown). Connected to the modem of the other party, the transmission data is modulated by the modulation / demodulation unit 4 and transmitted to the line 5, and the signal received via the line 5 is demodulated by the modulation / demodulation unit 4 to become reception data. The microprocessor 3 controls each part in the modem 2, and the program for that is stored in the read-only memory 8.

The power-on reset circuit 6 is connected to the reset terminal RST of the microprocessor 3, the power supply voltage + V in the modem 2 is applied to its power supply terminal 6A, and the reset signal generation circuit 7 is connected to the external reset terminal 6B. It is connected. When the power supply voltage + V in the modem 2 exceeds a predetermined value due to power-on, a reset signal is applied to the reset terminal RST of the microprocessor 3 to cause power-on reset. Also, when a reset signal is applied to the external reset terminal 6B from an external reset switch (not shown), the reset terminal R of the microprocessor 3
A reset signal is added to ST to perform the same reset operation as in the case of power-on reset.

Therefore, by applying a reset signal from the reset signal generation circuit 7 to the external reset terminal 6B of the power-on reset circuit 6, the microprocessor 3 can be reset. The reset signal generation circuit 7 detects that the ready signal ER indicating that the terminal device 1 is in the operable state is changed from the on state to the off state indicating the operation stopped state, that is, the ready signal. A reset signal is generated by detecting the fall of the ER from on to off.

Between the terminal device 1 and the modem 2, for example, the transmission data S is sent from the terminal device 1 to the modem 2.
D, a transmission request signal RS, a terminal device ready signal ER, etc. are transferred, and received data RD, a transmission enable signal CS, a data set ready signal D from the modem 2 to the terminal device 1.
R, carrier detection signal CD, transmission data timing signal ST2, reception data timing signal RT, ring detection signal CI, etc. are transferred.

In this embodiment, when the terminal device 1 transmits / receives data to / from a partner terminal device via the modem 2 and the line 5, the terminal device ready signal is sent to the modem 2. The ER is turned on, and the terminal device ready signal ER is turned off upon completion of data transmission / reception. The modem 2 responds to this terminal device ready signal ER by the terminal device 1
On the other hand, when the data set ready signal DR is turned on and then the terminal device 1 turns on the transmission request signal RS, the modem 2 turns on the transmission enable signal CS to the terminal device 1. As a result, the terminal device 1 sends the transmission data SD, and the transmission data SD is modulated by the modulation / demodulation unit 4 and sent to the line 5 via the 4-line / 2-line conversion unit 11, the line transformer 12, and the line interface unit 13. To be done.

When the terminal device ready signal ER from the terminal device 1 is turned from on to off after the transmission / reception of such data is completed, the reset signal generating circuit 7 detects the fall from on to off, A reset signal is applied to the external reset terminal 6B of the power-on reset circuit 6. As a result, a reset signal is applied from the power-on reset circuit 6 to the reset terminal RST of the microprocessor 3, and the microprocessor 3 is reset. That is, the microprocessor 3 is reset each time the terminal ready signal ER falls from ON to OFF due to the end of the data transmission / reception.

FIG. 2 is an explanatory view of a main part of a reset signal generation circuit according to an embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts, 21 is a counter, 22 is a pulse generation circuit, and 23 is a gate circuit ( G) and 24 are clock generators. The counter 21 uses the terminal device ready signal ER from the terminal device 1.
Starts counting of the clock signal applied from the clock generator 24 through the gate circuit 23 due to the fall from ON to OFF, and an overflow signal when the count signal exceeds a predetermined count content is generated by the pulse generation circuit 22 and the gate circuit. 23 and. Also, the count contents are cleared by the rise of the terminal device ready signal ER from OFF to ON.

The pulse generation circuit 22 generates a reset signal to be applied to the external reset terminal 6B of the power-on reset circuit 6 by the overflow signal. In addition, the gate circuit 23 causes the clock generator 24 to receive the overflow signal.
From the clock signal applied to the counter 21.

3A and 3B are diagrams for explaining the operation of the reset signal generating circuit according to the embodiment of the present invention. FIG. 3A is a terminal device ready signal ER, FIG. 3B is a count content of the counter 21, and FIG. 3C is an overflow signal. (D) shows a reset signal from the pulse generation circuit 22.

The terminal device ready signal ER is shown in FIG.
As shown in, at time t _1, it rises from off (OFF) to on (ON), at time t ₂ it falls from on (ON) to off (OFF), and at time t _4, it changes from off. The case where the counter 2 rises to ON and falls from ON to OFF at time t ₅ is shown. At time t ₁ , the terminal device ready signal ER rises from OFF to ON, so that the counter 2
The count content of 1 is cleared as shown in (b).
Next, at time t _2, when the terminal device ready signal ER falls from on (ON) to off (OFF), the counter 21
Starts counting the clock signals from the clock generator 24. Therefore, the count content of the counter 21 is
It gradually rises as shown in (b).

When the counter 21 overflows (OVF) at time t ₃ , an overflow signal is output and added to the pulse generating circuit 22 and the gate circuit 23, as shown in (c). The pulse generation circuit 22 shows the pulse shown in (d) at the rising edge of the overflow signal (the polarity of this pulse shows a positive polarity, but it can be a negative polarity corresponding to the polarity of the external reset signal).
Is generated and added to the external reset terminal 6B of the power-on reset circuit 6 as a reset signal. That is, when the terminal device ready signal ER falls from on to off and the off state continues from time t ₂ to t ₃ , a reset signal is generated, and the influence of noise can be eliminated. .

As described above, the counter 21 clears the content of the count (at times t ₁ and t ₄ ) when the terminal device ready signal ER rises from OFF to ON, and when it falls from OFF to ON. The clock signal starts counting (at times t ₂ and t ₅ ), and an overflow signal is output after a predetermined time (at times t ₃ and t ₆ ). Such a control configuration can be easily realized by a relatively simple logic circuit, and the microprocessor 3
Since it has a function of detecting the terminal device ready signal ER from the terminal device 1, it is possible to control the counting operation of the counter 21 by the control of the microprocessor 3.

The pulse generation circuit 22 is for generating a pulse based on the overflow signal, and can be constituted by a flip-flop or the like. It is also possible to directly apply a reset signal from the pulse generation circuit 22 to the reset terminal RST of the microprocessor 3. The clock generator 24 can also be used as the clock generator in the microprocessor 3 or the modem 2.

In the case where a printer or the like is connected to the terminal device 1 and data is transferred from the terminal device 1 to the printer for printing, the microprocessor of the printer also prints the print data from the terminal device 1 to the printer. It is also possible to use a signal for transfer and to detect the signal when the signal turned on during the transfer of the print data falls off and reset the microprocessor.

[0026]

As described above, according to the present invention, the microprocessor 3 is reset by detecting the fall of the ready signal indicating the operation of the terminal device 1 from ON to OFF, such as data transfer. Since the resetting is performed after the series of processes described above is completed, there is an advantage that the control process of the microprocessor 3 is not affected and the runaway can be prevented.

The reset signal generating circuit 7 is replaced by the counter 2
1 and the pulse generation circuit 22, the microprocessor 3 is reset only when the fall of the ready signal from ON to OFF continues for a predetermined time, and malfunctions due to noise and the like are prevented, and There is an advantage that the runaway of the microprocessor 3 can be prevented.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a main part of a reset signal generation circuit according to the embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Terminal device 2 Modem 3 Microprocessor (MPU) 4 Modulator / demodulator 5 Line 6 Power-on reset circuit 6A Power supply terminal 6B External reset terminal 7 Reset signal generation circuit

Claims (2)

[Claims] 1. A runaway prevention control method for preventing runaway of a microprocessor of a device that transfers data to and from a terminal device, wherein a ready signal indicating that the terminal device is operable falls from on to off. And a reset signal generation circuit for generating a reset signal for the microprocessor, and resetting the microprocessor each time the ready signal falls from ON to OFF. 2. The reset signal generation circuit generates a reset signal for the microprocessor based on a counter that starts counting clock signals at the fall of a ready signal from the terminal device and an overflow signal of the counter. The runaway prevention control system according to claim 1, further comprising a pulse generation circuit.