JPH07312365A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To uniformly accumulate an insulation film on a lower electrode of a material which is remarkably uneven on a surface without reducing specific inductive capacity by a method wherein other elements have beforehand been added in a metal film and are diffused up to an insulation film surface in an insulation film accumulation. CONSTITUTION:There exist a recess and a projection of about 20nm at max due to a crystal grain boundary on a W film surface. In the prior art (b), it is understood that a film thickness is thinned to about half in a corner part on the bottom of the recess and the projection on a surface of a W crystal grain 3. As a Ta2O5 film 2 is increased promptly leak current when the film thickness is thinned, a large leak current flows out from a portion where the film thickness is thin locally. However, in this embodiment (a), a curvature of the surface of Ta2O5 film 2 can be made the same as or higher than that of the corner part on the bottom of the recess and the projection of a W crystal grain 1 (to which Si is added), and the leak current can be reduced more than the prior art. By controlling the annexing amount of Si, absorption probability of the Ta2O5 film 2 can be reduced without decreasing specific inductive capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to depositing an insulating film evenly on a lower electrode made of a material having a large surface irregularity without lowering the relative dielectric constant and reducing the relative dielectric constant. The present invention relates to a method for manufacturing a semiconductor device having an insulating film exhibiting leakage current characteristics.

[0002]

2. Description of the Related Art A typical process for manufacturing a conventional semiconductor device capacitive element will be described with reference to the schematic sectional view of FIG. That is, first, the SiO ₂ film 5 is formed on the Si substrate 4 except for a partial region. Next, TiN is used as a barrier metal on the entire surface.
After forming the film 6, only the portion on the SiO ₂ film 5 is removed. In the figure, (a) shows a state in which the W film 7 is formed as the lower electrode of the capacitive element on the sample by a sputtering method and is processed on the SiO ₂ film 5. After that, a state in which the Ta ₂ O ₅ film 2 is formed as a capacitive insulating film on the lower electrode W film 7 is shown in (b). Finally, a TiN film 8 is formed as an upper electrode on the Ta ₂ O ₅ film 2 to complete the capacitive element.
((c)).

[0003]

In recent years, with the miniaturization of capacitive elements, the use of a Ta ₂ O ₅ film having a relative dielectric constant about 6 times that of SiO ₂ has been studied as an insulating film. Ta ₂ O ₅
When forming a film, a chemical vapor deposition (CVD) method using an organic compound of Ta 2 as a raw material is generally used as a deposition method on a three-dimensionally processed lower electrode. Although as the lower electrode material is generally used Si, SiO ₂ layer of low dielectric constant is formed on the Ta ₂ O ₅ / Si interface by heat treatment after deposition during or deposition of Ta ₂ O ₅ Therefore, there is a problem that the relative dielectric constant of the entire insulating film is lowered. For this reason,
A metal that is not easily oxidized as the lower electrode material, such as W,
However, the W surface has irregularities of up to about 20 nm due to the grain boundaries. Furthermore, since the adsorption probability of the Ta organic compound is high, the step coverage is poor, and the Ta ₂ O ₅ film thickness is locally thinned at the bottom corners of the surface irregularities, increasing the leakage current. I knew it was. For example, in a DRAM capacitive element, if the leak current of the insulating film is large, the refresh time must be shortened, and the power consumption becomes large. Therefore, it is necessary to reduce the leak current by making the insulating film thickness uniform even on the surface irregularity bottom corner portion.

An object of the present invention is to solve the problems of the prior art described above, and to uniformly deposit an insulating film on a lower electrode of a material having large surface irregularities without lowering the relative dielectric constant. Another object of the present invention is to provide a method for manufacturing a semiconductor device having an insulating film exhibiting low leakage current characteristics.

[0005]

[Means for Solving the Problems] The above object is to add other elements to the metal film in advance in the manufacturing process of a semiconductor device in which an insulating film is deposited / formed on the metal film by a chemical vapor deposition (CVD) method. In addition, by diffusing the other element to the surface of the insulating film during the deposition of the insulating film, the probability of adsorption of the CVD raw material is reduced, and the coverage of the insulating film is improved. Can be achieved by That is, a small amount of an element capable of reducing the adsorption probability of the insulating film deposition raw material, such as Si, is added to the lower electrode and diffused to the film surface during the insulating film deposition to improve the coverage of the insulating film. The leak current is to be reduced.

If the adsorption probability of the CVD raw material can be reduced, the coverage of the step portion can be improved by, for example, the Journal of Vacuum.
Known by simulation, as described in Science Technology B pp.618-624. Also, the substrate is Si
, It is known that Si diffuses to the film surface during the deposition of CVD-Ta ₂ O ₅ film (for example, written in Autumn Proceedings of the Applied Physics Society of Japan, No. 2, 18a-ZQ-1, p. 694). ). Also,
As a method of reducing the leak current by including Si in the Ta ₂ O ₅ film, Japanese Patent Publication No. 5-53069 and Japanese Patent Laid-Open No. 4-6
By preventing crystallization of Ta ₂ O ₅ film as described in Japanese Patent No. 833, and Japanese Patent Laid-Open No. 64-50428, Journal of Electr.
It is known that defects in the Ta ₂ O ₅ film are repaired by Si as described in Ochemical Society, pp.320-328, but the adsorption probability of the CVD raw material on the film surface as in the present invention is known. It is not intended to improve the coverage by reducing.

[0007]

The present inventors obtained experimental results that the deposition rate of the CVD-Ta ₂ O ₅ film decreases when the content of Si with respect to W of the lower electrode is increased. I came to have an idea. However, like silicide
In the electrode containing excessive Si, a low dielectric constant SiO ₂ layer is formed at the interface of Ta ₂ O ₅ , and the relative dielectric constant of the entire insulating film is reduced. According to the present invention, by controlling the addition amount, it is possible to reduce the adsorption probability without lowering the relative dielectric constant, and it is possible to solve the problem of an increase in leak current due to the covering property. According to the present invention, it is possible to uniformly form an insulating film on a metal material having large surface irregularities by the CVD method.

[0008]

EXAMPLES The method of the present invention will be specifically described below with reference to examples. A typical procedure for manufacturing a capacitive element by the method of the present invention will be described with reference to the schematic sectional view of FIG. First, the SiO ₂ film 5 is formed on the Si substrate 4, leaving a partial region. Next, as a barrier metal, a TiN film 6 is formed to a thickness of 50 nm by the RF sputtering method. Sputtering conditions are purity
Using 99.99% Ti target, N ₂ / Ar = 40% (total pressure 5
In a mTorr) atmosphere, the RF output was set to 2.5 kW, and the barrier metal was formed by processing on the SiO ₂ film 5. Next, as the lower electrode,
A CVD method of reducing WF ₆ with SiH ₄ was used to form a W film 9 with a film thickness of 100 nm containing 2% of Si. Here, the CVD conditions for the trace amount of Si added W were a substrate temperature of 280 ° C. and a SiH ₄ / WF ₆ flow rate ratio of 50%. The Si concentration in the W film can be changed by changing the SiH ₄ / WF ₆ flow rate ratio and the substrate temperature. After that, the state in which the lower electrode is formed by processing on the SiO ₂ film 5 is shown in FIG.

FIG. 3B is a view showing a state in which the Ta ₂ O ₅ film 2 is formed as a capacitive insulating film on the lower electrode W film 9. This Ta ₂ O ₅ film 2 is pentaethoxyl tantalum (heating the raw material container to 125 ° C., carrier gas is N ₂ : 50 sccm) and oxygen (600 sccm) as the raw material gas, and the film forming chamber pressure is 0.2 Torr,
A film thickness of 10 nm was formed by a CVD method with a substrate temperature of 400 ° C. During the deposition of this Ta ₂ O ₅ film, Si diffuses from the lower electrode to the film surface, reducing the probability of raw material adsorption. In addition, Ta ₂ O
_{5 When the} film deposition temperature was 300 ° C or lower, the diffusion was not sufficiently performed and the effect could not be confirmed. A capacitor is completed by forming a TiN film 8 by RF sputtering as an upper electrode ((c)). The sputtering conditions were the same as those for forming the barrier metal.

A maximum of 20 nm due to grain boundaries on the W film surface
There are some irregularities. Ta on the W film in this embodiment
A cross-sectional view of the ₂ O ₅ film-covered shape and a comparison with the case of the conventional technique are shown in FIGS. According to conventional technology
In (b), it was found that the film thickness was reduced to about half at the bottom corners of the W surface irregularities. The leak current of Ta ₂ O ₅ rapidly increases as the film thickness becomes thin, and thus a large leak current locally flows from the thin film portion. However, in the case of this example (a), the curvature of the Ta ₂ O ₅ film surface is set to W
The curvature of the bottom corner portion of the unevenness can be made equal to or larger than that, and the leak current can be reduced as compared with the case of the conventional technique. The current-voltage characteristics of the capacitive element according to this structure are shown in FIG. 4 in comparison with those according to the present invention and those according to the prior art. Here, in order to enhance the effect of reducing the leak current by improving the coating property, each sample was subjected to heat treatment at 280 ° C. for 30 minutes while irradiating a mercury lamp in an atmosphere containing ozone before forming the upper electrode. It is known that the above treatment reduces defects in the Ta ₂ O ₅ film (for example, described in JP-A-2-283022).
by. From the results shown in the figure, in the case of the sample according to the conventional technique, the leakage current density at a voltage of 0.75 V is 10 to ⁷ A / cm ² , whereas in the case of the sample according to the present example, it is 10 to ⁸ A. / cm ~ ⁸ A /
It can be seen that it has been reduced to cm ² or less.

Further, Ta ₂ O ₅ after completion of the capacitive element of this embodiment
Figure 5 shows the Si distribution in the depth direction in the film. From the results in the figure, it can be seen that the diffusion is about 10 times larger than the Si concentration inside the Ta ₂ O ₅ insulating film. However, no decrease in relative permittivity was confirmed by adding Si to the lower electrode. Also, at the interface between Ta ₂ O ₅ and the lower electrode W,
No growth of SiO ₂ was observed.

As a means for adding Si to the W film of the lower electrode, it has been confirmed that similar effects can be obtained by using SiH ₂ F _{2 in} addition to SiH ₄ when the W film is formed by the CVD method. Was done. In addition to or SiH ₄ instead of SiH _4, it may be used _{Si 2 H 6, Si 3 H} 8. Further, instead of WF ₆ , WCl ₆ , W (CO) ₆ , (C ₅ H ₅ ) ₂ WH ₂ (biscyclopentadienyltungsten), W ₂ [N (CH ₃ ) ₂ ] ₆ (hexakisdimethyl) It is also possible to use an organic metal containing W such as amidoditungsten). When forming a W film by the sputtering method, a desired amount of Si should be previously prepared in the W target.
The effect was also confirmed by the method of adding the target and the method of using two targets of W and Si to perform sputtering simultaneously or alternately. In addition, the sputtering method or CVD
Of Si by the impurity implantation in the W film formed by the
Effects have also been confirmed by the method of adding a desired amount of Si, or the method of forming Si to a required thickness on the W film surface by the CVD method or the sputtering method and then diffusing Si into the film by heat treatment. On the contrary, the effect was also confirmed by forming a Si film in advance, then forming W by a sputtering method or a CVD method and then adding Si by a heat treatment at 400 ° C or higher. In this case, it was confirmed that the effect can be obtained even if the above heat treatment is omitted if the substrate temperature at the time of depositing the insulating film is 400 ° C. or higher. However, in this method, when the film thickness of W 2 is 100 nm or more, the diffusion of Si into the insulating film is not sufficient, so the W film thickness is preferably 50 nm or more.

It is also known that Si is replaced by W when Si is formed in advance and WF ₆ is introduced after being heated to 300 ° C. (WF ₆ / N ₂ = 20/2000 sccm, pressure 700 mTorr). (E.g., Materials Research Society 1989 p
p.143-149). Even with this method, the same effect could be confirmed because Si contains several% in W.

In order to control the addition amount with good reproducibility, a raw material prepared by mixing W raw material and Si raw material in a predetermined ratio was prepared in advance, and the lower electrode was formed by the CVD method. As a result, WF ₆ and SiH ₄ , using a mixture of Si ₂ H ₆ , Si ₃ H ₈ , and SiH ₂ F ₂ , a mixture of an organic compound of W and an organic compound of Si, and an organic compound raw material containing W and Si at the same time A similar effect was confirmed. In all of the above cases,
The effect of the present invention was confirmed when the Si concentration in the W film was within the range of 0.1 to 30 atomic%. FIG. 6 shows the dependency of the Ta ₂ O ₅ film growth rate and the relative dielectric constant on the Si addition ratio in the W film. If the Si addition ratio is less than 0.1%, the effect of reducing the adsorption probability due to the diffusion of silicon is not sufficient, so no decrease in the deposition rate is observed, and if it is more than 30%, the relative dielectric constant decreases due to the SiO ₂ film formation. It will be noticeable. In addition, if the diffusion amount of Si increases, it becomes a defect that causes leakage in the Ta ₂ O ₅ film.
The reduction of the leak current is most effective when it is 5 atomic%.

In the above embodiment, Si is used as an additional element.
Although the case where Ge and Ti are contained in the lower electrode by the same means is also described in the case of using
A similar effect was confirmed in the atomic% range. In addition, the distribution of additive elements in the Ta ₂ O ₅ film in the depth direction was mostly present near the film surface, as in the case of Si.

In addition, Ta, TaN, Ti, Ti are used as electrode materials.
When N, WN, Mo, MoN is used and Si, Ge are added, and Ta, TaN, WN, Mo, MoN are used as electrode materials, Ti,
Similar results were obtained when was added. In addition, in this embodiment, Ta ₂ O ₅ is formed by the CVD method using pentaethoxytantalum and oxygen as source gases for the capacitive insulating film.
Although an example using a film was explained, the Ta source gas was formed by the CVD method using other Ta organic material sources such as TaCl ₅ , Ta (OCH ₃ ) ₅ and Ta (N (CH ₃ ) ₂ ) ₅ . Even in the case, the same effect was confirmed.

In this embodiment, the insulating film T
The a ₂ O ₅ film was used, but Ti, Zr, Hf, Y, Nb oxide film and PbT
The effect was also confirmed in a mixed film of oxides such as iO ₃ , Pb (Zr _X Ti _1-X ) O ₃ , SrTiO ₃ , and Ba _X Sr _1-X TiO ₃ . These oxide films are
It can be formed by a CVD method using an organic compound of the corresponding metal as a source gas. Further, Pt, Ru, and Ru oxide were used as the lower electrode material, and T was used as the additive element.
a, Ti, Si and Ge were used. However, as an insulating film, PbTiO
_{In the case of using the three} film and the Pb (Zr _X Ti _1-X ) O ₃ film, the concentration of the element added to the lower electrode is limited to 10% or less. If the amount is larger than this, the crystallinity of the insulating film is obstructed and the relative dielectric constant is significantly lowered.

As the manufacturing device of the capacitive element, one that can be transferred to the insulating film forming device without being exposed to the atmosphere after forming the lower electrode was used. This is because when the lower electrode W was formed and left in the atmosphere for 1 week, a natural oxide film grew to a thickness of about 2 nm on the surface, which hindered the diffusion of the additive element and the effect could not be confirmed.

Further, a dynamic random access memory (DRAM) was manufactured using the capacitive element according to the present invention. A sectional view of the DRAM cell is shown in FIG. Here, the capacitance element has a SiO ₂ equivalent film thickness of 1.5 nm (Ta ₂ O ₅ film thickness of 9 nm) and a withstand voltage of 0.75 _V.
The above (judgment current density 10 to ⁸ A / cm ² ) is satisfied, and
Operation as DRAM was confirmed.

The present invention is not limited to the capacitive element,
It can also be applied to the case where it is necessary to uniformly form an insulating film on the unevenness of a metal film such as an interlayer insulating film in a semiconductor device. As the metal film in this case, in addition to W, WN,
Ti, TiN, Ta, TaN, Mo, MoN, TiW, Al, Ni, Cr, Co, A
g, Cu, Pb, Pd, Sn, V, Mn, Fe, Zr, Nb, Rh, Hf, Ir,
Pt, Au, Ru, Ru oxides and alloys thereof can be mentioned. As the additive element, an element not contained in the metal film material may be selected from Si, Ge, Ta and Ti.

Further, according to the present invention, since the adsorption probability between the flat surface portion and the side surface portion of the metal of the same material can be largely changed, the insulating film can be deposited in a self-aligned manner.
For example, if Si is selectively contained in the metal by the impurity implantation method or the sputtering method to reduce the adsorption probability of the flat metal portion, the insulating film is selectively deposited on the side surface portion of the metal.
As a result, the etching back process and the like can be omitted. Specifically, it can be applied to a W gate sidewall as shown in FIG. 8A and a trench sidewall protective film as shown in FIG. 8B. Further, when the electrode material is formed on the shape as shown in (c), a simple stack type capacitive element is obtained, and the step of forming the sidewall of the lower electrode side wall portion can be omitted.

[0022]

As described above, by using the semiconductor device and the method of manufacturing the same as the apparatus and the method of manufacturing the present invention, the problems of the prior art can be solved and the relative permittivity can be lowered. It was possible to provide a semiconductor device having an insulating film exhibiting low leakage current characteristics, and a method for manufacturing the same, by which an insulating film can be uniformly deposited on a lower electrode made of a material having large surface irregularities without causing .

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a Ta ₂ O ₅ film coating shape (a) according to the present invention and a coating shape (b) according to a conventional technique, which are formed on the unevenness due to crystal grains on the W surface, in comparison.

FIG. 2 is a cross-sectional view for explaining a process of manufacturing a capacitive element according to a conventional technique.

FIG. 3 is a cross-sectional view for explaining a process of manufacturing a capacitive element according to the present invention.

FIG. 4 is a diagram showing a comparison of leakage current-voltage characteristics of a capacitor according to the present invention and a capacitor according to a conventional technique.

FIG. 5 is a diagram showing the distribution of Si atom concentration in the Ta ₂ O ₅ film according to the present invention in the depth direction.

FIG. 6 Lower electrode W of deposition rate and relative permittivity of Ta ₂ O ₅ film
FIG. 6 is a graph showing the dependence of the medium Si content on the additive rate.

FIG. 7: DRAM manufactured by using the capacitor according to the present invention
FIG.

FIG. 8 is a diagram showing a specific application example of the self-aligned deposition effect of an insulating film according to the present invention.

[Explanation of symbols]

1 ... W crystal grain (Si added), 2 ... Ta ₂ O ₅ film, 3 ... W crystal grain, 4 ... Si substrate, 5, 12, 17 ... SiO ₂ film, 6, 8, 15
... TiN film, 7 ... W film, 9 ... W (Si added) film, 10 ... n ⁺ -
Si (source / drain region), 11 ... Polycrystalline Si (word line), 13 ... PSG / SOG / PSG (interlayer insulating film), 14 ... WSi ₂ (bit line), 16 ... BPSG / HLD (interlayer insulating film) .

Continuation of front page (51) Int.Cl. ⁶ Identification number Office internal reference number FI Technical indication location H01L 21/822 21/8242 27/108 (72) Inventor Masayuki Nakata 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Yoshitaka Nakamura 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Masaru Izawa 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Research Center Co., Ltd. In-house (72) Inventor, Yuzuru Ooji 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Hitachi Central Research Laboratory

Claims (32)

[Claims] 1. In the process of manufacturing a semiconductor device in which an insulating film is deposited / formed on a metal film by a chemical vapor deposition (CVD) method, another element is added to the metal film in advance to deposit the insulating film. A method for manufacturing a semiconductor device, characterized in that the probability of adsorption of a CVD raw material is reduced by diffusing the above-mentioned other elements into the surface of the insulating film, and the coverage of the insulating film is improved. 2. The metal film is W, and the additive element is
The method of manufacturing a semiconductor device according to claim 1, wherein the method is Si. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the amount of Si added is 0.1 to 30 atomic% with respect to W. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the method of adding Si is a method of CVD using WF ₆ and SiH ₄ as raw materials. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the method of adding Si is a method of previously forming a Si film and replacing it with W by WF ₆ . 6. A method of adding another element to the metal film, wherein a metal film is formed on the film of the addition element, and the addition element is diffused into the metal film by heat treatment before or during the deposition of the insulating film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a method of manufacturing the semiconductor device. 7. The raw material for forming the W film is WF ₆ , WCl ₆ ,
At least one or more of W (CO) ₆ , (C ₅ H ₅ ) ₂ WH ₂ (biscyclopentadienyl tungsten), W ₂ [N (CH ₃ ) ₂ ] ₆ (hexakisdimethylamide ditungsten) 3. The method for manufacturing a semiconductor device according to claim 2, wherein: 8. SiH ₄ and SiH ₂ as raw materials for the additive element Si
_{3. The} method of manufacturing a semiconductor device according to claim 2, wherein at least one kind selected from F ₂ , Si ₂ H ₆ and Si ₃ H ₈ is used. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a tantalum oxide film, and an organic compound of tantalum (Ta) or a chloride is used as a forming material thereof. 10. The method of manufacturing a semiconductor device according to claim 1, wherein the additive element remains in the metal film even after the element is completed, and a large amount thereof is present particularly in the film surface in the insulating film. . 11. In the covering shape of the insulating film by the concavity and convexity of the metal film, the curvature of the insulating film surface is deposited so as to be equal to or larger than the curvature of the bottom corner of the metal film step bottom. The method for manufacturing a semiconductor device according to claim 1. 12. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film is W to which Si is added, and the insulating film is a Ta oxide film. 13. The method of manufacturing a semiconductor device according to claim 12, wherein a silicon oxide film having a thickness of 1 nm or less is formed at the interface between the Si-added W film and the Ta oxide film. 14. The method of manufacturing a semiconductor device according to claim 1, wherein a sputtering method is used as a means for adding another element into the metal film. 15. The method of manufacturing a semiconductor device according to claim 1, wherein a CVD method is used as a means for adding another element into the metal film. 16. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity implantation method of implanting the other element into the metal film is used as a means for adding the other element into the metal film. 17. The semiconductor device according to claim 1, wherein a method of depositing the other element on the surface of the metal film and then performing a heat treatment is used as a means for adding the other element into the metal film. Production method. 18. The semiconductor device according to claim 2, wherein a CVD method using a raw material in which a substance containing W and a substance containing Si are mixed is used as a means for adding Si to the W film. Manufacturing method. 19. The raw material for CVD is at least WF <sub>6
19. The</sub> method for manufacturing a semiconductor device according to claim 18, which is a raw material mixed with a substance represented by Si _X H _{2X + 2} . 20. The raw material for CVD is at least WF ₆ .
19. The method for manufacturing a semiconductor device according to claim 18, which is a raw material mixed with a substance represented by SiH _X F _4-X . 21. The CVD raw material is an organic compound of W 2.
19. The method for manufacturing a semiconductor device according to claim 18, which is a mixture of Si and an organic compound. 22. The method of manufacturing a semiconductor device according to claim 18, wherein the raw material of the CVD is an organic compound containing W and Si at the same time. 23. The material of the metal film is W, WN, Ti, TiN,
Ta, TaN, Mo, MoN, Al, Ni, Cr, Co, Ag, Cu, Pb, Pd,
Sn, V, Mn, Fe, Zr, Nb, Rh, Hf, Ir, Pt, Au, Ru, RuO
_{2. The} method for manufacturing a semiconductor device according to claim 1, wherein the material is a material containing at least one kind of _X. 24. The material of the insulating film is Si, Ta, Ti, Zr,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is an oxide of Hf, Y, Pb, Nb, Sr, Ba, La or a mixture of these oxides. 25. The elements added to the metal film are Si and G
2. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of e, Ta and Ti is selected. 26. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the metal film is W and the additive element is Ti. 27. The amount of Ti added is 0.1 to 5 relative to W.
27. The method for manufacturing a semiconductor device according to claim 26, wherein the content is 0 atomic%. 28. The method of manufacturing a semiconductor device according to claim 1, wherein the lower electrode material of the semiconductor device is made of W and the additive element is Ge. 29. The amount of Ge added is 0.1 to 5 relative to W.
29. The method for manufacturing a semiconductor device according to claim 28, wherein the content is 0 atomic%. 30. The method of manufacturing a semiconductor device according to claim 1, wherein after the metal film is formed, a semiconductor manufacturing apparatus is used which can transport the sample without exposing the sample to the atmosphere. 31. A semiconductor device using the capacitive element manufactured by the manufacturing method according to claim 1. 32. In a method of manufacturing a semiconductor device in which an insulating film is deposited / formed on a metal film by a CVD method, another element is selectively added to the flat surface of the metal, and the raw material adsorption probability of the flat surface is controlled by the side surface. The method for manufacturing a semiconductor device is characterized in that the insulating film is deposited on the side surface of the metal film in a self-aligned manner by making the insulating film smaller than the metal part.