JPH07311629A - Integrated circuit - Google Patents

Abstract

PURPOSE:To provide the integrated circuit which has its through current reduced and does not consume electric power more than required by supplying two kinds of output currents to a driving circuit and lowering the driving capability when the speed of a clock is slow. CONSTITUTION:An input signal IN is supplied to the gates of transistors(TR) 11, 12, and 17 and a control signal EN is supplied to the gate of a TR 18 and further supplied to the gate of a TR 13 through an inverter 21. Four TRs 13, 12, 17, and 18 are interposed in series between a power source VCC and the ground, two TRs 11 and 16 are interposed between the power source VCC and ground, and the drains of the four TRs 11, 12, 16, and 17 are connected to output an output signal OUT. Therefore, when the control signal EN is 'L', the TR 11 outputs 'H' and the TR16 outputs 'L'; when the control signal is 'H', the TRs 11 and 12 output 'H' and the TRs 16 and 17 output 'L'. The output current in the former case is smaller than that in the latter case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit which operates in synchronization with a clock signal, and more particularly to an integrated circuit designed to reduce power consumption during low speed operation.

[0002]

2. Description of the Related Art For example, a microprocessor operates in synchronization with a clock signal. The number of times of switching of the circuit element per unit time is proportional to the frequency of the clock signal. Then, when the logic level is switched by the switching of the circuit element, the current for charging and discharging the capacitive load consumes power in the integrated circuit. Here, the capacitive load is, for example, the gate capacitance or drain capacitance of the transistor or the capacitance associated with the wiring. The higher the frequency of the clock signal, the lower the impedance of the capacitive load, the larger the current that charges and discharges the capacitive load, and the larger the power consumed in the integrated circuit.

Further, for example, during the waiting time of processing such as waiting while accessing the external memory, some circuit elements such as the clock driver repeat switching. In the case of performing processing with low immediacy in this way, even if the processing speed is reduced, no adverse effect occurs.Therefore, the frequency of the clock signal is made lower than before, the number of times of switching of circuit elements is reduced, and the consumption of integrated circuits is reduced. Power is being reduced.

[0004]

In a CMOS type integrated circuit, a drive circuit having a large drive capability has a large through current and a large power consumption. FIG. 11 is a circuit diagram showing a driver and its peripheral portion in a conventional integrated circuit.
In the figure, IN is an input signal input to the input terminal 63 and is given to the gates of the P-channel transistor 61 and the N-channel transistor 62. Both transistors 61 and 62 are connected in series between the power supply VCC and ground
A connection line 67 that configures 65 and connects the output terminal 64 of the driver 65, which is the connection point, and the circuit element 66 that is provided next has a resistance component, and a capacitance component 68 is present between the connection line 67 and the installation. Exists. When the input signal IN is "L" (or "H"), the driver 65 outputs "H" (or "L"). When the potential of the input signal IN is lower than the gate voltage threshold of the P-channel transistor 61 and higher than the gate voltage threshold of the N-channel transistor 62, the two transistors 61 and 62 which are conductive in the saturation region are used. A current flows from the power supply Vcc to ground. This is the shoot-through current.

Since the potential of the input signal IN is kept higher than the gate voltage threshold of the P channel transistor 61 or lower than the gate voltage threshold of the N channel transistor 62, the driver 65 operates stably. There is no steady flow of through current. However, the potential of the input signal IN is lower than the gate voltage threshold of the P-channel transistor 61 in the transition period when the input signal IN switches from “H” to “L” or from “L” to “H”, and the N-channel transistor 61 There is a period where the gate voltage is higher than the gate voltage threshold of 62, and a through current flows during this period. The maximum value of this shoot-through current is determined by the magnitude of the source-drain current when both transistors 61 and 62 are operating in the saturation region.

The drive capability of the drive circuit forming the integrated circuit is the capability of transmitting the potential to be obtained at the output end of the drive circuit as the input signal of the circuit element of the next stage. The factors that delay the transmission of this signal are the resistance component and the capacitance component existing between the output end of the drive circuit and the input end of the circuit element of the next stage. In FIG. 11, in order to charge or discharge the capacitance component 68 via the resistance component of the connection line 67 until the change in the potential obtained at the output end 64 of the driver 65 is transmitted to the input end of the circuit element 66 at the next stage. Need time. The time for this charging or discharging is the amount of positive charge or negative charge that can be supplied from the driver 65 to the capacitance component 68 per unit time, that is, the P-channel transistor 61 or the N-channel transistor 62 flows in the respective saturation regions. It is determined by the magnitude of the source-drain current. As described above, the factors that determine the driving capability of the driver 65 and the factors that determine the magnitude of the through current are the same, and when a higher driving capability is required, the through current increases.

The drive capability of a drive circuit such as a data bus driver is designed so that the integrated circuit operates properly at the maximum frequency of the expected clock. When this integrated circuit is operated in synchronization with a low frequency clock, the drive circuit drives the circuit element in the next stage for a longer time than when it is operated in synchronization with the highest frequency. Therefore, in this case, the driving capability of the driving circuit is more than necessary, and the magnitude of the through current is unnecessarily large. Thus, when operating the integrated circuit in synchronization with a clock of a low frequency, there is a first problem that more power is consumed than necessary because the drive capability that is originally needed is exhibited. Further, in a CMOS integrated circuit, there is power consumption due to a direct current component flowing in an amplifier circuit such as a sense amplifier.

FIG. 7 is a block diagram of a memory in a conventional integrated circuit. In the figure, 43 is a memory array, which stores information in binary numbers in memory cells (not shown) arranged in n rows and 4 m columns. The memory cells in each row are made up of m groups of 4 memory cells, which is 4 m in total.

The address latch 41 latches an address signal input from the outside during a period in which the clock φ1 is applied, shapes the waveform into an amplitude according to the internal logic of the memory, and supplies it to the address decoder 42. The address decoder 42 is connected to the memory array 43 by word lines and column selection lines, selects a row as one word line based on an address signal, and each set 4 in the selected row of the memory array 43 based on the address signal. One memory cell in each set is selected from the memory cells by the column selection line. The memory array 43 reads the information of each of the selected m sets of one cell and supplies it to the sense circuit 44 via the m pairs of IO lines and bar IO lines.

The sense circuit 44 is provided with m sense amplifiers (not shown), detects the signal read from the memory cell during the period when the sense amplifier enable signal SAE is given, amplifies it, and gives it to the read data latch 45. .
Read data latch 45 latches the signal applied from sense circuit 44 during the period in which clock φ2 is applied.

FIG. 8 is a schematic diagram showing the waveform of the clock in FIG. In the figure, φ1 is the clock φ1,
φ2 is a clock φ2, and both clocks φ1 and φ2 appear alternately. When reading the memory data, the read enable signal RD (not shown) is generated as "H" for a period of one cycle from the first rising of the clock φ1 to the next rising after the input of the address signal, and during that period. , The memory array 43 reads the information from the memory cell and supplies it to the sense circuit 44, the read data latch 45 latches the output amplified by the sense circuit 44, and the signal RD falls at the falling edge of the clock φ2 during the "H" period. , That latch is complete.

FIG. 9 is a circuit diagram of a sense amplifier of the sense circuit 44 shown in FIG. Transistor 31, transistor 32
Are P-channel transistors having the same characteristics, their sources are connected to the power supply voltage Vcc, their gates are connected to each other, and their drains are connected to the drains of the transistors 33 and 34, respectively. Both transistors 33 and 34 are N-channel transistors having the same characteristics. The connection point of the drains of both transistors 31 and 33 is connected to the connection point of the gates of both transistors 31 and 32.

The connection point of the drains of both the transistors 32 and 34 becomes the output point of the sense amplifier and gives the output potential V ₀ . The sources of both transistors 33 and 34 are connected to each other,
A transistor 35 is interposed between the connection point and the ground. The gate of the transistor 35 is supplied with the sense amplifier enable signal SAE, the gate of the transistor 33 is connected to the IO line, and the gate of the transistor 34 is connected to the bar IO line.

The operating principle of such a sense amplifier is known, and the potential difference between the IO line and the bar IO line is increased and output as the value of the output potential V ₀ .
In this sense amplifier, when the signal SAE is "H" and the potentials of the IO line and the bar IO line are not lower than the gate voltage thresholds of both N-channel transistors 33 and 34, respectively, There is a problem that current continues to flow. In order to avoid such a problem, the signal SAE is controlled to be "H" during the period of reading the memory. The signal SAE of the sense amplifier is "H".
During a certain period, the potential difference between the IO line and the bar IO line is increased and the output potential V ₀ is given to the read data latch 45.
The signal SAE is designed to hold "H" until the read data latch 45 completes receiving the output potential V ₀ .

FIG. 10 is a circuit diagram for generating a conventional signal SAE. In the figure, the read enable signal RD is applied to the NAND gate 38. The clock φ2 is also applied to the NAND gate 38. The output terminal of the NAND gate 38 is directly connected to the inverter 39 and outputs the sense amplifier enable signal SAE via the inverter 49. Therefore, after the address signal is input, the first "H" period of the clock φ2 is output as the sense amplifier enable signal SAE. The falling time of this "H" period is the time when the latching of the output of the sense amplifier is completed.

In the case where the integrated circuit is operated in synchronization with the assumed highest frequency clock, the sense amplifier starts the amplification operation when the signal SAE rises, and the read data is read when the clock φ2 falls. Latch 45 must complete the latching operation. That is, the circuit constant of the sense amplifier is designed to satisfy this condition. When the integrated circuit including this sense amplifier is operated in synchronization with a low frequency clock, the clock period is longer than the assumed maximum frequency clock period, so the "H" period of the signal SAE is necessary for the original data sensing. It is longer than the "H" period. There is a second problem that the sense amplifier continues to flow a direct current and consumes power during a period unnecessary for this lengthened data sensing.

In order to solve the first problem of the present invention, the drive circuit is provided with different drive capabilities, and when the clock frequency is low, the through current of the drive circuit is driven by driving the next stage with a small drive capability. The first purpose is to provide an integrated circuit which does not consume more power than necessary, and in order to solve the second problem, a direct current can be passed only during a period originally required by a functional circuit. A second object is to provide an integrated circuit that does not consume more power than necessary.

[0018]

An integrated circuit according to a first aspect of the present invention is an integrated circuit having a drive circuit for driving a circuit of the next stage in synchronization with clocks having a plurality of frequencies, and a plurality of different switchable circuits are provided. It is characterized in that it is provided with a drive circuit having a drive capability and a determination means for determining whether the frequency of the clock is high or low, and is configured to switch the drive capability of the drive circuit according to the determination result of the determination means.

In the integrated circuit according to the second aspect of the invention, in the integrated circuit which operates in synchronization with clocks of a plurality of frequencies, the next stage circuit is driven by the output current output from n transistors connected in parallel. A drive circuit, a switching circuit that individually turns on / off the operating power supply of n-1 transistors of the drive circuit according to a given signal, and a determination signal by determining that the clock frequency is lower than a predetermined value. An output circuit for outputting is provided, and the determination circuit output by the output circuit is applied to the switching circuit to reduce the output current output by the drive circuit.

In the integrated circuit according to the third aspect of the present invention, a drive circuit composed of a P-channel transistor and a drive circuit composed of an N-channel transistor, which should be connected between the operating power supply and the ground, are connected in series, and both drive circuits are connected. It is characterized in that the output current is obtained from the point.

An integrated circuit according to a fourth aspect of the present invention is an integrated circuit having a functional circuit that synchronizes with a divided clock obtained by dividing the frequency of the original clock, in which the logic of the original clock and the divided clock is used. A driving means for driving the functional circuit by a product is provided.

An integrated circuit according to a fifth aspect of the invention is such that a CMOS is synchronized with a divided clock obtained by dividing the frequency of an original clock.
An integrated circuit having a sense amplifier for amplifying data read from a memory is characterized by comprising driving means for driving the sense amplifier by a logical product of the original clock and the divided clock.

[0023]

In the first aspect of the invention, the drive circuit has a plurality of different drive capabilities that can be switched, the determination means determines whether the frequency of the clock is high or low, and the drive capability of the drive circuit is determined according to the determination result of the determination means. Therefore, the driving capability, that is, the output current can be switched according to the level of the clock frequency, and the through current of the driving circuit can be suppressed to be small according to the frequency.

In the second invention and the third invention, the drive circuit drives the circuit of the next stage by the output current output from the n transistors connected in parallel, and the switching circuit is (n-1) of the drive circuit. The operating power supply of each transistor is turned on / off according to a given signal, and the output circuit determines that the frequency of the clock is lower than a predetermined value and outputs a determination signal,
When the clock frequency is lower than a predetermined value, the shoot-through current of the drive circuit is generated because the output current output by the drive circuit is configured to be small by applying the determination signal output by the output circuit to the switching circuit. Can be made smaller.

In the fourth aspect of the invention, since the driving means drives the functional circuit by the logical product of the original clock and the divided clock, the functional circuit functions at a necessary time point under the divided clock, and the functional period is It is the shortest period based on the original clock.

In the fifth invention, the driving means drives the sense amplifier by the logical product of the original clock and the divided clock. Therefore, the sense amplifier reads the data read from the CMOS memory at a necessary time point under the divided clock. The period of amplification is the shortest period based on the original clock.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. Embodiment 1. FIG. 1 is a circuit diagram of a drive circuit functioning as an inverter based on the first invention, the second invention or the third invention. In the figure, 1 is an input terminal to which an input signal IN is input, and 2 is a control terminal to which a control signal EN is applied. The number of output terminals for outputting the output signal OUT is 3. Between the output terminal 3 and the power supply Vcc, the series circuit of the transistor 12 and the transistor 13 and the transistor 11 are connected in parallel, and between the output point for outputting the output signal OUT and the ground,
A series circuit of the transistor 17 and the transistor 18 and the transistor 16 are connected in parallel.

Transistors 11, 12, 13 are P-channel transistors, and transistors 16, 17, 18 are N-channel transistors. Input signal IN is four transistors 11,1
The control signal EN is applied to the gates of the transistors 2, 16 and 17, and is applied to the gate of the transistor 18 and also to the gate of the transistor 13 via the inverter 21. The three transistors 11, 12, 13 and the inverter 21 and their peripheral portions constitute a drive circuit for supplying positive charges, and the three transistors 16, 17,
18 and its peripheral portion constitute a drive circuit for supplying negative charges. Then, both drive circuits form a drive circuit that functions as an inverter.

Next, the operation will be described. When the control signal EN is "H", the gate of the transistor 13 is "L" by the inverter 21 and the transistor 13 is in the ON state,
Since the gate of the transistor 18 is "H", the transistor 18 is in the ON state. When the input signal IN is "L" in this state, both transistors 11 and 12 are turned on, both transistors 16 and 17 are turned off, and the power supply VCC
Is output, and the output signal OUT becomes "H". Control signal EN
Is "H" and the input signal IN is "H", both transistors 11 and 12 are turned off, and both transistors are turned off.
16, 17 is turned on, the ground potential is output, and the output signal
OUT becomes “L”.

When the control signal EN is "L", both the transistors 13 and 18 are off. Therefore, in this state, when the input signal IN is "L", the transistor
Since 11 is in the ON state, the power supply Vcc is not applied to the transistor 12. In this state, the input signal IN is "H".
At this time, the transistor 16 is in the ON state and the ground potential is not given to the transistor 17.

Therefore, the drive capability of the present drive circuit is such that when the control signal EN is "H" and the input signal IN is "L", the positive charge supply capability and the transistor provided through the series connection of the transistors 12 and 13 are Determined by the sum of the positive charge supply capability given via 11, the control signal EN is "H" and the input signal
When IN is “H”, it is determined by the sum of the negative charge supply capability provided through the series connection of the transistors 17 and 18 and the negative charge supply capability provided through the transistor 16.
When the control signal EN is “L” and the input signal IN is “L”, it is determined by the positive charge supply capability given through the transistor 11, and the control signal EN is “L” and the input signal IN is “H”. In that case, it is determined by the negative charge supply capability provided through the transistor 16.

As described above, the present driving circuit can switch the driving ability in two stages by the control signals "H" and "L". By connecting a drive circuit that outputs "H" and a drive circuit that outputs "L" between the power supply Vcc and the ground, the next stage can be driven as an inverter.

When the present drive circuit is used as a driver for a bus that transfers data in one cycle of a clock in an integrated circuit and the integrated circuit operates in synchronization with a high speed clock, the control signal EN is set to "H". By setting
The bus can be charged and discharged quickly, and high-speed bus transfer can be realized. When the integrated circuit operates in synchronization with the low-speed clock, the control signal EN is set to "L" so that the bus transfer is slow enough to complete the data transfer in one cycle. It is possible to reduce the driving capability and bring it close to the necessary minimum size, reduce the through current, and reduce the power consumption of the integrated circuit. In this case, it takes a long time to charge and discharge the bus, and it is possible that a long shoot-through current will flow to the bus receiver.However, if a latch is used as the bus receiver, input will occur only when necessary. By shutting off, it is possible to eliminate the possibility that a long-time through current will flow.
When a circuit element other than the latch is used as the bus receiver, the driving capability of the bus receiver is smaller than that of the bus driver, and the shoot-through current flowing there is not a problem.
Therefore, it is necessary to identify whether the clock is fast or slow.

FIG. 2 is a block diagram of a circuit for identifying the low speed and outputting the signal SLOW when the clock is low speed.
The clock input in the figure is given to the low-pass filter 28 via the capacitor 25. The connection point between the capacitor 25 and the low-pass filter 28 is grounded via the resistor 26 and the diode 27 in parallel. The differentiating circuit consisting of the capacitor 25 and the resistor 26 generates an upward trigger pulse at the rising edge of the clock and a downward trigger pulse at the falling edge of the clock. The downward trigger pulse is grounded by the diode 27, and the upward trigger pulse is given to the low pass filter 28. When the clock is high speed, the upward trigger pulse is blocked by the low pass filter 28, and when the clock is low, the upward trigger pulse passes through the low pass filter 28 and AD
It is given to the converter 29, AD-converted, and given to the decoder 30 as a digital value.

The decoder 30 stores a digital value serving as a reference for identifying whether or not the clock speed is low. The digital value provided from the AD converter 29 is compared with this reference digital value. It is determined whether the speed is low or not, and when it is determined that the speed is low, "L" is output as the signal SLOW. The signal SLOW is used as the control signal EN. In addition,
In this circuit, the upward trigger pulse obtained by differentiating the clock is passed through the low pass filter 28 to the AD converter.
Although it is input to 29, when the clock is generated by the PLL method inside the integrated circuit, the gate control voltage given to the voltage controlled oscillator (not shown) is
By inputting it to the D converter 29, the decoder 30 performs the same operation, and when it determines that the clock is low speed, it outputs "H".
Output as SLOW signal.

Needless to say, when the clock signal has a high speed, the signal HIGH can be output by identifying the high speed by a similar method. In addition, when a high-speed or low-speed clock signal is obtained by switching the division ratio of the clock signal according to the result of decoding the program inside the CPU (not shown) that is executing the program,
The control signal EN can be generated based on the signal for switching the frequency division ratio. When the clock signal is supplied from the outside of the integrated circuit, a signal indicating whether the clock signal is high speed or low speed is similarly given to the integrated circuit from the outside, and the control signal EN is supplied based on the signal. Can be generated.

Embodiment 2. FIG. 3 is a circuit diagram of a drive circuit functioning as an inverter based on the first invention, the second invention or the third invention. In the figure, EN1 and EN2 are both control signals. The control signal EN1 is given to the gate of the transistor 13 via the inverter 21 on the one hand, and is directly given to the gate of the transistor 18 on the other hand. The control signal EN2 is given on the one hand to the gate of the transistor 15 via the inverter 22, and on the other hand to the gate of the transistor 20 as it is. Input signal IN is 6 transistors 11,12,14,1
It is given to each gate of 6,17,19.

Output point for outputting output signal OUT and power supply V
Two transistors 14 and 15 are connected in series between CC,
Two transistors 19 and 20 are connected in series between the output point for outputting the output signal OUT and the ground. Both transistors 14 and 15 are P-channel transistors, and both transistors 19 and 20 are N-channel transistors.
Since other configurations are similar to those in FIG. 1, the same parts are designated by the same reference numerals and the description thereof will be omitted.

Next, the operation will be described. Both control signals EN
If both 1 and EN2 are "H", 4 transistors 1
3,14,18,20 are in the ON state. In this state, when the input signal IN is given as "L", the three transistors 11, 12, 14 are turned on and the three transistors 16, 17,
19 is turned off and the output signal OUT becomes "H". The drive capability of the drive circuit in this case is determined by the sum of the positive charge supply capability provided through the transistors 14 and 15 connected in series, the transistors 12 and 13 connected in series, and the transistor 11 respectively.

When both control signals EN1 and EN2 are "H" and the input signal IN is given as "H", the three transistors 11, 12, 14 are in the OFF state and the three transistors are 16, 17, 19 are turned on, and the output signal OUT becomes "H". The drive capability of the drive circuit in this case is determined by the sum of the negative charge supply capability provided through the transistors 19 and 20 connected in series, the transistors 17 and 18 connected in series, and the transistor 16 respectively.

When the control signal EN1 is "H", the control signal EN2 is "L" and the input signal IN is "L", the two transistors 11 and 12 are in the ON state. 16, 17 are turned off, and the output signal OUT becomes "H". The driving capability of the driving circuit in this case is that the transistors 12 and 13 and the transistor connected in series are
It is determined by the sum of the positive charge supply capacities given through 11 respectively.

When the control signal EN1 is "H", the control signal EN2 is "L", and the input signal is "H", the two transistors 11 and 12 are turned off. 16, 17 will be in the ON state, and the output signal OUT will be "L". In this case, the driving capability of the driving circuit is the transistor 17 and 18 and the transistor connected in series.
It is determined by the sum of the negative charge supply capacities given through 16 respectively.

Further, both control signals EN1 and EN2 are "L".
In case of, all four transistors 13,15,18,20 are OF
It is in the F state. Therefore, in this state, when the input signal IN is given as "L" (or "H"), the driving capability of the driving circuit is the positive charge (or negative charge) supply capability given through the transistor 11 (or 16). Determined by That is, three transistors 11, 12, 14 (or three transistors connected in parallel)
The output current of (16,17,19) drives the circuit of the next stage, and the two transistors 13,15 (or 18,20) respectively output two transistors 12,14 (or 18,20) according to the control signals EN1, EN2. The operating power supply of 17, 19) is turned on and off individually. Thus both control signals EN1, EN2
When the control signal EN1 is “H” and the control signal EN2 is “L”, the drive capability of the drive circuit is larger than when both are “L”, and both control signals EN1 and EN2 are “H”. In the case of ", the driving capability of the driving circuit is larger.

In order to generate both control signals EN1 and EN2, it is necessary to identify whether the clock is high speed, medium speed or low speed. This is a signal HI for identifying high speed and a signal MID for identifying medium speed by changing the decoder 30 in the block diagram of FIG. 2 for identifying clock speed.
Can be obtained.

FIG. 4 is a circuit diagram of a circuit for generating the control signals EN1 and EN2. In the figure, HI is a signal that becomes "H" when it is determined that the speed of the clock signal is high,
The MID is a signal that becomes "H" when it is determined that the speed of the clock signal is a medium speed. When it is determined that the speed of the clock signal is low, both HI and MID are "L".

The signal HI is output as the control signal EN2 via the buffer 23 on the one hand, and is output as the control signal EN1 via the OR gate 24 on the other hand. The signal MID is output as the control signal EN1 via the OR gate 24. Therefore, when the signal HI is "H" and the signal MID is "L", both control signals EN1, EN2
Are both "H", and when the signal MID is "H" and the signal HI is "L", the control signal EN1 is "H" and the control signal EN2 is
Becomes "L", and both control signals EN1 and EN2 both become "L" when both signals HI and MID are "L".

In this embodiment, the clock frequency is set to 3
The means for switching the driving capability of the drive circuit to any one of the three steps according to the classification has been described. By switching the drive capability of the drive circuit to one of multiple levels, it is possible to more finely reduce the power consumption of the integrated circuit.

Embodiment 3. FIG. 5 is a circuit diagram of a circuit for generating a sense amplifier enable signal SAE for driving a sense amplifier according to the fourth or fifth invention. In the figure
CK0 is the original clock that operates the memory, its duty ratio is 50%, it is given to the 1/2 frequency divider 50, and it becomes the inverted original clock bar CK0 via the inverter 51, and becomes the 3-input NAND gate 57. Given to. 1/2 divider 50
Is an original clock CK given by a control signal not shown.
The frequency of 0 is divided into 1/2 and output as the signal CK1 or the original clock CK0 is output as it is as the signal CK1.The signal CK1 generated in this way is NANDed. It is given to the gate 52 and also given to the NAND gate 54 through the inverter 53. NAND gate 52 is
The output is given to the NAND gate 54, and the clock φ 1 is output via the inverter 55. The NAND gate 54 gives its output to the NAND gate 52 and outputs the clock φ 2 via the inverter 56.

Both NAND gates 52 and 54 form a flip-flop, the clock φ1 is given to the address latch 41 which latches the address signal, and the clock φ2 is the read data for designating the period for latching the data read from the memory. It is supplied to the latch 45 and also to the 3-input NAND gate 57. When the address signal is applied to the address latch 41, the read enable signal RD generated in the circuit (not shown) is input to the 3-input NAND gate 57. 3-input NA
The input terminal of the ND gate 57 is directly connected to the inverter 58,
Sense amplifier enable signal SAE via inverter 58
Is output to the sense circuit 44.

Next, the operation will be described. FIG. 6 is a time chart showing the operation of the circuit of FIG. 6A shows the original clock CK0, and FIG. 6B shows that the original clock CK0 is 1/2.
The signal CK1 divided by the divider 50 is shown. In the initial state, if both CK0 and CK1 are "L", both inputs of the NAND gate 52 are "L" and both inputs of the NAND gate 54 are "H". It becomes L "and the clock φ2 becomes" H ". At the rising time t ₁ of the original clock CK0, the signal CK1 rises, the output of the NAND gate 52 does not change, the polarity of the output of the NAND gate 54 is inverted and becomes “H”, and this inverted “H” is transferred to the NAND gate 52. When applied, both inputs of the NAND gate 52 become "H". Therefore, the clock φ2 becomes "L" and the clock φ1 becomes "H". Original clock CK0
The signal CK1 does not change at the time point t _{2 when} the signal falls.

At the rising time t ₃ of the original clock CK0, the signal CK1 falls, the output of the NAND gate 54 does not change, the polarity of the output of the NAND gate 52 is inverted to "H", and this inverted "H". Are applied to the NAND gate 44, the two inputs of the NAND gate 54 become "H". Therefore, the clock φ1 becomes "L" and the clock φ2 becomes "H". FIG. 6 (C) shows the clock φ1, and FIG.
(D) shows the clock φ2. In this way, both clocks φ1 and φ2 are obtained. Although there is a slight time lag, the original clock CK0 is used during the "H" period of both clocks φ1 and φ2.
Is almost equal to one cycle of.

Thereafter, the state where the address signal is input at time t ₄ after the clock φ1 continues to fall and the clock φ2 falls is shown in FIG. 6 (E).
Period from the rise time t ₅ to the next rising time t ₆ of the clock φ1 follow, read enable signal RD is a situation that is generated as "H" shown in FIG. 6 (F). This signal RD, clock φ2 and inverted original clock bar
CK0 is input to the 3-input NAND gate 57. FIG. 6G shows the situation where the logical product of these three inputs is generated as the sense amplifier enable signal SAE via the inverter 58. The "H" period of the sense amplifier enable signal SAE is equal to the "H" period of the inverted original clock bar CK0, within the "H" period of the read enable signal RD, within the "H" period of the clock φ2 of the read data latch period. And it exists at the end of the period. Therefore, the period for driving the sense amplifier is equal to the shortest period required for original data sensing, and the time for driving the sense amplifier is the time required for latching data.

Therefore, at the time of a low speed clock in which the frequency of the clocks φ1 and φ2 is 1/2 of the frequency of the original clock CK0, the sense amplifier is further supplied with no current for a period unnecessary for data sensing. Since the output is completely latched by the read data latch 45, a read data latch error does not occur.

The frequency of clocks φ1 and φ2 is the original clock CK
If it is 1/4 of the frequency of 0, 1/4 of original clock CK0 in addition to read enable signal RD, clock φ2, inverted original clock
A clock φ2 (1/4) divided by is added to generate a sense amplifier enable signal SAE by the logical product of 4 inputs, and the sense amplifier enable signal SAE is supplied to the sense circuit 44, so that a current flows to the sense amplifier for a period unnecessary for data sensing. Therefore, it is not necessary to consume more power than necessary. This is the same even when the frequencies of the clocks φ1 and φ2 are 1/8 or less of the frequency of the original clock CK0.

In this embodiment, the sense amplifier enable signal generating circuit which does not consume more DC current than necessary in the sense amplifier has been described. However, this method is applied to a DC circuit such as an amplifier circuit which operates when the clock frequency changes. It goes without saying that by applying it to a functional circuit that consumes current, it is not necessary to consume more power than necessary.

[0056]

According to the first aspect of the present invention, since the drive circuit having a plurality of different switchable drive capabilities is provided and the drive capability of the drive circuit is switched according to the level of the clock frequency judged by the judging means, the clock The shoot-through current of the drive circuit increases or decreases according to the level of the frequency, and unnecessary power is not consumed.

According to the second and third aspects of the present invention, the driving circuit for driving the circuit of the next stage by the output current output from the n transistors connected in parallel, and the n-1 transistors of the driving circuit. A switching circuit that individually turns on and off the operating power source according to a given signal, and when the frequency of the clock is lower than a predetermined value, the output means outputs a determination signal,
Since the drive capability of the drive circuit is made small, the through current of the drive circuit is reduced, and more power than necessary is not consumed.

According to the fourth aspect of the invention, since the driving means drives the functional circuit by the logical product of the original clock and the divided clock, the functional circuit functions for the shortest period based on the original clock, and the power more than necessary is supplied. Do not consume.

According to the fifth aspect of the invention, since the driving means drives the sense amplifier by the logical product of the original clock and the divided clock, the period during which the sense amplifier amplifies the data read from the CMOS memory is the shortest period based on the original clock. Next to
Do not consume more power than necessary.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an inverter having two types of drive capabilities according to a first embodiment.

FIG. 2 is a block diagram of a circuit for identifying that a clock is low speed.

FIG. 3 is a circuit diagram of an inverter having three types of drive capabilities according to the first embodiment.

FIG. 4 is a circuit diagram of a circuit that generates a control signal for the inverter shown in FIG.

FIG. 5 is a circuit diagram of a circuit that generates a sense amplifier enable signal according to a second embodiment.

FIG. 6 is a time chart showing the operation of the circuit shown in FIG.

FIG. 7 is a block diagram of a memory in a conventional integrated circuit.

8 is a schematic diagram showing waveforms of clocks in FIG. 7. FIG.

9 is a circuit diagram of a sense amplifier of the sense circuit shown in FIG.

FIG. 10 is a circuit diagram of a circuit for generating a conventional sense amplifier enable signal.

FIG. 11 is a circuit diagram showing a conventional driver and its peripheral portion.

[Explanation of symbols]

41 address latch, 43 memory array, 44 sense circuit, 45 read data latch, CK0 Original clock with the highest driving speed.

Claims (5)

[Claims] 1. An integrated circuit comprising a drive circuit for driving a circuit in the next stage in synchronization with clocks of a plurality of frequencies,
A drive circuit having a plurality of switchable different drive capacities and a judgment unit for judging whether the clock frequency is high or low are provided, and the drive capacities of the drive circuits are switched according to the judgment result of the judgment unit. An integrated circuit characterized by the above. 2. In an integrated circuit which operates in synchronization with clocks of a plurality of frequencies, a drive circuit for driving a circuit of the next stage by an output current output from n transistors connected in parallel, and a drive circuit of the drive circuit. a switching circuit that individually turns on / off the operating power supply of the n-1 transistors according to a given signal; and an output circuit that determines that the frequency of the clock is lower than a predetermined value and outputs a determination signal, An integrated circuit which is configured to reduce an output current output from the drive circuit by applying a determination signal output from the output circuit to the switching circuit. 3. A drive circuit composed of a P-channel transistor and a drive circuit composed of an N-channel transistor, which are to be connected between an operating power supply and ground, are connected in series, and an output current is obtained from a connection point of both drive circuits. The integrated circuit according to claim 2. 4. In an integrated circuit having a functional circuit that synchronizes with a divided clock obtained by dividing the frequency of an original clock, the functional circuit is driven by a logical product of the original clock and the divided clock. An integrated circuit comprising driving means. 5. A CMOS integrated circuit having a sense amplifier for amplifying data read from a CMOS memory in synchronization with a divided clock obtained by dividing the frequency of an original clock, wherein the original clock and the divided clock are included. A CMOS integrated circuit comprising driving means for driving the sense amplifier by a logical product with a clock.