JPH0731080A - Waveform storage device - Google Patents

Abstract

PURPOSE:To easily diagnose an apparatus by writing a state change signal detected by a CPU in a storage medium by a delay of a predetermined time when a state change having a fault of a power converter occurs, and storing waveform data before and after the change. CONSTITUTION:An AC commercial power source 1 is converted by a power converter 2a, and supplied to a load 3 through a CT. Outputs of the CT and the PT are converted to digital values by an A/D converter 5, and supplied to a CPU 4, buffers 6a, 6b to monitor a state change. When the CPU 4 detects a change of a state having a fault such as service interruption, recovery, and the like, the CPU 4 outputs signals 103, 104a-104d, operates a monostable multivibrator 9, an output of a logic element 10 is delayed by a predetermined time by an FF11 and a delay circuit 12, and a write enable signal 102 is output. A state change signal is recorded on a storage medium 7a or 7b through the buffer 6a or 6b. Thus, a diagnosis is facilitated from waveform data before and after the stage change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform storage device for storing and storing output waveform data of a power converter.

[0002]

2. Description of the Related Art FIG. 4 shows an example of the configuration of a conventional data storage device. In FIG. 4, 1 is an AC power supply, 2 is a power conversion device that converts the power of the AC power supply 1, 3 is a load, 4 is a central processing unit (hereinafter referred to as CPU), 5 is a voltage / current value of the power conversion device 2. A / D converter for converting to digital data
Data, 6a and 6b are buffers for permitting or prohibiting data input, 7a and 7b are storage media, 8 is an inverting element, 101 is a data bus, and 102 is a write enable signal supplied by the CPU 4. The power converter 2 is an uninterruptible power supply (hereinafter referred to as UPS), a thyristor leona.
The device is a typical one.

The data of the data bus 101 is stored in the storage medium 7a.
When it is desired to record the data in the memory, the CPU 4 sets the write permission signal 102 to "1" and opens the buffer 6a. As a result, the data on the data bus 101 is connected to the storage medium 7a. When the data of the data bus 101 is to be recorded in the storage medium 7b, the CPU 4 sets the write enable signal 102 to "0" and opens the buffer 6b. As a result, the data of the data bus 101 is recorded in the storage medium 7b.

[0004]

In the configuration of FIG. 4, the CP
Since there is only one type of write enable signal from U4, the storage medium 7
Switching between a and 7b is generally performed when the power conversion device 2 fails. However, in this case, it is not possible to collect the output waveform data other than a failure, such as a change in the operating state of the power converter 2, for example, a sudden load change or a power failure. -A facility for collecting data,
When there was no method, the waveform data showing the electrical characteristics of the power conversion device 2 could not be collected.

The present invention has been made in order to eliminate the above-mentioned drawbacks. Not only when a failure occurs in the power conversion device, but also when the operating condition of the power conversion device changes due to a power failure or the like, a fixed time elapses. After that, the storage medium of the storage destination is switched, the waveform data before and after the operating state of the power converter is changed is stored in the storage medium, and the waveform data showing the electrical characteristics is left, thereby diagnosing the power converter. It is an object of the present invention to provide a waveform storage device for performing the above.

[0006]

In order to achieve the above object, the present invention comprises the following elements as shown in FIG. 1. UPS2a failure signal 10 supplied from CPU
3. A monostable multivibrator 9 which outputs a one-shot pulse by catching the rising of each of the power failure signal 104a, the power recovery signal 104b, the UPS power feeding signal 104c, and the bypass power feeding signal 104d from "0" to "1". An OR element 103. which outputs the OR of the outputs of the monostable multivibrators 9. 3. A flip-flop 11 which alternately outputs "0" and "1" by using the output pulse of the OR element 10 as a clock input. The change in the output of the flip-flop 11 is delayed for a fixed time, and the write enable signal is set to 1 in the buffers 6a and 6b.
Delay element 12 that outputs 02

[0007]

Function: Signal groups 103, 104a to 10 from the CPU 4
When any of 4d changes from “0” to “1”, that is, when any of the phenomena of failure, power failure, power recovery, UPS power supply and bypass power supply occurs in UPS 2a, the monostable multivibrator 9 Since the one-shot pulse is output from any one of the outputs, the output of the OR element 10 rises from "0" to "1".

The flip-flop 11 alternately outputs "0" and "1" with the rising edge of the OR element 10 as a clock input. That is, the logic of the output of the flip-flop 11 is inverted when any one of the phenomena of failure, power failure, power recovery, UPS power supply, and bypass power supply occurs.

Further, if the output of the flip-flop 11 is delayed by the delay element 12 for a certain time, a failure, a power failure, a power recovery, a U
After a certain period of time from the occurrence of either PS power supply or bypass power supply, only one of the buffers 6a and 6b is opened and the other is closed.

As a result, the storage medium whose buffer is closed has waveform data from the time when any one of the phenomena of failure, power failure, power recovery, UPS power supply and bypass power supply occurs until a certain time elapses. Recorded and saved.

[0011]

1 is a block diagram showing an embodiment of the present invention, and the present invention will be described below with reference to FIG. Figure 1
Power converter 2a, for example, an uninterruptible power supply has a failure, a power failure,
After a certain period of time has passed from the time of power recovery, UPS power supply, or bypass power supply, access to the currently recording storage medium is stopped and waveform data is recorded on the other storage medium. It is a waveform storage device to be executed.

In FIG. 1, U supplied from the CPU 4
A monostable multivibrator that outputs a one-shot pulse by catching the rising from "0" to "1" of the PS2a failure signal 103, power failure signal 104a, power recovery signal 104b, UPS power feeding signal 104c, and bypass power feeding signal 104d. , A logical sum element 10 that outputs the logical sum of the outputs of the monostable multivibrator 9, and output pulses of the logical sum element 10 as clock inputs, "0" and "1".
And a delay element 12 that delays the change of the output of the flip-flop 11 for a predetermined time and outputs the write enable signal 102 to the buffers 6a and 6b.

Signal groups 103, 104a from the CPU 4
When the dash of 104d changes from "0" to "1",
In other words, when a phenomenon such as a failure, a power failure, a power recovery, a UPS power supply, or a bypass power supply occurs in the UPS 2a, the timing of the phenomenon occurrence is transmitted to the circuit in the subsequent stage, so that the monostable multivibrator 9 has five outputs. Only one of them becomes a one-shot pulse.

Since the logical sum element 10 takes the logical sum of the five outputs of the monostable multivibrator 9, the logical sum element 1
The output of 0 rises from "0" to "1". OR element 10
Of the flip-flop 11 as the clock input
Outputs "0" and "1" alternately. That is, the logic of the output of the flip-flop 11 is inverted when any one of the phenomena of failure, power failure, power recovery, UPS power supply, and bypass power supply occurs.

When the output of the flip-flop 11 is used as a storage medium switching trigger, access is stopped immediately after the occurrence of the phenomenon and the waveform after the occurrence of the phenomenon is not recorded. It is necessary to delay and record the waveform data after the phenomenon occurs for a certain period of time.

Therefore, if the output of the flip-flop 11 is delayed by the delay element 12 for a certain time, a failure, a power failure, a power recovery, a U
After a certain period of time has elapsed from the occurrence of either PS power supply or bypass power supply, only one of the buffers 6a and 6b is opened and the other is closed. As a result, the waveform data from the time when the phenomenon occurs until a certain time has elapsed is recorded and stored in the storage medium whose buffer is closed.

As described above, not only when a failure occurs in the UPS, but also when a main circuit phenomenon other than the failure such as a failure, a power failure, a power recovery, a UPS power supply, and a bypass power supply is used as a storage medium switching trigger signal, a predetermined time period is stored. By delaying the trigger signal, the waveform data from the occurrence of the phenomenon until after a lapse of a fixed time is recorded in the storage medium, and the waveform data showing the electrical characteristics is recorded.
You can leave the data.

Next, another embodiment of the present invention will be described with reference to FIG. 2 in which the same parts as those in FIG. Figure 2
Allows the timing of switching the storage medium to be changed according to the phenomenon that occurs in the UPS 2a, so that a failure, a power failure,
It is a waveform storage device capable of leaving waveform data showing electrical characteristics at an appropriate timing for each phenomenon after a lapse of a certain time from a time point at which one of power recovery and UPS power supply occurs.

Power failure signal 104a of UPS 2a, UPS power supply signal 104c and failure signal 1 supplied from CPU 4
The delay elements 12a, 12b, and 12c that delay the change of 03 by the times t1, t2, and t3, respectively, and the outputs of the delay elements 12a, 12b, and 12c are detected as rising from "0" to "1". A monostable multivibrator 9 that outputs a shot pulse, a logical sum element 10 that outputs a logical sum of the outputs of the monostable multivibrator 9, and an output pulse of the logical sum element 10 as a clock input And a flip-flop 11 that alternately outputs "1".

Power failure signal 104 supplied from CPU 4
a, the UPS feed signal 104b and the fault signal 103 change from "0" to "1" when each phenomenon occurs in the UPS. The outputs of the delay elements 12a to 12c are the power failure signal 1
04a, UPS feed signal 104b and failure signal 103 change from "0" to "1" at times t1 and t2, respectively.
, T3, it changes from "0" to "1", and the timing of stopping the recording of the waveform data to the storage medium and switching the access to another storage medium is transmitted to the circuit in the subsequent stage.

In the monostable multivibrator 9, one of the outputs of the delay elements 12a to 12c is "0" to "1".
The one-shot pulse is output by capturing the timing of the change to.

Since the logical sum element 10 takes the logical sum of the three outputs of the monostable multivibrator 9, the logical sum element 1
The output of 0 rises from "0" to "1". OR element 1
The flip-flop 11 alternately outputs "0" and "1" with the rising edge of the output of 0 as the clock input. That is, the output of the flip-flop 11 is a power failure, UPS power supply,
Each time t1 from the occurrence of one of the failure phenomena
, T2, and t3, the logic is inverted.

The method of opening / closing the buffer 6a or 6b by the write enable signal 102 which is the output of the flip-flop 11 and saving the recorded contents of the storage medium 7a or 7b is the same as in FIG. To do.

As described above, in this embodiment, by using the delay elements 12a to 12c having the time constants for each phenomenon, the waveform data showing the electrical characteristics is left at an appropriate timing for each phenomenon. be able to.

FIG. 3 in which the same parts as those in FIGS. 1 and 2 are designated by the same reference numerals is a block diagram showing still another embodiment of the present invention. This embodiment is an example in which four storage media are used. When a UPS failure, power failure, or UPS power feeding phenomenon occurs, the waveform storage device sequentially switches the storage medium at an appropriate timing for each phenomenon.

The failure signal 103 supplied from the CPU 4,
The operations of the power failure signal 104a, the UPS power feeding signal 104b, the delay elements 12a to 12c, the monostable multivibrator 9 and the logical sum element 10 are the same as those in FIG.

The 2-bit shift register 13 (hereinafter referred to as a shift register) uses the rising edge of the output of the OR element 10 as a clock input, and whenever the phenomenon of UPS occurs and the OR element 10 rises, 2 bits of 0 to 3 are sequentially output.

The 2-input 4-output decoder 14 (hereinafter referred to as a decoder) outputs "0" only for the write enable signal 102a when the 2-bit data output from the shift register 13 is "0". In the same way, only when 102 is 102b,
"0" is output only when the value is 2 and only when the value is 3 and 102d.

The buffers 6a to 6d are opened only when the write enable signals 102a to 102d are "0", and the waveform data are written in the storage media 7a to 7d, respectively. As a result, after a certain phenomenon occurs in the UPS, the access to another storage medium is switched after a predetermined time for each phenomenon has elapsed, and the waveform data showing the electrical characteristics is stored at an appropriate timing for each phenomenon. It

In the present invention, by using the shift register and the decoder, not only the waveform storage device having two storage media as shown in FIGS. 1 and 2, but also four or more storage media are provided. Even in the waveform storage device, the waveform data showing the electrical characteristics can be left at an appropriate timing for each phenomenon that occurs.

[0031]

As described above, according to the present invention, when a phenomenon such as a failure or a power failure occurs in the power converter,
It is possible to provide a waveform storage device capable of leaving waveform data showing electrical characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram of a waveform storage device showing an embodiment of the present invention.

FIG. 2 is a block diagram of a waveform storage device showing another embodiment of the present invention.

FIG. 3 is a block diagram of a waveform storage device showing still another embodiment of the present invention.

FIG. 4 is a block diagram of a conventional waveform storage device.

[Explanation of symbols]

1 ... Commercial AC power supply 2, 2a
… Power converter 3… Load 4
... Central processing unit 5 ... A / D converters 6a to 6d
... Buffers 7a to 7d ... Storage medium 8
… Inversion element 9… Monostable multivibrator 10
... OR element 11 ... Flip-flops 12 to 12
c ... Delay element 13 ... 2-bit shift register 14
... decoder 100 ... write enable signal generating means 101
... Data bus 102 to 102d ... Write enable signal 103
… Fault signal 104a… Power failure signal 104b
… Recovery signal 104c… UPS power supply signal 104d
… Bypass power signal

Claims (2)

[Claims] 1. A central processing unit for controlling data for recording a waveform of a power conversion device, one or a plurality of storage media for recording or reproducing the waveform data, and this storage A waveform storage device comprising one or a plurality of buffers for permitting or prohibiting data input to the medium, and switching a storage medium for recording data by a write permission signal supplied from the central processing unit. In addition to the above, in addition to the case where a failure occurs in the power conversion device, a write permission signal generating means for switching a storage medium for recording data according to a change in the state of the power conversion device after a lapse of a predetermined time is added. The waveform storage device stores the waveform data immediately after the operating state of the power conversion device is changed in the storage medium. 2. A central processing unit for controlling data for recording a waveform of a power conversion device, one or a plurality of storage media for recording or reproducing the waveform data, and this storage. A waveform storage device comprising one or a plurality of buffers for permitting or prohibiting data input to the medium, and switching a storage medium for recording data by a write permission signal supplied from the central processing unit. In addition to the case where a failure occurs in the power conversion device, the power conversion device is provided with a write permission signal generation means capable of changing the timing of switching the storage medium due to a phenomenon that occurs in the power conversion device. A waveform storage device that can leave waveform data showing electrical characteristics at an appropriate timing for each phenomenon that occurs.