JPH07307897A - Key signal processor for video signal processing - Google Patents

Abstract

PURPOSE:To realize a special effect of a sub-pixel level with simple circuit configuration by delaying a key input signal in the unit of one clock, selecting two signal pairs in a prescribed delay relation, interpolating the signals and compositing the signals. CONSTITUTION:First and second sets of delay key signals of a couple of arbitrary combination based on a selection control signal SELCNT are selected by a matrix circuit 20A. Signal interpolation circuits 30A, 30B implement signal interpolation based on coefficients K0, K1 as to the selected two pairs of delayed key signals. Furthermore, a signal synthesis unit 40A synthesizes key signals interpolated depending on the mode designated by a mode signal MODE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key signal processing device for video signal processing used in a digital video signal switcher for processing a key signal for imparting a special effect to a video signal. In particular, the present invention relates to a key signal processing device for video signal processing, which generates a key signal enabling a special effect of a sub-pixel level narrower than a pixel interval. More specifically, the present invention provides a video signal processing key suitable for processing a key signal that enables soft border line processing, a key signal that enables soft drop border processing, and the like. The present invention relates to a signal processing device. More specifically, the present invention relates to a key signal processing device for video signal processing capable of having an IC circuit configuration suitable for composite processing of key signals. Still more specifically, the present invention relates to a video signal processing key signal processing device for generating a key signal for defocusing a video signal.

[0002]

2. Description of the Related Art In a digital video signal switcher, various special effects are applied to a video signal. There are various special effects such as border lines, drop borders, shadows, and outlines. A key signal is used to apply such a special effect, but it is necessary to perform various processes on the key signal according to the content of the special effect.

[0003]

When a high-level special effect is applied, a special effect less than a pixel interval of a video signal, that is, a sub-pixel level special effect has been demanded. A circuit (device) having a simple circuit configuration for effectively processing a key signal for performing the above is not yet known.

Further, even if the conventional method performs signal combination of two key signals, for example, a positive NAM (non-additive mixing) operation for expanding the width of the key signals, the time between the two key signals ( If the phases are far apart,
It is equivalent to simply separating and outputting the two key signals,
The width of the key signal cannot be expanded as desired.
That is, the conventional method has a problem that if the time interval between two key signals is large, desired signal combination cannot be performed even if the positive NAM operation is performed.

Further, it becomes an extended function of the above-mentioned processing,
A key signal processing device for video signal processing suitable for processing a key signal that enables soft border processing or a key signal that enables soft drop border processing is also known. Absent.

A video signal processing key having a configuration suitable for performing the above-mentioned key signal in a complex and effective manner, for example, by applying a soft border line processing and further by performing a soft drop border processing. No signal processor is known.

Further, a special effect for smoothing the border is required, but a key signal processing device for video signal processing capable of suitably generating such a key signal has not yet been known.

Further, there is no known key signal processing device for video signal processing which provides a defocused key signal showing a smooth change.

A first object of the present invention is to provide a video signal processing key signal processing device capable of providing a key signal capable of realizing a special effect of a subpixel level of a pixel interval or less with a simple circuit configuration. It is in. The second aspect of the present invention
It is an object of the invention to provide a video signal processing key signal processing device capable of effective signal synthesis even when the time difference (phase difference) between two key signals for signal synthesis is large. Further, a third object of the present invention is to achieve the above first object and the second object.
It is an object of the present invention to provide a key signal processing device for video signal processing which simultaneously achieves the above object.

A fourth object of the present invention is to provide a key signal which enables soft border line processing or a video signal which is suitable for generating a key signal which enables soft drop border processing. It is to provide a key signal processing device for processing. A fifth object of the present invention is to provide a key signal processing device for video signal processing, which has a preferable configuration for compositely performing the above-described key signals. A sixth object of the present invention is to carry out the above-mentioned processing,
It is another object of the present invention to provide a video signal processing key signal processing device capable of generating a key signal capable of smoother edging.

A seventh object of the present invention is to provide a key signal processing device for video signal processing capable of generating a defocused key signal showing a smooth change.

[0012]

[Means and Solutions for Solving the Problems] The First
The key signal processing device for video signal processing of the present invention that achieves the third object sequentially delays a key input signal used for applying a special effect to a video signal in units of one clock, and outputs the delayed key signal. A signal delay circuit for receiving the key input signal and a plurality of delayed key signals output from the signal delay circuit, and select two pairs of signal sets each having a predetermined delay relationship based on the selection control signal. A signal selecting circuit, a first signal interpolating circuit for interpolating the first pair of signals output from the signal selecting circuit using a first coefficient, and a first signal interpolating circuit output from the signal selecting circuit. A second signal interpolating circuit that performs signal interpolation using a second coefficient for two pairs of signals, and a signal combining the output of the first signal interpolating circuit and the output of the second signal interpolating circuit. Key signal for video signal processing And outputs as having a signal combining circuit. The action signal delay circuit sequentially delays a key input signal used for applying a special effect to a video signal based on a clock corresponding to the transfer of the video signal, and outputs a plurality of delayed key signals. As a result, a plurality of delayed key signals are generated which are relieved when the phase difference in the phase adjustment and the signal combination is separated. The desired two pairs of signals are selected by the signal selection circuit. As a pair of signals of each signal set, a signal set having a time difference of one clock is preferably selected. The first signal interpolating circuit and the second signal interpolating circuit respectively interpolate the selected signal set and multiply by a coefficient. As a result, a sub-pixel level signal within the pixel interval is generated. In particular, it can be interpolated to an arbitrary value by multiplying by a coefficient. The signal synthesis circuit is the first
The signal interpolation result and the second signal interpolation result are combined. As signal combination, for example, a positive NAM operation or a negative NAM operation is performed. The key signal thus signal-synthesized is a one-dimensionally processed key signal.

A key signal processing device for video signal processing, which achieves the above-mentioned fourth object requiring three-dimensional key processing, is one horizontal synchronization of a video signal with a key input signal used for applying a special effect to the video signal. A signal delay circuit that sequentially delays by a unit of time (1H line) corresponding to a period and outputs the delayed plurality of key signals, and receives the key input signal and the plurality of delayed key signals output from the signal delay circuit , A pair of signal sets each having a predetermined delay relationship in the first direction of the video signal, for example, in the vertical direction, are selected, and those signals are selected by a predetermined number of layers in the first direction of the video signal. A first direction signal adjusting unit for adjusting the width of the signal and a result of signal adjustment performed by the first direction signal adjusting unit, and the signals are orthogonal to the first direction with respect to those signals. A second direction signal adjusting unit that adjusts the width of the image signals by a predetermined number of layers in the second direction of the image signal, for example, the abnormal direction, and a predetermined direction for the second direction signal adjusted signal. A multiplication unit that multiplies the coefficient by the number of layers for key signal processing, and a signal combination circuit that combines a plurality of multiplication results corresponding to the number of layers for key signal processing from the multiplication unit and outputs as a key signal for video signal processing. Have. The action signal delay circuit sequentially delays a key input signal used for applying a special effect to a video signal in units of 1H line, and outputs a plurality of delayed key signals. As a result, a delayed key signal is generated that relieves when there is a time difference in signal adjustment and signal synthesis. In the first direction, eg
The vertical signal adjustment unit adjusts the vertical position of the key signal in the vertical direction and the width of the key signal by the number of layers for processing the key signal. That is, the key input signal and each delayed key signal from the signal delay circuit are received, a signal set having a predetermined delayed relationship is selected based on the vertical direction selection control signal, and the vertical phase of the selected signal is selected. Is adjusted by the number of layers for key signal processing, and the width of the adjusted signal is adjusted by the number of layers for key signal processing. The signal adjusting unit in the second direction, for example, the horizontal direction, adjusts the horizontal position of the key signal, the horizontal position of the key signal, and the width of the key signal by the number of layers for processing the key signal. That is, with respect to the result of adjustment by the vertical direction signal adjustment unit, a signal group having a predetermined delayed relationship is selected based on the horizontal direction selection control signal, and a horizontal position key signal processing is performed for the selected signal. Adjust the number of layers, and adjust the width of the phase-adjusted signal by the number of layers for key signal processing. In the horizontal adjustment and the vertical adjustment, first, the vertical adjustment is performed, and then the result is adjusted in the horizontal direction, or vice versa. Alternatively, the horizontal adjustment and the vertical adjustment may be independently performed and the results may be combined. The multiplication unit performs height adjustment on the result adjusted in the horizontal direction and the vertical direction as described above. That is, the multiplication unit multiplies the vertically adjusted signal and the horizontally adjusted signal by a predetermined coefficient by the number of layers for key signal processing. The signal synthesizing circuit synthesizes a plurality of three-dimensionally adjusted key signals thus obtained. For signal synthesis,
A positive NAM operation or a negative NAM operation is performed.

A key signal processing device for video signal processing that achieves the fifth object has, as a basic circuit configuration, a selector for selecting and outputting a plurality of key input signals based on a selection control signal, and an output from the selector. A plurality of key signal transforming circuits for receiving the key signals to be transformed and transforming the waveforms of the key signals, wherein each of the key signal transforming circuits converts the key input signal output from the selector to one of the video signals.
A signal delay circuit that sequentially delays by a time unit corresponding to a horizontal synchronization period (1H line) and outputs the delayed plurality of key signals, a key input signal output from the selector, and the signal delay circuit. A plurality of delay key signals are received, a pair of signal sets each having a predetermined delay relationship in the first direction of the video signal are selected, and a selected number of layers are selected in a predetermined direction in the first direction of the video signal. A first direction signal adjusting unit that adjusts the width of the signal, and a result of the signal adjustment performed by the first direction signal adjusting unit, and a video signal that is orthogonal to the first direction with respect to those signals. A second direction signal adjusting unit for adjusting the widths of those signals by a predetermined number of layers in the second direction, and each of the plurality of outputs of the plurality of key signal transforming circuits is provided. It has a plurality of multiplication circuits for multiplying a predetermined coefficient, and a first signal combining circuit for signal combining a plurality of multiplication results of the multiplication circuit. Preferably, a first delay circuit for receiving the signal processing key signal of the video signal processing key signal processing device in the preceding stage and delaying it by the operation time required by the key signal modification circuit and the multiplication circuit, and the selector. A second delay circuit for delaying a selected key signal by an operation time required by the key signal modification circuit and the multiplication circuit, and an output of the first delay circuit or an output of the second delay circuit to select the second delay circuit. A switching circuit applied to the second signal combining circuit and the result of the first signal combining circuit;
It further comprises a second signal synthesizing circuit which synthesizes a signal with either the output of the first delay circuit or the output of the second delay circuit selected by the switching circuit.

A key signal processing device for video signal processing that achieves a further preferable fifth object is a key signal processing device for video signal processing, wherein the above-mentioned key signal processing device for video signal processing is set as one set. Connect in cascade. That is, in the video signal processing key signal processing device of the present invention, the first line delay circuit means, the first signal adjustment circuit means, the first line delay circuit means, and the first signal adjustment are provided. A plurality of delay circuits for receiving the outputs of a plurality of key signal modification circuits of the preceding video signal processing key signal processing device having circuit means and sequentially delaying the time corresponding to one line of the video signal. Second line delay circuit means having a circuit configuration equivalent to that of the line delay circuit means, a plurality of delay key signals delayed by the second line delay circuit means, and the video signal processing key signal processing. The first signal, which receives the output of the first signal combining circuit of the device as a signal processing key signal of the key signal processing device for video signal processing in the preceding stage and performs the second signal adjustment on these key signals And a second signal conditioning circuit means having an equivalent circuit configuration as integer circuit means. By integrally constituting a first signal conditioning circuit means effects a second signal adjusting circuit means as an IC, respectively, the only possible cascaded required number of IC. Preferably, the result of signal synthesis in the signal adjusting circuit means of the previous stage is used for signal synthesis of the next stage.

In order to achieve the above-mentioned sixth object, a two-line delay circuit delaying the output of the second signal combining circuit of the first signal adjusting circuit means by two lines, and the first signal. The output of the second signal synthesizing circuit of the adjusting circuit means or the output of the two-line delay circuit is switched and the second
And a switching circuit for applying as a key signal of the key signal processing device for video signal processing in the preceding stage to the signal adjusting circuit means.

A key signal processing device for video signal processing (key signal defocusing device) that achieves the seventh object is such that a key input signal used for applying a special effect for defocusing a video signal A signal delay circuit that sequentially delays based on a clock corresponding to transfer and outputs a plurality of delayed key signals, and a selection control signal that receives the key input signal and a plurality of delayed key signals output from the signal delay circuit. A signal selection circuit for selecting a plurality of pairs of signal groups having a predetermined delayed relationship based on the above, and position adjustment in the first direction of the video signal for the selected plurality of pairs of signals, The first direction signal adjusting unit for adjusting the width, and the second direction of the video signal orthogonal to the first direction with respect to the result of the plurality of pairs adjusted by the first direction signal adjusting unit. A second direction signal adjusting unit for adjusting a position and adjusting a width of the adjusted signal; a multiplying unit for multiplying a result of the second direction adjusted pairs of sets by a predetermined coefficient; and a multiplying unit. And a signal synthesizing circuit for synthesizing the signal of the multiplication result of. The signal combining circuit is preferably a positive NAM operation and a negative NAM.
It has a circuit for performing calculations, and these calculations are performed based on the mode signal.

【Example】

First Embodiment A first embodiment of the video signal processing key signal processing apparatus of the present invention will be described with reference to FIG. The video signal processing key signal processing apparatus of the first embodiment is a signal processing apparatus that performs one-dimensional adjustment (time width adjustment) for one key signal. The key signal processing device for video signal processing illustrated in FIG. 1 includes a key signal delay circuit 10A and a matrix circuit (signal selection circuit) 20.
A, first signal interpolation circuit 30A, second signal interpolation circuit 3
0B and a signal synthesis circuit 40A.

FIG. 2 is a block diagram of a key signal adjusting circuit for performing the most basic processing for processing one type of key signal. The key signal adjustment circuit shown in FIG. 2 corresponds to the key signal delay circuit 10A shown in FIG. 1 and the key signal delay circuit 10 shown in a simplified configuration is shown, and the matrix signal selection circuit 20A shown in FIG. The signal selection circuit 20 corresponding to the above and the configuration thereof is simplified, and the first signal interpolation circuit 30A and the second signal interpolation circuit 30B shown in FIG. The signal interpolation circuit 30 shown in FIG. From the above, the video signal processing key signal processing device shown in FIG. 1 has a circuit configuration in which the key signal adjusting circuit of FIG. 2 showing the basic circuit configuration and the signal synthesizing circuit 40A are combined.

The basics of the time width adjusting operation of the key signal will be described with reference to the key signal adjusting circuit shown in FIG. A key input signal KEYIN which is a binary signal of white / black (or 0/1) is input to the key signal adjusting circuit.

The key signal delay circuit 10 has unit clock delay circuits 11 to 15, and these unit clock delay circuits 11 to 15 send the key input signal KEYIN to the clock CLK.
Based on the delay. The value of 1 clock CLK corresponds to the time for transferring the data for 1 pixel of the video signal to be subjected to the special effect using the key signal. Therefore, the key input signal KEYIN input to the key signal delay circuit 10 is sequentially delayed in the unit clock delay circuits 11 to 15 with a delay time corresponding to the video signal at 1-pixel intervals. Key signal delay circuit 10 shown in FIG.
A has a circuit configuration corresponding to the key signal delay circuit 10 shown in FIG. 2, and sequentially outputs the key input signal KEYIN by 1
N delay circuits D0 to Dn- which are delayed by the clock CLK
1 is cascaded.

The signal selection circuit 20 shown in FIG. 2 receives the key input signal KEYIN itself and the key input signal sequentially delayed by one clock unit in the key signal delay circuit 10, and optionally selects it based on the selection control signal SELCNT. The key input signal and the delay key signal having the delay relationship of 1 or the pair of the delay key signal having the arbitrary delay relationship are selected and output from the output terminals O0 and O1. In this embodiment, preferably, a pair of key signals delayed by one clock are output from the output terminals O0 and O1. When two signals separated by one clock are selected, there is no large difference in the time difference between the two signals to be interpolated in the signal interpolation circuit 30, and for example, non-additive mixing (N-additive mixing: N
A key signal is provided which is useful in subsequent arithmetic processing such as AM). Hereinafter, in the present embodiment, a case will be described in which a pair of key signals having a delay relationship of one clock is selected and output. Of course, the signal selection circuit 20 can select a pair of key signals having an arbitrary delay relationship according to the instruction of the selection control signal SELCNT. The matrix circuit 20A shown in FIG. 1 is similar to the signal selection circuit 20 shown in FIG. Output a set of selection signals. The first pair of selection signals are output terminals OUT1, OU
The signal is output from T2 and applied to the first signal interpolation circuit 30A. The second pair of selection signals are output terminals OUT2 and O2.
It is output from the UT3 and applied to the second signal interpolation circuit 30B. In this embodiment, the output terminal OUT
The two delayed key signals output from 0 and OUT1 are shifted by one clock CLK. That is, the pair of selection signals of the first set, that is, the first selection signal and the second selection signal of the first set are arbitrary delayed key signals separated by one clock. Similarly, output terminals OUT2, OUT3
The two key signals output from are shifted by one clock CLK. That is, the second pair of selection signals,
That is, the first selection signal and the second selection signal of the second set are arbitrary key signals separated by one clock.

The signal interpolation circuit 30 shown in FIG. 2 inputs a pair of key signals selected and output by the signal selection circuit 20,
Interpolation processing of the two key signals is performed. FIG. 3 (A)-
The operation of the signal interpolation circuit 30 will be described with reference to FIG.
FIG. 3A is a graph showing the time change of the first key signal output from the signal selection circuit 20 in the key signal adjustment circuit of FIG. 2, and FIG. 3B is the output from the signal selection circuit 20. 3C is a graph showing the change over time of the second key signal, and FIG. 3C is a graph showing the interpolation result of the signal interpolation circuit 30. In FIGS. 3A to 3C, one scale on the horizontal axis corresponds to the time of one clock CLK. The second key signal INB is delayed by one clock CLK with respect to the first key signal INA. This delay relationship is based on the key input signal KEYIN and the output of the unit clock delay circuit 11 of the key signal delay circuit 10 or the unit clock delay circuit 11
Any signal may be used as long as it is delayed by one clock CLK, such as signals before and after. The selection is defined by the selection control signal SELCTL applied to the signal selection circuit 20. The signal interpolation circuit 30 performs a signal interpolation calculation based on the following equation.

[0024]

## EQU1 ## OUT30 = K.times.INA + (1-K) .times.INB (1) where K is an interpolation coefficient with a value of 0 to 1, INA is the first key signal, and INB is the second Is the key signal of
OUT30 is the interpolation result.

FIG. 3C is a graph showing the interpolation result OUT30 of the signal interpolation circuit 30 when the coefficient K = 0.5. The graph illustrated in FIG. 3C shows the waveform of the key signal obtained by averaging the first key signal INA and the second key signal INB when the coefficient K = 0.5. As a result, the first key signal INA and the second key signal INB
Both are signals delayed by 1 clock CLK unit, but a value within 1 clock CLK can be obtained by interpolation. Since one clock corresponds to one pixel interval, it means that a key signal within one pixel interval, that is, a subpixel level is obtained by interpolation. That is, the signal interpolation result OUT30 includes the first key signal INA having a pixel interval and the second key signal I having a pixel interval.
It means a sub-pixel level interpolation key signal obtained by using NB. In other words, the signal interpolation result OUT
Reference numeral 30 denotes the result of signal adjustment of the key input signal KEYIN having the pixel interval to the sub-pixel level. Since the coefficient K can be set appropriately, the signal adjustment amount can be adjusted by setting the coefficient K appropriately. As described above, the interpolation result OUT30 is not 1 for each clock CLK but 1
Since the time is adjusted to be less than the clock CLK, the use of the interpolation result OUT30 enables special effect processing at a sub-pixel level of 1 pixel or less, instead of special effect processing for each pixel as in the conventional case. How the signal is adjusted with respect to the key input signal KEYIN is defined by the coefficient K and the pair of key signals selected by the signal selection circuit 20. In other words, the signal adjustment amount can be defined by the coefficient K and the selection control signal SELCTL.

The first signal interpolation circuit 30A shown in FIG.
Performs the interpolation calculation on the first selection signal and the second selection signal of the first set using the coefficient K0 with K = K0 in Expression 1. As a result, the first signal interpolation circuit 30A performs the first signal adjustment using the first set of the first selection signal and the second selection signal. The second signal interpolating circuit 30B shown in FIG. 1 uses K = K0 in Expression 1 for the first selection signal and the second selection signal of the second set using the coefficient K1.
The interpolation calculation is performed. As a result, the second signal interpolation circuit 30B performs the second signal adjustment using the second set of the first selection signal and the second selection signal.

In the signal combining unit 40A shown in FIG. 1, the first signal interpolating circuit 30A first adjusts the first key signal INA and the second signal interpolating circuit 30.
The second adjusted second key signal INB is applied from B, and the delayed key signal delayed by one clock is applied from the key signal delay circuit 10A.

FIG. 4 shows the signal combining unit 4 shown in FIG.
0A compatible signal synthesizing circuit 4 with a simplified configuration
It is a circuit diagram of 0. The signal combination circuit 40 receives the first key signal INA and the second key signal INB, performs signal combination based on the type of the mode signal MODE, and outputs a combination result OUT40. Here, Table 1 shows an example of the type of the mode signal MODE and its processing content in the present embodiment.

[0029]

[Table 1] Table 1 Mode type Mode name Mode processing contents Mode 0 Positive NAM operation Selectively outputs the higher level of the first key signal INA and the second key signal INB. Mode 1 Negative NAM operation The one with the lower level of the first key signal INA and the second key signal INB is selectively output. Mode 2 First input selection output Selects and outputs the first key signal INA. Mode 3 Second input selection output Selectively outputs the second key signal INB. Note: NAM means Non-Additive Mixing.

FIG. 5 is a graph showing the operation of the signal synthesizing circuit 40 shown in FIG. 4, and FIG. 5 (A) shows the signal synthesizing circuit 40.
FIG. 5B is a graph showing the time change of the first key signal input to the second key input signal, and FIG.
6 is a graph showing the time change of the key signal of FIG.
Is a signal combining circuit 40 based on the first mode (mode 0)
5D is a graph showing the result of combining, and FIG. 5D is a graph showing the result of combining the signal combining circuit 40 based on the second mode (mode 1). The first key signal IN shown in FIG.
Using A and the second key signal INB shown in FIG.
In the signal synthesis circuit 40, mode 0 (positive NAM
If the signal synthesis of (computation) is performed, the width of the synthesis result OUT40 becomes wider as illustrated in FIG. In addition, if the signal synthesis of mode 1 (negative NAM operation) is performed,
As illustrated in FIG. 5D, the synthesis result OUT40
Becomes narrower. That is, using the signal synthesis circuit 40,
The width of the key signal can be widened by performing the signal synthesis of mode 0, and the width of the key signal can be narrowed by performing the signal synthesis of mode 1 (negative NAM operation). Therefore, by using the key signal synthesized in mode 0, the border line processing, that is, the width of the video signal can be thickened (widened). On the contrary, if the key signal synthesized in mode 1 is used, the width of the video signal can be narrowed.

FIG. 6 is a graph showing another operation of the signal combining circuit 40 shown in FIG. 4, and FIG. 6A is a graph showing the time change of the first key signal input to the signal combining circuit 40. 6B is a graph showing the change over time of the second key signal input to the signal combining circuit 40, and FIG.
(C) is a graph showing a synthesis result of the signal synthesis circuit 40 based on the first mode (mode 0: positive NAM operation). First key signal IN shown in FIGS. 6A and 6B
There is a time difference between A and the second key signal INB. As a result, the mode 0 (positive NA
When the signal synthesis by M calculation) is performed, the first key signal IN
A signal combination for expanding the width of the signal between A and the second key signal INB is not performed, and the combined result OUT40 is a discontinuous signal obtained by simply outputting the first key signal INA and the second key signal INB. It becomes the key signal of the state. Such discontinuous key signals cannot be effectively used for special effect processing.

In order to prevent such a problem of signal combination in the mode 0 (positive NAM operation) for the first key signal INA and the second key signal INB having a large time difference between the two signals, the signal of the signal combining circuit 40 is used. Also in the synthesis, as described with reference to FIGS. 1 and 2,
It is desirable to use a key signal obtained by delaying the key input signal KEYIN every clock CLK. Therefore, the delayed key signal from the key signal delay circuit 10A shown in FIG. 1 is applied to the signal synthesis unit 40A shown in FIG. 7A to 7F are graphs showing signal synthesis in the key signal delay circuit 10A shown in FIG. That is, FIG. 7 is a graph showing a signal combining operation in the first mode for expanding the time width of the key signal.
FIG. 7A is a graph showing the change over time of the first key signal INA-1, that is, the key input signal KEYIN.
(B) to (D) are the first sequentially delayed by the unit clock.
5 is a graph showing the time change of the key signals INA-2 to INA-4. FIG. 7E is a graph showing the time change of the second key signal INB. FIG. 7 (F) is based on the first mode, and the first key signals INA-1 to INA-4 illustrated in FIGS. 7 (A) to (D) and the second key signals INA-1 to INA-4 illustrated in FIG. 7 (E).
7 is a graph showing the result of signal combination with the key signal INB of FIG.
In this way, by combining the first key signal INA delayed by one clock CLK and the second key signal INB,
Even if there is a time difference as illustrated in FIGS. 6A and 6B between the first key signal INA and the second key signal INB, the time width of the key signal does not become discontinuous, The key signal can be generated as a continuous wide signal.

FIG. 8 shows the signal combining unit 4 illustrated in FIG.
It is a circuit block diagram of 0A. The signal combining unit 40A is
The signal synthesis circuits 401 to 407 are connected as shown in the figure.
There is. Operations of the respective signal synthesis circuits 401 to 407
Is similar to the signal combining circuit 40 illustrated with reference to FIG.
is there. The first signal synthesis circuit 401 is a key signal delay circuit.
10A second stage delay circuit D ₁Input key signal IN1 of
Second stage delay circuit D₁Output key signal IN2 (of the third stage
Delay circuit D₂Input key signal IN2)
U The signal synthesis in this embodiment spans the width of two signals.
Widening mode 0 (Positive NAM operation) signal synthesis
is there. The other signal synthesizing circuits 402 to 403 are also used for signal combination.
Mode 0 (positive NAM performance)
Signal synthesis of two delayed key signals that are shifted by one clock
I do. The signal synthesis unit 40A includes a signal synthesis circuit 40.
6, basically from the first signal interpolation circuit 30A
The first signal adjusted first key signal INA and the second key signal INA
The second signal adjusted second signal from the signal interpolation circuit 30B.
Signal is synthesized with the INB signal.
As indicated by the solid line, the delay key signal from the key signal delay circuit 10A is received.
Therefore, the first signal interpolation circuit 30
The first key signal INA and the first signal adjusted from A
Second signal interpolating circuit 30B from the second signal adjusted second
Refer to FIGS. 6 (A) and 6 (B) for the key signal INB of
Key input signal even if there is a large time difference
The width of KEYIN can be expanded. Signal synthesis unit
40A is a mode 0 (positive NA
Not only the M operation) but the circuits for performing other operations shown in Table 1
And has shown in Table 1 according to the mode signal MODE.
Calculations in various modes can be performed.

As described above, when the key signal processing device for video signal processing according to the first embodiment of the present invention illustrated in FIG. 1 is used, the selection control signal SE in the matrix circuit 20A is used.
Select the first and second sets of delayed key signals of any pair of combinations based on LCNT, and select the first signal interpolation circuit 3
0A and the second pair of delayed key signals selected in the second signal interpolation circuit 30B, the coefficient K0
It is possible to perform signal interpolation based on the coefficient K1 and the coefficient K1, and to synthesize the key signal interpolated according to the mode designated by the mode signal MODE in the signal synthesis unit 40A.

The implementation of the key signal processing apparatus for video signal processing according to the first embodiment of the present invention is not limited to the above-described example, but various modifications can be made. For example, in the matrix circuit 20A shown in FIG. 1 or the signal selection circuit 20 shown in FIG. 2, the case where only one pair of key signals that are delayed by one clock is selectively output has been described. In addition to the selection of a pair of key signals, the value of the selection control signal SELCNT may be arbitrarily set to selectively output key signals separated by an arbitrary time, for example, in a two-clock delay relationship. In addition, the key signal delay circuit 10A of FIG. 1 or the key signal delay circuit 10 of FIG.
Describes the case where the unit delay circuits (elements) are cascade-connected, but the key signal delay circuit 10 and the key signal delay circuit 10A are configured by using, for example, one RAM, and the key input signal is input to the RAM. Write continuously,
Even when reading is performed according to the read clock, the delayed key signal delayed by one clock is provided.

According to the video signal processing key signal processing apparatus of the first embodiment of the present invention, the key signal can be adjusted at the sub-pixel level smaller than the pixel interval. According to the first embodiment of the present invention, even if there is a considerable time difference between the two key signals, the width of the key input signal is made continuous,
It can be adjusted without problems according to the set mode. Further, according to the first embodiment of the present invention, the two signals adjusted at the sub-pixel level as described above can be combined in a desired mode.

The described video signal processing key signal processing apparatus according to the second embodiment of the second embodiment the present invention. FIG. 9 is a graph illustrating the borderline processing with software. Image processing for developing such an original video signal in a three-dimensional pyramid shape requires creating a key signal having a three-dimensional size. FIG. 10 is a graph illustrating the soft drop border processing. The original video signal like this
For image processing that is dimensionally continuous and changes in size, it is necessary to create a key signal having a three-dimensional size. As shown in FIGS. 9 and 10, in order to perform the soft border line processing or the soft drop border processing, the key signal processing of the first embodiment for performing the one-dimensional signal adjustment described above is sufficient. However, it is necessary to extend the processing of the key signal to two-dimensional signal adjustment, and further to three-dimensional signal adjustment.

FIG. 11 shows a second embodiment of the present invention for generating a key signal which enables the soft border line processing shown in FIG. 9 and the soft drop border processing shown in FIG. It is a block diagram of a key signal processing device for video signal processing. The key signal processing device for video signal processing illustrated in FIG. 11 includes a key signal delay circuit 100, a signal transmission bus 200, a vertical (vertical) direction signal adjusting unit 300 as a first direction signal adjusting unit, and a second direction signal adjusting unit. (Horizontal) direction signal adjustment unit 4 as
00, multiplication unit 500, and signal combining circuit 60
Has 0. An outline of the operation of this video signal processing key signal processing device will be described. The key signal delay circuit 100 delays the key input signal KEYIN used for signal adjustment and signal combination. The key input signal KEYIN and the delayed key signal are applied to the vertical (vertical) direction signal adjusting unit 300 via the signal transmission bus 200, the signal is adjusted in the vertical direction, and the signal is combined to expand its width. The output of the vertical direction signal adjustment unit 300 is the horizontal direction.
When applied to the direction signal adjustment unit 400, the horizontal (horizontal)
In the direction signal adjusting unit 400, the signal is adjusted in the horizontal direction, and the signals are combined to expand the width.
The key signals thus adjusted in the vertical direction and the horizontal direction are used as coefficients HK1 to H in the multiplication unit 500.
K8 is multiplied and the size in the height direction is adjusted. In the signal synthesizing circuit 600, the key signals thus adjusted are synthesized based on the mode signal MODE.

The key signal processing device for video signal processing of the second embodiment will be described in detail. Each of the key signal delay circuits 100 delays the key signal by 1H (a time corresponding to one horizontal synchronizing period of a video signal).
104, the vertical (vertical) direction signal adjustment unit 300 includes eight series of vertical direction signal adjustment circuits 301 to 303, and the horizontal (horizontal) direction.
The direction signal adjustment unit 400 also has eight series of horizontal direction signal adjustment circuits 401 to 403, and the multiplication unit 500 also has eight series of multiplication circuits 501 to 503. The number of stages of the 1H line delay circuits 101 to 104 is defined according to the adjustment amount of the video signal for key signal processing and the number of video signals. The vertical (vertical) direction signal adjustment unit 300, the horizontal (horizontal) direction signal adjustment unit 400, and the multiplication unit 500 are
In this embodiment, each has eight series of circuits. In the case of the borderline processing with software shown in FIG. 9, for example, 8 series corresponds to the height. In the case of the soft-applied drop border shown in FIG. 10, this corresponds to the continuous number.

The key signal delay circuit 100 sequentially delays the key input signal KEYIN every 1H line for 1H.
The line delay circuits 101 to 104 are connected in cascade. As the 1H line delay circuits 101 to 104, for example, a frame memory used for video signal processing can be used. When the key input signal KEYIN is written in the frame memory and read out, 1H
It becomes a delayed key signal. In the key signal delay circuit 10A in the key signal processing device for video signal processing of the first embodiment and the key signal delay circuit 10 as the basic circuit shown in FIG. 2, the pixels corresponding to the clock with respect to the key input signal. Although the unit delay is performed, in the present embodiment, the key input signal KEYIN is delayed for the 1H line for signal processing in order to generate the key signal applicable to the image processing having the spread. Of course, the reference of the delay of the 1H line is the clock CLK. The delay key signal output from the central 1H line delay circuit 102 is vertical (vertical).
It serves as a timing reference signal for signal processing in the direction signal adjustment unit 300, the horizontal (horizontal) direction signal adjustment unit 400, and the like. That is, the central 1H line delay circuit 1
A vertical (vertical) direction signal adjustment unit 300, a horizontal (horizontal) direction signal adjustment unit 400, and the like perform signal processing before and after the delayed key signal output from No. 02.

The signal transmission bus 200 uses the key input signal KE.
The delayed key signal delayed by YIN and the key signal delay circuit 100 is applied to the vertical (vertical) direction signal adjustment unit 300.

Vertical (vertical) direction signal conditioning unit 300
Is a key input signal KEYIN and a key signal delay circuit 1
The delayed key signal delayed at 00 is input to adjust the magnitude of the input key signal in the vertical direction. In this embodiment, the vertical (vertical) signal adjusting unit 300 includes eight vertical signal adjusting circuits 30 arranged in parallel.
1 to 303, and these circuits 301 to 303 have the same circuit configuration. Eight vertical signal conditioning circuits 30
Each of 1 to 303 is a matrix circuit 2 in the key signal processing device for the first video signal processing described with reference to FIG.
0A, the first signal interpolation circuit 30A and the second signal interpolation circuit 30B, and a circuit corresponding to the signal synthesis unit 40A. However, in the second embodiment, since the key signal is delayed by the key signal delay circuit 100, the key signal delay circuit 10A for each clock shown in FIG. 1 is unnecessary. The signal selection, signal interpolation, and signal combination processing in the second embodiment are basically the same as those of the video signal processing key signal processing apparatus described with reference to FIG. However, the vertical (vertical) direction signal adjustment unit 30
At 0, signal processing is performed in the vertical direction.

Horizontal (horizontal) direction signal conditioning unit 400
Also, in the second embodiment, eight horizontal direction signal adjusting circuits 401 to 403 are provided in parallel, and these circuits 401 to 403 have the same circuit configuration. Each of the eight horizontal signal adjusting circuits 401 to 403 is shown in FIG.
The matrix circuit 20A and the first signal interpolation circuit 30A in the video signal processing key signal processing device described with reference to FIG.
And a circuit corresponding to the second signal interpolating circuit 30B and the signal synthesizing unit 40A. However, in the second embodiment, since the key signal delay circuit 100 delays the key signal by 1H, the key signal delay circuit 10A shown in FIG. 1 that delays by 1 clock is not necessary. The signal selection, signal interpolation, and signal combination processing in the second embodiment are basically the same as those of the video signal processing key signal processing apparatus described with reference to FIG. However, in the horizontal (horizontal) direction signal adjustment unit 400, signal processing is performed in the horizontal direction.

The multiplying unit 500 has, in this embodiment, eight series of multiplying circuits 501 to 503,
Vertical (vertical) direction signal adjustment unit 300 for vertical signal adjustment, horizontal (horizontal) direction signal adjustment unit 400
The signal adjustment in the height direction is performed on the result of the signal adjustment in the horizontal direction in. The signal adjustment is to multiply by the coefficients HK1 to HK8. Therefore, the multiplication circuits 501 to 503 add the coefficient HK1 to the result of the horizontal direction signal adjustment circuits 401 to 403.
~ Take the HK8. The multiplication coefficients HK1 to HK8 are set by the operator in the same manner as the selection control signal SELCNT and the mode signal MODE.

The signal synthesizing circuit 600 synthesizes the above-mentioned three-dimensionally signal-adjusted key signal. Mode 0, that is, a positive NAM operation is generally used as the content of the signal synthesis, but depending on the purpose of use of the key signal,
Negative NAM calculation and other signal combining shown in Table 1 can be performed. The designation is made by the mode signal MODE set by the operator.

As described above, if the key signal processed by the video signal processing key signal processing device of the second embodiment is used, the border line processing in which the software shown in FIG. 9 is applied to the video signal, or It is possible to perform the drop border processing with the software shown in FIG.

The implementation of the key signal processing device for video signal processing according to the second embodiment of the present invention is not limited to the circuit configuration illustrated in FIG. 11, but various configurations are possible. For example, the positions of the vertical (vertical) direction signal adjustment unit 300 and the horizontal (horizontal) direction signal adjustment unit 400 may be reversed. Alternatively, the vertical direction signal adjustment unit 300
It is also possible to independently perform the processing of (1) and the processing of the horizontal (horizontal) direction signal adjustment unit 400 and combine the results.

According to the video signal processing key signal processing apparatus of the second embodiment of the present invention, the key signal can be adjusted at the sub-pixel level as in the first embodiment. Further, according to the second embodiment of the present invention, like the first embodiment, even if the two signals are considerably separated in time, the width of the key signal is made continuous and the mode signal is adjusted according to the mode without any problem. it can. Further, according to the second embodiment of the present invention, as in the first embodiment, two signals obtained by adjusting the key signal at the sub-pixel level can be combined in any mode.

In addition, according to the second embodiment of the present invention, it is possible to generate a key signal suitable for soft border line processing or soft drop border processing. Furthermore, when the key signal processing device for video signal processing of the present invention is used as a bandpass filter which is effective in both the vertical and horizontal directions of the key signal, the filter performance is improved.

Third Embodiment As a third embodiment of the present invention, the generation of a key signal that enables soft border line processing or a key signal that enables soft drop border processing is combined. The key signal processing device for video signal processing of the present invention, which is efficiently performed, will be described. FIG. 12 is a block diagram of a key signal processing device for video signal processing according to a third embodiment of the present invention. This video signal processing key signal processing device includes a selector 110, a key signal modification unit 130 including a plurality of key signal modification circuits 131 to 134, and a plurality of multipliers 141 to 141.
It has a multiplication unit 140 composed of 144, a first signal composition circuit 150, a second signal composition circuit 170, a timing adjustment circuit 120 composed of a first delay circuit 121 and a second delay circuit 122, and a switching circuit 160. The video signal processing key signal processing device shown in FIG. 12 is realized by using the circuits constituting the video signal processing key signal processing device of the above-described first and second embodiments.

The video signal processing key signal processing apparatus shown in FIG. 12 is configured to perform signal processing on five key signals KIN0 to KIN4. These key signals KIN0
KIN4 is applied to the selector 110, and the matrix circuit 20A shown in FIG. 1 or the signal selection circuit 2 shown in FIG.
Similar to 0, a plurality of arbitrary pairs of signals selected based on the selection control signal SELCNT are selected. The pair of key signals selected by the selector 110 are applied to the key signal modification circuits 131 to 134. Key signal transformation circuit 1
The signal delay circuits shown in FIGS. 1 and 2 are provided in each of 31 to 134, and the signal adjustment shown in FIG. 11 is performed on the key signals delayed by these signals. Each of the key signal transformation circuits 131 to 134 has a circuit configuration in which the vertical (vertical) direction signal adjustment unit 300 and the horizontal (horizontal) direction signal adjustment unit 400 of the video signal processing key signal processing device shown in FIG. 11 are incorporated. Has become. That is,
In each of the key signal transformation circuits 131 to 134, signal adjustment in the vertical direction is performed, and a horizontal signal is obtained as a result. Alternatively, the key signal transformation circuit 13
In each of the circuits 1-134, signal adjustment in the horizontal direction is performed, and a signal in the vertical direction is performed for the result.
In the multipliers 141 to 144, the key signal transforming circuits 131 to 13 are similar to the multiplier unit 500 shown in FIG.
The key signal adjusted in step 4 is multiplied by a coefficient to adjust the signal in the height direction. With respect to the result, in the first signal synthesis circuit 150, similarly to the signal synthesis circuit 600 shown in FIG. 11, signal synthesis is performed based on the first mode signal MODEA, that is, positive NAM operation is performed in this example.

In the video signal processing key signal processing apparatus shown in FIG. 12, a combined input signal CMVI input to the first delay circuit 121 in the second signal synthesizing circuit 170 is further added.
N and the output of the first signal synthesis circuit 150, or any one of the key signals KIN0 to KIN4 selected by the selector 110, the output of the first signal synthesis circuit 150, and the signal synthesis based on the second mode signal MODEB. I do. The signal synthesis in the second signal synthesis circuit 170 is, for example, a positive NAM operation in this example. In this signal combination, the switching circuit 160 is used to select one of the combination input signal CMVIN input to the first delay circuit 121 and the key signals KIN0 to KIN4 selected by the selector 110. In the case of the first stage of the cascade circuit configuration, the switching circuit 160 applies one of the key signals KIN0 to KIN4 selected by the selector 110 to the second signal synthesis circuit 170. In addition, in the case of two stages or more in the cascade circuit configuration, the switching circuit 1
60 applies the combined input signal CMVIN to the second signal combining circuit 170. That is, in the case of the first stage of the cascade circuit configuration, the key signal from the selector 110 and the result from the first signal synthesis circuit 150 are the second signal synthesis circuit 170.
In the second and subsequent stages of the cascade circuit configuration, the combined input signal CMVIN and the first signal combining circuit 15 are combined.
The result from 0 is subjected to signal synthesis in the second signal synthesis circuit 170. The first delay circuit 121 is a circuit for adjusting the timing of the combined input signal CMVIN and the result of signal processing output from the selector 110 by the key signal modification unit 130, the multiplication unit 140, and the first signal synthesis circuit 150. Is. Similarly, the second delay circuit 122 receives the key signal KIN selected by the selector 110.
This is a circuit for adjusting the timing of any one of 0 to KIN4 and the result of signal processing output from the selector 110 by the key signal modification unit 130, the multiplication unit 140, and the first signal synthesis circuit 150.

The signal combining result of the second signal combining circuit 170, that is, the combined output signal CMVOUT, is used as the key signal which has been subjected to the signal processing as it is, or in order to perform the composite processing shown in FIG. Is applied to the key signal processing device. Further, the output of the key signal modification circuit 134 is output as the cascade output CASOUT for the processing of the next stage. Detailed operations of the video signal processing key signal processing device of the third embodiment will be described later together with the video signal processing key signal processing device of the fourth embodiment.

[0054] The video signal processing key signal processing apparatus of a fourth embodiment of the fourth embodiment the present invention described with reference to FIG. 13. FIG. 13 is a block diagram of a video signal processing key signal processing device, which is an extension of the video signal processing key signal processing device shown in FIG. 12, as a fourth embodiment of the present invention. The video signal processing key signal processing device shown in FIG. 13 comprises the video signal processing key signal processing device shown in FIG. 12 as one integrated circuit (IC), which can be cascade-connected by a required number of stages. It was done. The video signal processing key signal processing apparatus shown in FIG. 13 includes a first signal delay unit 210 including 1-line delay circuits 211 to 214 that delays by a time corresponding to a time required for scanning one line of a video signal. Key signal processing IC 220 for video signal processing, which uses the shown key signal processing device for video signal processing as an IC, two-line delay circuit 230 for delaying by a time corresponding to the time for scanning two lines of the video signal, switching circuit 240, and each video signal 1-line delay circuit 251-delayed by a time corresponding to the time for scanning 1 line
A second signal delay unit 250 composed of 254 and a second video signal processing key signal processing IC 260 equivalent to the video signal processing key signal processing IC 220. The basic operations of the first video signal processing key signal processing IC 220 and the second video signal processing key signal processing IC 260 have been described with reference to FIG. The first video signal processing key signal processing IC 220 includes the combination input signal CM of the preceding stage.
Since VIN is not input, the key signal output from the selector 110 in the switching circuit 160 shown in FIG. 12 is applied to the second signal synthesizing circuit 170, but the second video signal processing key signal processing IC 260 includes Combination output signal C of key signal processing IC 220 for video signal processing of No. 1
MVOUT is the second video signal processing key signal processing IC 2
Since 60 combination input signals CMVIN are applied,
This combined input signal CMVIN is applied to the second signal combining circuit 17
Used for signal synthesis at 0. The basic functions of the first signal delay unit 210 and the second signal delay unit 250 are similar to those of the 1H line delay circuit 100 shown in FIG. The switching circuit 240 uses the combined output signal CMVOUT of the first video signal processing key signal processing IC 220.
To directly select the second key signal processing IC for video signal processing
Output as 260 combination input signal CMVIN or 2
It is switched whether to apply the result of timing adjustment in the line delay circuit 230 as the combination input signal CMVIN of the first video signal processing key signal processing IC 220.

As illustrated in FIG. 13, a first signal delay unit 210 and a first video signal processing key signal processing IC 220 are set as one set, and a next stage is provided via a switching circuit 240 and a two-line delay circuit 230. That is, the second signal delay unit 250 and the second video signal processing key signal processing IC 260 can be appropriately connected in cascade to perform the key signal composite processing as needed. The 2-line delay circuit 230 is a circuit for performing smooth edging, as described later.

Explanation of Operation of Third and Fourth Embodiments Key signal processing device for video signal processing of the third embodiment shown in FIG. 12 and video signal processing of the fourth embodiment shown in FIG. A specific operation of the key signal processing device will be described. Figure 1
Reference numeral 4 is a basic key input signal KEYI to be processed.
It is the figure which illustrated N three-dimensionally (perspectively). The key input signal KEYIN is v0 in the vertical direction and h in the horizontal direction.
0 and height (level) l (ell) 0 are represented as a uniform rectangular parallelepiped. Key input signal KEYIN shown in FIG.
Is applied to the first signal delay unit 210 of the key signal processing device for video signal processing shown in FIG. 13, the origin (reference time) is sequentially applied as shown in FIGS.
It is delayed by 1H with respect to 0.

These delayed key signals KIN0 to KI
N4 is applied to the first video signal processing key signal processing IC 220 shown in FIG. The first video signal processing key signal processing IC 220 is equivalent to the video signal processing key signal processing device of FIG. 12, and the key signals KIN0 to KIN4 from the first signal delay unit 210 are the selectors of FIG. 110 is applied to the key signal transformation unit 13
At 0, the signal is adjusted vertically and horizontally. Here, as an example, an example in which the key signal is shaded will be described. 16A to 16D are graphs showing the results of the key signal modification circuits 131 to 134, respectively. The key signal modification circuits 131 to 134 are sequentially shifted by 1H in the vertical direction and 2 clocks in the horizontal direction.

The multipliers 141 to 144 shown in FIG. 12 in the first video signal processing key signal processing IC 220 shown in FIG.
In the results shown in FIG. 16, coefficient = 8
Multiply by / 9, 7/9, 6/9, 5/9. That is, FIG.
The height of the key signal shown in 6 is adjusted based on the above coefficient. The results are illustrated in FIGS. 17 (A) to (D). Figure 1
When the key signals illustrated in FIGS. 7A to 7D are combined in the first signal combining circuit 150 and the second signal combining circuit 170 illustrated in FIG. 12, the key signal illustrated in FIG. 18 is obtained. In this case, the switching circuit 160 in FIG. 12 is selected on the first stage side of the cascade circuit configuration, and the key signal KIN0 selected by the selector 110 is passed through the second delay circuit 122 and then the first signal in the second signal combining circuit 170. It is combined with the key signal from the signal combining circuit 150.

As described above, mainly, the key signal processing device for video signal processing shown in FIG. 12, that is, the first signal processing device shown in FIG.
The operation example of the video signal processing key signal processing IC 220 has been described. It is output as a cascade output CASOUT from the key signal modification circuit 134 or the first video signal processing key signal processing IC 220 shown in FIG. This cascade output CASOUT is the key signal shown in FIG. This cascade output CASOUT
As shown in FIG. 13, the signal is guided to the second signal delay unit 250 via the second signal delay unit 250 at the next stage. Thereby, also in the second signal delay unit 250, the same key signal processing as described above can be performed. The processing results are shown in FIGS. In the second video signal processing key signal processing IC 260, as shown in FIG. 12, two or more switches in the cascade circuit configuration of the switching circuit 160 are selected,
The combined output signal CMVOUT of the first video signal processing key signal processing IC 220 is signal-synthesized in the second signal synthesizing circuit 170. The result is shown in FIG. With the above processing, it is possible to generate a key signal that creates a three-dimensional shadow as illustrated in FIG.

Next, referring to FIG. 13, the function of the 2-line delay circuit 230 provided between the first video signal processing key signal processing IC 220 and the second video signal processing key signal processing IC 260 will be described. In conclusion, the 2-line delay circuit 230 is for smooth edging. First video signal processing key signal processing I
The result of C220, specifically, the result of the key signal modification unit 130 shown in FIG.
Assume that it is as illustrated in (D). Figure 21
The key signals illustrated in (A) to (D) are 0.5H in the vertical direction and 1 clock in the horizontal direction with reference to the key input signal KEYIN illustrated in FIG. 14 delayed by 2 lines + 4 clocks. It is an expanded version. Figure 21
The key signal shown in (D) is output from the key signal modification circuit 134 as a cascade output CASOUT. Figure 1
Key signals output from the two multipliers 141 to 144 are illustrated in FIGS. 22 (A) to 22 (D). First signal synthesis circuit 1
The synthesis result of 50 is shown in FIG. The switching circuit 160 of FIG. 12 is selected on the first stage side of the cascade circuit configuration, and the key signal KIN1 delayed by two lines in the selector 110 is selected as the key signal applied to the second delay circuit 122. The second delay circuit 122 delays by four clocks. 12 in the second video signal processing key signal processing IC 260 shown in FIG.
The result of the multiplication unit equivalent to the multiplication unit 140 illustrated in FIG. 24 is illustrated in FIGS. Figure 24
The results shown in (A) to (D) are used as the first signal combining circuit 150 in the second video signal processing key signal processing IC 260.
FIG. 25 shows the result of the signal synthesis performed in step. The combination output signal CMVOUT output from the first video signal processing key signal processing IC 220 is the key signal illustrated in FIG. 23, and the switching circuit 240 shown in FIG. Only delayed.
The purpose is for the signal synthesis result to overlap the result of the first video signal processing key signal processing IC 220 at the center of the pyramid type key signal, as illustrated in FIG. As a result, as illustrated in FIG. 26, the result of the first video signal processing key signal processing IC 220 and the result of the first video signal processing key signal processing IC 220 can be overlapped as desired, The result is a key signal with a smooth border.

As described above, the first video signal processing key signal processing IC 220 and the second video signal processing key signal processing IC 260 are cascade-connected to each other, whereby the above-described first and second embodiments are performed. In addition to the effects of the example, the following effects are achieved. (1) The border (border line) of the key signal can be widened. (2) When creating a shadow of a key signal, the shadow can be lengthened. (3) When the video signal processing key signal processing apparatus of the present embodiment is used as a bandpass filter that is effective in both the vertical and horizontal directions of the key signal, the filter performance is improved.

Further, in the present embodiment, the key signal processing device for video signal processing shown in FIG. 12 is realized as an IC, and by connecting the ICs in cascade for the required number of stages,
The desired composite key signal can be easily processed.

The examples of the key signal processing shown in FIGS. 12 and 13 described above are merely examples, and the key signal processing apparatus for video signal processing of the present invention is not limited to the above-described application but can be applied to various key signal processing.

Fifth Embodiment FIG. 27 shows a block diagram of a key signal defocusing device as a fifth embodiment of the video signal processing key signal processing device of the present invention. The key signal defocusing device shown in FIG. 27 includes a key signal delay circuit 10C including unit clock delay circuits 11C to 14C, a signal selection circuit 20C, and a signal adjustment circuit 31.
The signal adjusting unit 30C includes C to 33C, the signal multiplying unit 40C including multiplying circuits 41C to 43C, and the signal synthesizing circuit 50C. The key signal defocusing device illustrated in FIG. 27 and the phase adjusting circuit illustrated in FIG. 28 are a combination of circuits that constitute the video signal processing key signal processing device of the above-described embodiment. That is, FIG.
The key signal delay circuit 10C of FIG. 7 is substantially the same as the key signal delay circuit 10A of FIG.
0C is substantially the same as the matrix circuit 20A of FIG. 1 or the selector 110 of FIG. 12, and the signal combining circuit 50C of FIG. 27 is substantially the same as the signal combining circuit 40A of FIG. However, as shown in FIG. 28, each of the signal adjusting circuits 31C to 33C of the signal adjusting unit 30C has a first vertical direction signal adjusting circuit 311, a first horizontal direction signal adjusting circuit 312, and a second vertical direction signal adjusting circuit 312, respectively. Directional signal adjusting circuit 321 and second horizontal direction signal adjusting circuit 322, third vertical direction signal adjusting circuit 331 and third horizontal direction signal adjusting circuit 332, fourth vertical direction signal adjusting circuit 341 and fourth
Of the horizontal signal adjusting circuit 342. Note that FIG.
In FIG. 28, m-system signal adjusting circuits 31C to 33C are shown, but in FIG. 28, only 4 systems are illustrated with m = 4. In the following description, the case of four lines will be described. Therefore, it is assumed that the multiplication circuit (multiplier) in the signal multiplication unit 40C shown in FIG. 27 also has four systems as illustrated in FIG.

The operation of the key signal defocusing device illustrated in FIGS. 27 and 28 will be described with reference to FIGS. 29 to 32. The key input signal KE illustrated in FIG.
When YIN is applied to the key signal defocus device,
FIG. 29 (B) shows the key signals adjusted by the vertical signal adjusting circuits 311, 321, 331, 341 (FIG. 28) in the signal adjusting unit 30C via the key signal delay circuit 10C and the signal selecting circuit 20C. Illustrated in (E).
Here, the vertical direction is narrowed. further,
Horizontal direction signal adjusting circuits 312, 322, 332, 342
The key signal whose signal has been adjusted in FIG.
Illustrated in (I). Here, the horizontal direction is narrowed. Horizontal signal adjusting circuits 312, 322, 33
The adjustment result of 2, 342 is added to the multiplier 41B shown in FIG.
The result of the weighting processing in FIG.
It shows in (D). FIG. 30E shows the result of adding the results of the multipliers 41C to 44C in the signal combining circuit 50C, that is, the defocused key signal.

In the above signal processing, when viewed in one direction, for example, the vertical direction, the key input signal K shown in FIG.
With respect to EYIN, the vertical direction signal adjusting circuits 311, 321, and 33 have the waveforms shown in FIGS.
31 and 341, vertical signal adjustment is performed, and further weighting is performed in the multiplication circuits 41C to 44C.
As shown in (E), the result of signal combination in the signal combining circuit 50C is equivalent to KEYOUT. Defocused key output signal KE from the signal synthesis circuit 50C
YOUT is smoother than the key input signal KEYIN. When the result is viewed three-dimensionally, a pyramid-type defocus signal having a smooth slope is obtained as shown in FIG. However, the defocused key signal shown in FIG. 32 is not the four steps shown in FIG.
As a more practical example, the case of 10 stages is shown.

The implementation of the key signal processing device for video signal processing of the present invention is not limited to the various embodiments described above, and various modifications can be made. For example, it is obvious to those skilled in the art to appropriately combine the above-described embodiments, and modifications and variations of the above-described embodiments are also obvious to those skilled in the art.

[0068]

According to the present invention, the key signal can be adjusted at the sub-pixel level below the pixel interval.
Further, according to the present invention, the mode signal can be adjusted according to the mode without any problem even if the two key signals are considerably separated in time and the widths of the key signals are continuous. Further, according to the present invention, two signals obtained by adjusting the key signal at the subpixel level can be combined in any mode.

Further, according to the present invention, it is possible to generate a key signal suitable for soft border line processing or soft drop border processing. According to the present invention, the border (border line) of the key signal can be widened. Further, according to the present invention, when the shadow of the key signal is created, the shadow can be lengthened. Furthermore, when the video signal processing key signal processing device of the present invention is used as a bandpass filter that is effective in both the vertical and horizontal directions of the key signal, the filter performance is improved. Further, according to the present invention, the key signal processing device for video signal processing can be realized as an IC, and the IC
By cascading a required number of stages, it is possible to easily process a desired composite key signal.

Further, according to the present invention, a defocused key signal having a smooth change can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of a key signal processing device for video signal processing according to the present invention.

FIG. 2 is a configuration diagram of a signal adjustment circuit in FIG.

FIG. 3 is a graph showing the operation of the signal adjustment circuit shown in FIG. 2, and FIG. 3A shows the first key signal output from the signal selection circuit in the signal adjustment circuit of FIG. FIG. 3B is a graph showing a time change, FIG. 3B is a graph showing a time change of the second key signal output from the signal selection circuit in the signal adjustment circuit of FIG. 2, and FIG. It is a graph which shows the interpolation result of the signal interpolation circuit in the signal adjustment circuit of No. 2.

FIG. 4 is a configuration diagram of a signal combining circuit in FIG.

5 is a graph showing an operation of the signal synthesizing circuit shown in FIG. 4, and FIG. 5 (A) is a graph showing a time change of the first key signal input to the signal synthesizing circuit; Figure 5
5B is a graph showing the time change of the second key signal input to the signal combining circuit, and FIG. 5C is a graph showing the combining result of the signal combining circuit based on the first mode. (D) is a graph showing the synthesis result of the signal synthesis circuit based on the second mode.

FIG. 6 is a graph showing a signal synthesizing operation in the first mode when the time difference between two key signals is large, and FIG. 6 (A) shows the first key input to the signal synthesizing circuit. It is a graph which shows the time change of a signal, FIG.6 (B) is a graph which shows the time change of the 2nd key signal input into the signal synthetic | combination circuit, and FIG.6 (C) is a signal based on a 1st mode. It is a graph which shows the synthetic | combination result of a synthetic | combination circuit.

FIG. 7 is a graph showing an operation of signal combination by a positive NAM operation for expanding the width of a key signal, and FIG. 7 (A) is a graph showing a time change of a first key signal; 7B to 7D are graphs sequentially showing a time change of a first key signal delayed by a unit clock, and a graph showing a time change of an input second key signal. 7 (E) is a graph showing the change over time of the second key signal, and FIG. 7 (F) is a graph showing the combining result of the signal combining circuit based on the positive NAM operation.

FIG. 8 is a circuit configuration diagram of the signal combining unit illustrated in FIG. 1.

FIG. 9 is a graph illustrating soft borderline processing according to the present invention.

FIG. 10 is a graph illustrating soft drop border processing according to the present invention.

11 is a second embodiment of a key signal processing device for video signal processing according to the present invention, wherein the soft border line processing shown in FIG. 9 and the soft drop border shown in FIG. It is a block diagram of the key signal processing device for video signal processing which processes the key signal which can be processed.

FIG. 12 shows, as a third embodiment of the key signal processing device for video signal processing of the present invention, a key signal enabling soft border line processing or soft drop border processing. FIG. 3 is a configuration diagram of a video signal processing key signal processing device for efficiently performing a process of a key signal and so on in a complex and efficient manner.

13 is an expanded configuration diagram of the video signal processing key signal processing device shown in FIG. 12 as a fourth embodiment of the video signal processing key signal processing device of the present invention.

FIG. 14 is a diagram stereoscopically illustrating a basic key signal to be processed in the video signal processing key signal processing apparatus according to the third and fourth embodiments of the present invention.

15A to 15D are graphs showing a state in which the key input signal shown in FIG. 14 is sequentially delayed by 1H line.

16A to 16D are graphs showing results of shading the key signal shown in FIG. 15 in the key signal modification circuit shown in FIG. 12, respectively.

17A to FIG. 17D are diagrams of FIG.
The result shown in (D) shows that in the multiplier shown in FIG. 12 in the first video signal processing key signal processing IC 220 of FIG. 13, coefficients = 8/9, 7/9, 6/9, 5 /
It is a graph which shows the result of having multiplied by 9.

FIG. 18 is a graph showing a result of signal combination of the results shown in FIGS. 17A to 17D by the second signal combining circuit of FIG.

19 (A) to (D) show the result shown in FIG. 18 in addition to the second video signal processing key signal processing IC of FIG.
6 is a graph showing the result of signal processing in step S1.

20 is a graph showing the results of signal synthesis of the results shown in FIGS. 19A to 19D in the second video signal processing key signal processing of FIG. 13.

21A to 21D are graphs showing the processing results of the key signal modification unit shown in FIG. 12 in the first video signal processing key signal processing IC of FIG. 13.

22A to 22D are graphs showing processing results of the multiplication unit shown in FIG. 12 in the first video signal processing key signal processing IC of FIG. 13.

23 is a graph showing a result of signal combination of the results shown in FIGS. 22 (A) to 22 (D) in the first signal combining circuit of FIG.

24 (A) to (D) are the same as FIG. 23 (A) to FIG.
FIG. 14 is a graph showing a result of calculating the result shown in FIG. 13D by a multiplication unit in the second video signal processing key signal processing IC of FIG. 13.

FIG. 25 shows the results shown in FIGS. 24 (A) to 24 (D) in the first key signal processing IC for the second video signal processing.
3 is a graph showing the result of signal combination by the signal combination circuit of FIG.

FIG. 26 is a graph illustrating the function of the two-line delay circuit of FIG. 13 for smoothly edging the result shown in FIG. 25.

FIG. 27 is a block diagram of a key signal defocusing device of a fifth embodiment of a video signal processing key signal processing device of the present invention.

28 is a circuit configuration diagram of the signal adjustment circuit of FIG. 27.

FIG. 29 is a graph showing an operation example of the key signal defocusing device shown in FIGS. 27 and 28;
9A is a key input signal, FIGS. 2B to 2E are vertical phase adjustment results, and FIGS. 29F to 29I are horizontal phase adjustment results.

FIG. 30 is a graph showing an operation example of the key signal defocusing device shown in FIGS. 27 and 28, and FIG.
0 (A) to (D) are graphs showing weighting processing results of the multiplication circuit.

FIG. 31 is a graph showing the processing of the key signal defocusing device of FIGS. 27 and 28, and FIG.
Is a key input signal, and FIGS. 31 (B) to 31 (D) are vertical phase adjustment in the vertical direction signal adjusting circuit and weighting in the multiplication circuit. As a result, FIG. It is a graph which shows the result of having done.

32 is a perspective view of a defocused key signal that three-dimensionally represents the result of FIG. 31. FIG.

[Explanation of symbols]

 10-key signal delay circuit 10A-key signal delay circuit 11-15-unit clock delay circuit 20-signal selection circuit 20A-matrix signal selection circuit 30-signal interpolation circuit 30A-first signal interpolation Circuit 30B ... Second signal interpolation circuit 30C ... Signal adjustment unit 31C-33C ... Signal adjustment circuit 40 ... Signal synthesis circuit 40A ... Signal synthesis unit 401-407 ... Signal synthesis circuit 40C ... Signal multiplication unit 41C to 44C .. Multiplier 50C .. Signal combining circuit 100 .. Key signal delay circuit 101 to 104 .. 1H line delay circuit 200 .. Signal transmission bus 300 .. Vertical (vertical) direction signal adjusting unit 301 to 303.・ Vertical signal adjustment circuit 400 ・ ・ Horizontal (horizontal) signal adjustment units 401-403 ・ ・ Horizontal signal adjustment Circuit 500 ... Multiplying unit 501 to 503 ... Multiplier circuit 600 ... Signal combining circuit 110 ... Selector 120 ... Timing adjusting circuit 121 ... First delay circuit 122 ... Second delay circuit 130 ... Key signal Deformation unit 131-134 .. Key signal transformation circuit 140 .. Multiplication unit 141-144 .. Multiplier 150 .. 1st signal synthesizing circuit 160 .. Switching circuit 170 .. 2nd signal synthesizing circuit 210 .. 1 signal delay unit 211-214 .. 1 line delay circuit 220 .. 1st video signal processing key signal processing IC 230 .. 2 line delay circuit 240 .. Switching circuit 250 .. 2nd signal delay unit 251 ... 254 ... 1-line delay circuit 260 ... 2nd key signal processing IC for video signal processing 300 ... Direct) direction signal adjusting unit 301 to 303 ... Vertical direction signal adjusting circuit 400 ... Horizontal (horizontal) direction signal adjusting unit 401 to 403 ... Horizontal direction signal adjusting circuit 500 ... Multiplying unit 501-503 ... Multiplying circuit 600 ..Signal synthesis circuits

Claims (13)

[Claims] 1. A signal delay circuit for sequentially delaying a key input signal used for applying a special effect to a video signal in units of one clock and outputting the delayed key signal, and the key input signal and the signal delay circuit. A signal selection circuit that receives a plurality of delay key signals that are output and that selects two pairs of signal sets each having a predetermined delay relationship based on the selection control signal, and a first set that is output from the signal selection circuit. A first signal interpolating circuit for interpolating a signal of the pair of signals using the first coefficient, and a signal of the second pair of the pair of signals output from the signal selecting circuit using the second coefficient. A second signal interpolating circuit for performing interpolation, and a signal synthesizing circuit for synthesizing signals of the output of the first signal interpolating circuit and the output of the second signal interpolating circuit to output as a video signal processing key signal Video signal processing Key signal processing device. 2. A key signal processing device for video signal processing according to claim 1, wherein said signal synthesizing circuit has a circuit for performing a positive NAM operation and a negative NAM operation, and these operations are performed based on a mode signal. 3. A signal delay circuit for sequentially delaying a key input signal used for applying a special effect to a video signal in a time unit corresponding to one horizontal synchronizing period of the video signal, and outputting the delayed plurality of key signals. Receiving the key input signal and a plurality of delayed key signals output from the signal delay circuit, selecting a pair of signal sets each having a predetermined delay relationship in the first direction of the video signal, and selecting the selected signals For adjusting the width of the video signals by a predetermined number of layers in the first direction
A direction signal adjusting unit, and a predetermined number of layers for the second direction of the video signal that receives the signal adjustment results of the first direction signal adjusting unit and is orthogonal to the first direction with respect to those signals. A second direction signal adjusting unit for adjusting the widths of the signals only; a multiplication unit for multiplying the second direction signal adjusted signal by a predetermined coefficient by the number of layers for key signal processing; And a signal synthesizing circuit for synthesizing a plurality of multiplication results corresponding to the number of layers for key signal processing, and outputting as a video signal processing key signal. 4. The key signal processing device for video signal processing according to claim 3, wherein said signal synthesizing circuit has a circuit for performing a positive NAM operation and a negative NAM operation, and these operations are performed based on a mode signal. 5. A selector for selecting and outputting a plurality of key input signals based on a selection control signal, and a plurality of key signal transforming circuits for receiving the key signals output from the selectors and transforming the waveforms of the key signals. And each of the key signal modification circuits sequentially delays the key input signal output from the selector by a time unit corresponding to one horizontal synchronizing period of the video signal, and outputs the delayed plurality of key signals. A signal delay circuit, a key input signal output from the selector, and a plurality of delayed key signals output from the signal delay circuit,
Selecting a pair of signal pairs each having a predetermined delay relationship in the first direction of the video signal, and adjusting the width of those signals by a predetermined number of layers in the first direction of the video signal for the selected signal; A one-way signal adjusting unit, and a predetermined layer for receiving a result of signal adjustment by the first direction signal adjusting unit and for a second direction of a video signal that is orthogonal to the first direction with respect to those signals. A plurality of second direction signal adjusting units for adjusting the widths of the signals by a number, and a plurality of multiplying circuits for multiplying a plurality of outputs of the plurality of key signal transforming circuits by predetermined coefficients, respectively, and the multiplying circuits. And a first signal synthesizing circuit for synthesizing a plurality of the multiplication results of 1. into a video signal processing key signal processing device. 6. The first signal combining circuit is a positive NA.
Has a circuit for performing M operation and negative NAM operation,
6. The calculation according to claim 5, wherein these calculations are performed based on the mode signal.
Key signal processing device for video signal processing described. 7. A first signal receiving a signal processing key signal of a key signal processing device for video signal processing in the preceding stage, and delaying by a calculation time required by the key signal modification circuit and the multiplication circuit.
Delay circuit, a second delay circuit that delays the selected key signal from the selector by an operation time required by the key signal modification circuit and the multiplication circuit, and an output of the first delay circuit or the second delay circuit. A result of the switching circuit and the first signal combining circuit for selecting an output of the circuit and applying it to the second signal combining circuit, and an output of the first delay circuit selected by the switching circuit or the second 6. The video signal processing key signal processing device according to claim 5, further comprising a second signal synthesizing circuit for synthesizing a signal with any of the outputs of the delay circuits. 8. The second signal synthesizer circuit is a positive NA.
Has a circuit for performing M operation and negative NAM operation,
8. The calculation according to claim 7, wherein these calculations are performed based on the mode signal.
Key signal processing device for video signal processing described. 9. A first line delay circuit means having a plurality of delay circuits for receiving a key input signal and sequentially delaying the time corresponding to one line of a video signal, and the first line delay circuit means. 9. A first signal adjusting circuit means for receiving a plurality of delayed key signals and an original key input signal and adjusting the signals for these key signals, wherein the first signal adjusting circuit means is a signal processing circuit. The following circuit described, a selector that selects and outputs a plurality of key input signals based on a selection control signal, and a plurality of key signal modification that receives the key signals output from the selector and modifies the waveforms of the key signals Each of the plurality of key signal transformation circuits sequentially delays the key input signal output from the selector by a time unit corresponding to one horizontal synchronization period of a video signal, A signal delay circuit for outputting the key signal of, and a key input signal output from the selector and a plurality of delayed key signals output from the signal delay circuit,
Selecting a pair of signal pairs each having a predetermined delay relationship in the first direction of the video signal, and adjusting the width of those signals by a predetermined number of layers in the first direction of the video signal for the selected signal; A one-way signal adjusting unit, and a predetermined layer for receiving a result of signal adjustment by the first direction signal adjusting unit and for a second direction of a video signal that is orthogonal to the first direction with respect to those signals. A plurality of second direction signal adjusting units for adjusting the widths of the signals by a number, and a plurality of multiplying circuits for multiplying a plurality of outputs of the plurality of key signal transforming circuits by predetermined coefficients, respectively, and the multiplying circuits. And a signal processing key signal of a key signal processing device for video signal processing in the preceding stage, and receives the key signal transformation circuit and the multiplication circuit. A first delay circuit for delaying an operation time required by an arithmetic circuit; a second delay circuit for delaying a selected key signal from the selector for an operation time required by the key signal modification circuit and the multiplier circuit; Switching circuit for selecting the output of the delay circuit or the output of the second delay circuit and applying it to the second signal combining circuit, the result of the first signal combining circuit, and the switching circuit A second signal combining with either the output of the first delay circuit or the output of the second delay circuit
Key signal processing apparatus for video signal processing, comprising a signal synthesizing circuit according to claim 1. 10. The output of a plurality of key signal transforming circuits of said video signal processing key signal processing device is received, and one of the video signals is received.
Second line delay circuit means having a plurality of delay circuits for sequentially delaying a time corresponding to a line, a plurality of delay key signals delayed by the second line delay circuit means, and the video signal processing A second signal that receives the output of the first signal combining circuit of the key signal processing device as a signal processing key signal of the key signal processing device for video signal processing in the preceding stage, and performs a second signal adjustment on these key signals. Adjusting circuit means, wherein the second signal adjusting circuit means has the following circuit according to claim 5-8, a selector for selecting and outputting a plurality of key input signals based on a selection control signal, and the selector A plurality of key signal modification circuits for receiving the output key signals and modifying the waveforms of the received key signals, each of the plurality of key signal modification circuits being output from the selector. And a signal delay circuit for sequentially delaying the key input signal in time units corresponding to one horizontal synchronization period of the video signal and outputting the delayed plurality of key signals, the key input signal output from the selector, and the signal delay Accepts multiple delayed key signals output from the circuit,
Selecting a pair of signal pairs each having a predetermined delay relationship in the first direction of the video signal, and adjusting the width of those signals by a predetermined number of layers in the first direction of the video signal for the selected signal; A one-way signal adjusting unit, and a predetermined layer for receiving a result of signal adjustment by the first direction signal adjusting unit and for a second direction of a video signal having an orthogonal relationship to the first direction with respect to those signals. A plurality of second direction signal adjusting units for adjusting the widths of the signals by a number, and a plurality of multiplying circuits for multiplying a plurality of outputs of the plurality of key signal transforming circuits by predetermined coefficients, respectively, and the multiplying circuits. And a signal processing key signal of a preceding video signal processing key signal processing device are required in the key signal modification circuit and the multiplication circuit. A first delay circuit for delaying an operation time required by the selector, a second delay circuit delaying a selected key signal from the selector for an operation time required by the key signal modification circuit and the multiplier circuit, and the first delay circuit Of the output of the first delay circuit or the switching circuit for selecting the output of the second delay circuit and applying it to the second signal combining circuit, the result of the first signal combining circuit, and the first selected by the switching circuit. Second signal synthesis with either the output of the second delay circuit or the output of the second delay circuit
6. The key signal processing device for video signal processing according to claim 5, further comprising a signal synthesizing circuit according to claim 5. 11. A two-line delay circuit for delaying the output of the second signal combining circuit of the first signal adjusting circuit means by two lines, and an output of the second signal combining circuit of the first signal adjusting circuit means. 11. The video signal processing according to claim 10, further comprising a switching circuit for switching the output of the two-line delay circuit and applying it to the second signal adjusting circuit means as a key signal of a key signal processing device for video signal processing in the preceding stage. Key signal processing device. 12. A signal delay for sequentially delaying a key input signal used for applying a special effect for defocusing a video signal based on a clock corresponding to the transfer of the video signal, and outputting a plurality of delayed key signals. A circuit, and a signal selection circuit that receives the key input signal and a plurality of delayed key signals output from the signal delay circuit, and selects a plurality of pairs of signals in a predetermined delayed relationship based on a selection control signal, The first of the video signals for the selected pairs of signals
A first direction signal adjusting unit that adjusts the position in the direction and adjusts the width of the adjusted signal; and a video signal that is orthogonal to the first direction with respect to the result of a plurality of pairs adjusted by the first direction signal adjusting unit The position of the signal in the second direction and the width of the adjusted signal are adjusted.
A key signal device including a direction signal adjustment unit, a multiplication unit that multiplies a result of the second direction-adjusted pairs of sets by a predetermined coefficient, and a signal combination circuit that combines the multiplication results of the multiplication units. Focus device. 13. The key signal processing device for video signal processing according to claim 12, wherein said signal synthesizing circuit has a circuit for performing a positive NAM operation and a negative NAM operation, and these operations are performed based on a mode signal.