JPH1188119A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep the symmetrical property of a filter, to keep the phase of an output signal and to suppress a phase distortion by executing control to disconnect an input to a multiplier corresponding to a tap when a non-target signal is supplied to the tap and, at the same time, disconnect input signal supply to the multiplier which is symmetrical as against the tap. SOLUTION: Video signals are successively inputted from an input terminal 1 of a video signal processing digital filter with five-tap configuration and the respective signals are delayed by 1H delay elements 2-5 with a serial connecting configuration. A coefficient to be the tap coefficient of the filter is multiplied by multipliers 11-15 concerning the respective delay signals, the total sum of the respective multiplying outputs is obtained in an adder 21 and the output signal is derived. In this case, the signals to be inputted to the multipliers 11-15 are disconnected through the use of selectors 6-10 in accordance with the timings of the input signals and control is executed so as to permit the output of the tap to be symmetrical as against the coefficient of the tap without the target signal to be 'zero'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital filter, and more particularly to a digital filter used for processing a video signal.

[0002]

2. Description of the Related Art An example of a conventional digital filter of this type is disclosed in Japanese Patent Laid-Open No. Hei 5-219413, and FIG. 13 shows a block diagram of the digital filter. In FIG. 13, a 7-tap video signal processing digital filter is used.

[0005] In FIG. 13, a video signal from an input terminal 70 is sequentially input to a circuit having a configuration in which six 1H delay elements 31 to 36 are connected in series. Delay element 3 with six input signals
A total of seven output signals of 1-36 are multipliers 37-36.
43, and are multiplied by the tap coefficients selected by the selectors 44 to 50, respectively. These multiplied outputs are added by an adder 71 and derived from an output terminal 72.

In such a configuration, a video signal is inputted from an input terminal 70, and 1H delay elements 31 to 31 connected in series are connected.
Each is delayed at 36. The input signal and each of these delayed outputs are multiplied by a coefficient to be a tap coefficient of a filter in multipliers 37 to 43, and the sum of these multiplied outputs is obtained in an adder 71 to obtain an output signal. .

[0005] Coefficients to be multiplied by the respective delay signals in the multipliers 37 to 43 are set to "0" by using the selectors 44 to 50 according to the timing of the input signal, in the case of a signal that does not require filtering. In the case of a signal to be filtered, a predetermined value other than "0" is set.

FIGS. 14 and 15 show the transition of each tap coefficient and the output signal of the digital filter in the conventional circuit of FIG. FIG. 14 shows the transition of the coefficient of each tap. In FIG. 14, Ln (n = 1, 2, 2)
3,...) Represent time-sequential pixels, and 、 represents a target signal to be filtered and a video signal. In addition, black circles are non-purpose signals that do not require filtering and are signals in a blanking period or the like.

The tap coefficients Ai are represented for convenience in order to show the symmetry between Ai and Ai, and they are assumed to be the same.

When the center tap is in the signal L6, the coefficients of the digital filter are: ｛0,0,0, A-3 + A-2 + A-1 + A0, A1, A2,
A3｝, and the output signal at that time is (A-3 + A-2 + A-1 + A0) · L6 + A1 · L7 + A2
・ L8 + A3 ・ L9

When the center tap is in the signal L7, the coefficients of the digital filter are: ｛0, 0, A-3 + A-2 + A-1, A0, A1, A2, A3
出力 and the output signal at that time is (A-3 + A-2 + A-1) · L6 + A0 · L7 + A1 · L8
+ A2 · L9 + A3 · L10.

When the center tap is at signal L17, the coefficients of the digital filter are: A-3, A-2, A-1, A0, A1 + A2 + A3, 0,
0｝, and the output signal at that time is A-3 · L14 + A-2 · L15 + A-1 · L16 + A0 · L17 +
(A1 + A2 + A3) · L18

When the center tap is in the signal L18, the coefficients of the digital filter are: A-3, A-2, A-1, A0 + A1 + A2 + A3, 0,
0,0}, and the output signal at that time is: A-3 L15 + A-2 L16 + A-1 L17 + (A0 + A1 +
A2 + A3) .L18.

[0012]

Since the conventional digital filter operates as described above, if the filter is applied to a place other than the image signal, one side of the tap becomes shorter and shorter, and the filter becomes asymmetric. . When the filter becomes asymmetric, there is a problem that the pixel position (phase) of the output signal is shifted as compared with the signal before the original filter is applied. When the number of taps of the filter is large, the digital filter is connected in series. This problem is exacerbated.

It is an object of the present invention to provide a digital filter capable of suppressing the phase distortion by maintaining the phase of the output signal while maintaining the symmetry of the filter.

[0014]

According to the present invention, a signal in which a target signal to be filtered and a non-target signal which does not require filtering are transmitted in time series is supplied to an input terminal, A plurality of delay elements that are connected in series with each other and output the input signal with the same time delay, and a plurality of multipliers that multiply the input signal and each output signal of the delay element by a predetermined tap coefficient; An adder for adding and outputting an output, wherein when the undesired signal is supplied to a tap, the input to the multiplier corresponding to the tap is cut off, and the center tap is turned off. The digital filter includes control means for controlling the supply of the signal to the multiplier symmetric with respect to the tap with respect to the input.

The control means is provided between each input of the multiplier and each of the input terminals and each output terminal of the delay element to cut off a supply signal to each input of the multiplier. A plurality of selectors each having a zero terminal, and when the undesired signal is supplied to the tap, control is performed such that each selector of the input of the multiplier corresponding to the symmetric tap selects the zero terminal. It is characterized by the following.

According to the present invention, a signal in which a target signal to be filtered and a non-target signal that does not require filtering are sent out in time series is supplied to an input terminal and connected in series with each other. A plurality of delay elements for delaying the input signal by the same time and outputting the same; a plurality of multipliers for multiplying the input signal and each output signal of the delay element by a predetermined tap coefficient; And an adder that outputs an inverted signal of the input signal to the multiplier that is symmetric with respect to the center tap when the non-target signal is supplied to the tap. A digital filter is obtained that includes control means for controlling the input signal of the corresponding multiplier.

The control means has a plurality of sign inverters for inverting the sign of each input signal to the multiplier,
When the non-target signal is supplied to a tap, the output of the sign inverter corresponding to the tap symmetrical to the tap is controlled to be the input of the multiplier corresponding to the tap.

The operation of the present invention will be described. In one invention,
When an undesired signal that does not need to be filtered is supplied to a tap, the input to the multiplier corresponding to the tap is cut off, and at the same time, the signal is supplied to the multiplier symmetrical to the tap with respect to the center tap. , The symmetry of the output signal is maintained.

In another invention, when the undesired signal is supplied to the tap, the sign-inverted signal of the input signal to the multiplier symmetrical to the tap with respect to the center tap is converted to the signal of the multiplier corresponding to the tap. By controlling to be an input signal, the symmetry of the output signal is maintained.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and shows a digital filter for processing a video signal having a 5-tap configuration. Referring to FIG. 1, an input signal IN is supplied from an input terminal 1 to four 1H delay elements 2 connected in series with each other.
To 5 are sequentially input.

A total of five signals, the input signal and the output signals of the four delay elements, are input to corresponding multipliers 11 to 15 via selectors 6 to 10, respectively. The other input of each of the selectors 6 to 10 is supplied with a "0" signal for making the output of each of these selectors zero.

The outputs of the selectors 6 to 10 are connected to multipliers 11 to
15 and multiplied by taps generated by tap coefficient generators 16 to 20, respectively. These multiplied outputs are all added by an adder 21 to obtain a filter output OUT2.
It becomes 3.

The selector control unit 22 includes selectors 6 to 10
The control signal S1 controls the selectors 6 and 10 simultaneously, the control signal S2 controls the selectors 7 and 9 simultaneously, and the control signal S3 controls the selector 8 respectively. . In other words, the control signals simultaneously control the selectors of taps that are symmetrical about the center tap.

In such a configuration, video signals are sequentially input from the input terminal 1, and the signals are respectively delayed in the delay elements 2 to 5 in a series connection configuration. Each of the delayed signals is multiplied by a coefficient to be a tap coefficient of a filter in multipliers 11 to 15, and a sum of respective multiplied outputs is obtained in adder 21, and an output signal is derived.

In this case, the signals input to the multipliers 11 to 15 may be changed depending on the timing of the input signal.
The control is performed so that the output of the tap which is symmetric with the coefficient of the tap deviated from the target signal is set to "0".

In this example, for example, when a signal L19 which is not a video signal is applied to the tap formed by the multiplier 11,
The outputs of the selectors 6 and 10 are switched to "0" by the control signal S1.

When the non-video signals L20 and L19 are applied to the taps constituted by the multipliers 12 and 13, respectively, all the outputs of the selectors 6, 7, 9 and 10 are set to "0" by the control signals S1 and S2. ".

FIG. 2 is a diagram showing the relationship between each tap coefficient of the digital filter of FIG. 1 and control signals S1 to S3.
As described with reference to FIGS. 13 and 14, Ln indicates an input signal, O indicates that the input signal is a video signal, that is, a signal to be processed by this filter, and ● indicates that the input signal is in a blanking period or the like. Represents a signal that is not a video signal, ie, is not going to be processed by this filter.

FIG. 3 shows multipliers 11 to 1 under the same conditions as in FIG.
5 are respectively shown. FIG. 4 shows the output terminal 23.
In FIG.

FIG. 5 is a diagram showing an example of the selector control unit 22 of FIG. In FIG. 5, a counter 57 is reset by an HD (horizontal drive) pulse 51, and counts a distance from a horizontal synchronization signal of a video signal to each pixel.

Now, the output of the counter 57 in the horizontal direction is N
Assuming that the pixel starts at the position +1 and ends at the position N + 15, "N" is input to the input terminal 52 and "N + 12" is input to the input terminal 53 (see FIG. 6). .

In the comparators 58 and 59, the output T1 of the counter 57 and the respective inputs "N" and "N + 1" of the input terminals 52 and 53 are output.
2 ". The output T2 of the comparator 58 is sequentially delayed by one-pixel delay circuits (DFF) 60 to 62, and the output T3 of the comparator 59 is delayed by a delay circuit (DFF) 6
3 to 65 are sequentially delayed.

The outputs T4 to T6 of the DFFs 60 to 62 are S
R-FFs (set-reset FFs) 66 to 68 become set inputs, and DFFs 63 to 65 output T7 to T9 are S
These are reset inputs of the R-FFs 66 to 68. The inverted Q outputs 54 to 56 of the SR-FFs 66 to 68 become control signals S1 to S3.

FIG. 6 is a timing chart showing the operation of the circuit of FIG. 5. As is apparent from these figures, the control signals S1 to S1 for controlling the selectors 6 to 10 of FIG.
It turns out that S3 is obtained.

FIG. 7 is a block diagram of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. Also in this example, a digital filter for video signal processing having a 5-tap configuration is shown.

In FIG. 7, only parts different from FIG. 1 will be described. FIG. 1 shows one input of each of the selectors 6 to 10.
In this example, “0” is applied, but in this example, the outputs of the code converters 24 to 28 are applied respectively. Code converter 2
Numeral 4 is for converting the sign of the output of the delay element 5, and a code converter 25 is for converting the sign of the output of the delay element 4.

The code converter 26 converts the sign of the output of the delay element 3, and the code converter 27 converts the sign of the output of the delay element 2. Also, the code converter 2
Numeral 8 is for converting the sign of the input signal IN.

The selectors 6 to 10 are controlled independently by control signals S1 to S5 from the selector controller 22. The other configuration is the same as that of FIG. 1 and the description is omitted.

In this configuration, the input signal IN is input from the input terminal 1 and the delay elements 2 connected in series to each other
-5, respectively. Each delay output is connected to selector 6
To 10 are selected, and the delayed outputs are selected according to the state of the input signal, and the multipliers 11 to 15 multiply the delayed outputs by the coefficients serving as the tap coefficients of the filter. The multiplied outputs of the multipliers 11 to 15 are summed by an adder 21 and are derived from an output terminal 23 as an output signal OUT.

The selectors 6 to 10 are controlled so as to determine an output signal depending on whether or not a target signal is applied to each tap. In the filter, if an undesired signal is applied to one tap, the sign-inverted signal of the signal input to the multiplier of the symmetric tap with respect to the center tap,
An undesired signal is input to the tap multiplier.
As a result, the function of the tap to which an unintended signal is applied and the function of the symmetric tap are canceled.

In this example, when the signal input to the center tap is L17 and the non-video signal L19 is applied to the tap formed by the multiplier 11, the selector 6 encodes the output of the delay element 5 by the control signal S1. The conversion circuit 24 outputs the inverted signal.

FIG. 8 is a diagram showing coefficients and control signals of each tap of the digital filter in FIG. In the figure, Ln represents an input signal name, O represents a target image signal, ● represents a signal other than the target image,
S5 represents each control signal output from the first to fifth outputs of the selector control unit 22.

The tap coefficients as shown in the figure are generated from tap coefficient generators 16 to 20 according to the signal position of the center tap. 9 shows the outputs of the multipliers 11 to 15 under the same conditions as in FIG. 7, and FIG. 10 shows the signals output to the output terminal 23.

FIG. 11 is a diagram showing an example of the selector control unit 22 of FIG. In FIG. 11, the counter 105 is H
It is reset by the D pulse 101 and counts the distance from the horizontal synchronization signal of the video signal to each pixel.

Now, assuming that the output of the counter 105 in the horizontal direction starts at a position of N + 1 and ends at a position of N + 15, the input terminal 102 has "N",
It is assumed that "N + 15" is input to the input terminals 103 (see FIG. 12).

In the comparators 106 and 107, the counter 10
5 is compared with the respective inputs "N" and "N + 15" of the input terminals 102 and 103, respectively. Comparator 10
6 is a one-pixel delay circuit (DFF) 108-1.
10 and the output T3 of the comparator 107
Are sequentially delayed by delay circuits (DFF) 111 to 113.

The output T7 of the DFF 111 is the SR-FF11
5 and the output T8 of the DFF 112 is SR
-Set input of FF116. Also, DFF
An output T4 of 108 is a reset input of the SR-FF 118, and an output T6 of the DFF 109 is a reset input of the SR-FF 119.

The HD pulse 101 is output from the SR-FF 116,1
17 and the SR-FF 118,1
There are 19 set inputs. The set input of the SR-FF 117 is applied with the output of the OR gate 114 having the HD pulse and the output T9 of the DFF 113 as two inputs. And each output of SR-FF115-119 turns into control signal S1-S5.

FIG. 12 is a diagram showing the operation of the circuit of FIG. 11, and as is apparent from these diagrams, the selectors 6 to 6 of FIG.
Thus, the control signals S1 to S5 that are intended to control the control signal 10 are obtained.

[0051]

As described above, according to the present invention, the symmetry of the digital filter is maintained by losing the effectiveness of both the tap where the undesired signal is applied and the tap symmetrical to the tap. Therefore, there is an effect that the phase of the output signal can be suppressed and the phase distortion of the output signal can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart showing a relationship between a coefficient of each tap and a control signal in the block of FIG.

FIG. 3 is a timing chart of each output signal of the multiplier of FIG. 1 under the same conditions as in FIG. 2;

FIG. 4 is a timing chart of output signals of the block in FIG. 1 under the same conditions as in FIG. 2;

FIG. 5 is a diagram illustrating an example of a selector control unit 22 of the block in FIG. 1;

FIG. 6 is a timing chart showing the operation of the block in FIG. 5;

FIG. 7 is a block diagram of another embodiment of the present invention.

8 is a timing chart showing a relationship between a coefficient of each tap and a control signal in the block of FIG. 7;

9 is a timing chart of each output signal of the multiplier of FIG. 7 under the same conditions as in FIG. 8;

FIG. 10 is a timing chart of output signals of the block in FIG. 7 under the same conditions as in FIG. 8;

FIG. 11 is a diagram illustrating an example of a selector control unit 22 of the block in FIG. 7;

FIG. 12 is a timing chart showing the operation of the block in FIG. 11;

FIG. 13 is a diagram illustrating an example of a conventional digital filter.

FIG. 14 is a diagram showing changes in tap coefficients of the blocks in FIG. 14;

FIG. 15 is a diagram showing a change in an output signal of the block shown in FIG. 14;

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 to 5 1H delay element 6 to 10 selector 11 to 15 multiplier 16 to 20 tap coefficient generator 21 adder 22 selector control unit 23 output terminal 24 to 28 code converter

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03H 17/08 H03H 17/08 A H04N 5/14 H04N 5/14 Z

Claims (5)

[Claims] 1. A signal in which a target signal to be filtered and a non-target signal that does not require filtering are sent out in time series are supplied to input terminals, connected in series with each other, and each of the input signals is A plurality of delay elements that output with an equal time delay, a plurality of multipliers that multiply the input signal and each output signal of the delay element by a predetermined tap coefficient, and an adder that adds and outputs the multiplied outputs. When the non-target signal is supplied to a tap, the input to the multiplier corresponding to the tap is cut off, and at the same time, the multiplier is symmetric with the tap with respect to the center tap. A digital filter comprising control means for controlling the supply of the input signal to be cut off. 2. The control means is provided between each input of the multiplier and each input terminal of the multiplier and each output terminal of the delay element to cut off a supply signal to each input of the multiplier. A plurality of selectors each having a zero terminal, and when the undesired signal is supplied to the tap, control is performed such that each selector of the input of the multiplier corresponding to the symmetric tap selects the zero terminal. The digital filter according to claim 1, wherein: 3. A signal in which a target signal to be filtered and a non-target signal that does not require filtering are sent out in time series are supplied to input terminals, connected in series with each other, and each of the input signals is A plurality of delay elements that output with an equal time delay, a plurality of multipliers that multiply the input signal and each output signal of the delay element by a predetermined tap coefficient, and an adder that adds and outputs the multiplied outputs. When the non-target signal is supplied to a tap, a sign inverted signal of an input signal to the multiplier symmetrical to the tap with respect to the center tap when the tap is supplied to an input of a multiplier corresponding to the tap. A digital filter comprising control means for controlling a signal to be a signal. 4. The control means has a plurality of sign inverters for inverting the sign of each input signal to the multiplier, and when the non-target signal is supplied to a tap, the control means is symmetric with the tap. 4. The digital filter according to claim 3, wherein an output of the sign inverter corresponding to the tap is controlled to be an input of a multiplier corresponding to the tap. 5. The method according to claim 1, wherein the target signal is an image signal, the non-target signal is a signal in a blanking period other than the image signal, and the delay element is a 1H delay element. A digital filter according to any one of claims 1 to 4.