JPH07307686A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To generate a clock signal approximately coinciding with the timing of the peak value of a demodulated signal by differentiating the absolute value signal or the demodulated signal to generate a differential signal and comparing this differential signal with a prescribed threshold value to generate a comparison output signal. CONSTITUTION:A two-phase modulated SS signal is inputted to a correlation peak detection part 1 of a clock reproducing circuit. A correlation peak signal is outputted to the detection part 1 with the period of a PN signal. A detection part 2 detects this correlation peak signal to output the demodulated signal. An absolute value circuit part 3 generates the absolute value signal.of the demodulated signal, and a differentiating circuit part 5 differentiates this absolute value signal to generate a differential signal. A comparison circuit part 6 compares this differential signal with a required threshold, and for example, a positive pulse in the period when the differential signal exceeds the threshold, namely, the reproducing clock is generated, and the rise timing of this positive pulse approximately coincides with the peak timing of the demodulated signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit used when demodulating received data in a spread spectrum communication receiver.

[0002]

2. Description of the Related Art In a conventional clock recovery circuit, a pseudo noise (PN) signal is generated and transmitted by a spread spectrum system as a spread signal. As shown in FIG. Correlation peak detector 1 that generates and outputs a correlation peak signal for each cycle of a noise signal
A detection unit 2 that detects the correlation peak signal to generate a demodulation signal that represents the original data; an absolute value circuit unit 3 that generates an absolute value signal of the demodulation signal; and an absolute value signal of the demodulation signal. And a comparison circuit section 6 for generating a comparison output signal (clock signal) 9 by comparing it with a predetermined threshold value.

The operation of the conventional clock recovery circuit will be described with reference to the signal waveforms of the respective parts of the conventional clock recovery circuit shown in FIG. The two-phase phase-modulated SS signal (A) is input to the correlation peak detection unit 1 of the clock reproduction circuit. The correlation peak detection unit 1 that stores a pseudo noise (PN) signal in advance has a function shown in FIG.
The correlation peak signal (B) shown in is output. The detector 2 detects the correlation peak signal (B) and outputs a demodulation signal (C). The absolute value circuit unit 3 generates the absolute value signal (D) of the demodulated signal (C), and the comparison circuit unit 6 generates the absolute value signal (D).
And a predetermined threshold value are compared, and a reproduction clock (E) is output. However, the recovered clock obtained by the conventional clock recovery circuit always has a “deviation” from the center of the demodulated signal (C), as shown in FIG. Therefore, when the data is extracted from the demodulation signal (C) by utilizing the timing of the same reproduction clock (E), for example, the falling edge or the rising edge of the signal, the peak value of the demodulation signal (C) is changed due to the “deviation”. There is a problem that the reliability of data reproduction is deteriorated when the data cannot be taken out and the reception condition is bad.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a clock recovery circuit for generating a clock signal that substantially matches the timing of the peak value of a demodulated signal.

[0005]

In order to achieve the above object, a signal generated and transmitted by a spread spectrum method using a pseudo noise signal as a spread signal is input, and a correlation peak signal is generated for each cycle of the pseudo noise signal. A correlation peak detection unit that generates and outputs, a detection unit that detects the correlation peak signal to generate a demodulation signal that represents the original data, an absolute value circuit unit that generates an absolute value signal of the demodulation signal, and the demodulation signal In the clock recovery circuit, which comprises a comparison circuit unit that compares the absolute value signal of 1 with a predetermined threshold value and generates and outputs a comparison output signal, the absolute value signal of the demodulated signal is input and its differential signal is input to the comparison circuit unit. A differential circuit section for supplying is provided, and the differential signal is compared with a predetermined threshold value to generate and output a comparison output signal.

[0006]

With the above construction, the differential circuit section differentiates the absolute value signal of the demodulated signal to generate a differential signal. The comparison circuit unit compares the differential signal with a required threshold value, and, for example, generates a positive pulse in a period in which the differential signal exceeds the threshold value, and the falling timing of the positive pulse is the demodulated signal. It almost coincides with the peak timing.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock recovery circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a clock recovery circuit according to the present invention. A reference numeral 1 is a correlation peak detection unit for inputting an SS (spread spectrum) signal 8 generated and transmitted by a spread spectrum method using a pseudo noise (PN) signal as a spread signal, and generating and outputting a correlation peak signal for each cycle of the pseudo noise signal. Is. Reference numeral 2 is a detector that detects the correlation peak signal and generates a demodulated signal that represents the original data. An absolute value circuit unit 3 generates an absolute value signal of the demodulated signal. 4 is an automatic gain (AGC) for keeping the peak value of the absolute value signal constant.
It is a control unit. Reference numeral 5 denotes a differentiating circuit section that inputs the absolute value signal of the demodulated signal and supplies the differential signal to the comparing circuit section. Reference numeral 6 denotes a comparison circuit unit that compares the absolute value signal of the demodulated signal with a predetermined threshold value to generate and output a clock signal 9.

The operation of the clock recovery circuit according to the present invention is
This will be described with reference to the signal waveforms of the respective parts shown in FIG. 1 and FIG. The two-phase phase-modulated SS signal (A) is input to the correlation peak detection unit 1 of the clock recovery circuit. The correlation peak detection unit 1 that stores a pseudo noise (PN) signal in advance outputs the correlation peak signal (B) shown in FIG. 3 for each cycle of the PN signal. The detector 2 detects the correlation peak signal (B) and outputs a demodulation signal (C). The absolute value circuit section 3 generates an absolute value signal (D) of the demodulated signal (C), and the differentiating circuit section 5 differentiates the absolute value signal (D),
A differential signal (E) is generated. The comparison circuit unit 6 compares the differential signal (E) with a required threshold value, and generates, for example, a positive pulse in a period in which the differential signal (E) exceeds the threshold value: a reproduction clock (F). The falling timing (circle) of the same positive pulse almost coincides with the peak timing of the demodulated signal (C).

As shown in FIG. 2, the correlation peak detection unit 1 is composed of a highly reliable SAW (surface acoustic wave) matched filter 11, and the detection unit 2 delays the correlation peak signal by a required time. 21 and a mixer 22 that multiplies the correlation peak signal delayed by the delay element and the correlation peak signal. In addition, S transmitted in the air
Since the waveforms of the demodulated signal (C) and the absolute value signal (D) may become small depending on the state of the S signal (A), for example, the automatic gain (AGC) control unit 4 is provided after the absolute value circuit unit 3.
May be provided to keep the peak value of the absolute value signal (D) constant.

[0010]

As described above, the present invention provides a clock recovery circuit that generates a clock signal that substantially matches the timing of the peak value of a demodulated signal. Therefore, it is possible to eliminate the “difference” between the recovered clock and the demodulated signal obtained by the conventional clock recovery circuit, and to extract the peak value of the demodulated signal. Therefore, it is possible to expect an improvement in reliability during data reproduction. Further, even when the rising or falling of the obtained clock signal includes jitter, almost the peak value of the demodulated signal can be taken out, so that improvement in reliability can be expected during data reproduction.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a clock recovery circuit according to the present invention.

FIG. 2 is a specific block diagram of a correlation peak detection unit and a detection unit of the clock recovery circuit according to the present invention.

FIG. 3 is a waveform-time chart showing signal waveforms of respective parts of the clock recovery circuit according to the present invention.

FIG. 4 is a block diagram of an embodiment of a conventional clock recovery circuit.

FIG. 5 is a waveform-time chart showing signal waveforms of respective parts of the conventional clock recovery circuit.

[Explanation of symbols]

 1 Correlation peak detection unit 2 Detection unit 3 Absolute value circuit unit 4 Automatic gain (AGC) control unit 5 Differentiation circuit unit 6 Comparison circuit unit 8 SS (spread spectrum) signal 9 Clock signal 11 SAW (surface acoustic wave) matched filter 21 Delay Element 22 Mixer

Claims (3)

[Claims] 1. A correlation peak detection unit for inputting a signal generated and transmitted by a spread spectrum method using a pseudo noise signal as a spread signal, and for generating and outputting a correlation peak signal for each period of the pseudo noise signal, and the correlation peak. A detection unit that detects a signal to generate a demodulated signal, an absolute value circuit unit that generates an absolute value signal of the demodulated signal, and a comparison output signal that compares the absolute value signal of the demodulated signal with a predetermined threshold value. In the clock recovery circuit, which is composed of a comparison circuit section for generating and outputting the above, a differentiation circuit section for inputting the absolute value signal of the demodulated signal and supplying the differentiation signal to the comparison circuit section is provided. And a clock recovery circuit for generating and outputting a comparison output signal. 2. The clock recovery circuit according to claim 1, wherein the falling or rising of the comparison output signal is used for signal acquisition. 3. The clock recovery circuit according to claim 1, further comprising an automatic gain control section for holding the peak value of the absolute value signal constant.