JPH07307349A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent generation of voids due to gate metal material, in a gate aperture, and reduce stress in a Schottky gate, in an MESFET. CONSTITUTION:An interlayer insulating film 4 is deposited on a semiconductor substratum having a GaAs substrate 1, an operating layer 2, and a contact layer 3, and a gate aperture is formed. A first gate metal layer 6a forming a Schottky junction and a second gate metal layer 6b containg barrier metal are formed. A gate wiring 8 is formed by electrolytic plating using photoresist as a mask. The gate metal layers 6a, 6b are patterned in a gate electrode form, by using new photoresist as a mask. The interlayer insulating film 4 is etched by a wet method (a). The resist 9 is eliminated, and a protective film 10 is formed. Source-drain electrodes 11a, 11b are formed by selectively eliminating the protective film 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a field effect transistor having a gate electrode formed in a shape projecting toward a source side and a drain side.

[0002]

2. Description of the Related Art Conventionally, in a GaAs Schottky barrier gate type field effect transistor (hereinafter referred to as MESFET), in order to put it into practical use as an amplifying element in the millimeter wave band, the gate electrode has a T shape or a Y shape. It has been attempted to reduce the gate resistance of the miniaturized gate electrode by forming a part of the electrode so as to project like a "visor" toward the source side and the drain side by forming the shape. In this case, the T-shaped / Y-shaped gate electrode (hereinafter, referred to as “overhanging gate electrode”) has an asymmetric structure in which the “overhanging portion” to the “overhanging portion” have a drain side shorter than the source side, and thus the gate electrode and the drain electrode. It is known that reducing the parasitic capacitance between them is effective in improving the high frequency characteristics of the MESFET.

A semiconductor device having a protruding gate electrode having an asymmetrical structure of this kind and a method of manufacturing the same are disclosed in Japanese Patent Laid-Open No. 3-113.
It is known from Japanese Patent No. 66136. The prior art described in this publication will be described below with reference to FIGS.
This will be described with reference to FIG. 10A to 10D and 11A to 11C are cross-sectional views in order of the steps for explaining the method of forming the metal electrode in this conventional technique.

In this prior art, first, the GaAs substrate 1
A substrate on which the operating layer 2 and the contact layer 3 have been grown is prepared by the molecular beam epitaxial method, and the interlayer insulating film 4 having a film thickness of about 300 nm is formed on the semiconductor substrate by the CVD method or the like. Next, the gate opening pattern 1 having an opening line width of about 0.4 μm is formed by an ordinary lithography technique.
The first photoresist film 5 having 01a is formed.
Next, the interlayer insulating film 4 is selectively etched using the first photoresist film 5 as a mask to expose the surface of the contact layer 3 in the shape of the gate opening pattern 101a [FIG. 10 (a)].

Next, the first photoresist film 5 is removed, and the contact layer 3 is selectively etched using the interlayer insulating film 4 as a mask to form a recess portion. Then, CV
An insulating film having a film thickness of about 300 nm is formed by the D method, and this is etched back to make the gate opening width 0.2 to 0.25.
A side wall insulating film 4a that regulates the thickness to about μm is formed [FIG.
(B)].

Next, from above the semiconductor substrate 1, WSix and Ti /
Au is deposited to a film thickness of about 200 nm to form a first gate metal layer 6c and a second gate metal layer 6d [FIG. 10 (c)]. Then, the third of the gate electrode pattern
Photoresist film 9 is formed [FIG. 10 (d)], and this is used as a mask for ion milling and MIE (Magnes
Etoron Ion Etching) method is used to selectively remove the first gate metal layer 6c and the second gate metal layer 6d to process these metal layers into gate electrode shapes [FIG.
1 (a)].

Next, the third photoresist film 9 is removed, and a fourth photoresist film (not shown) having openings in the drain electrode pattern, the source electrode pattern and the gate electrode pattern is formed. With the photoresist film of No. 4 as a mask, the interlayer insulating film 4 and the sidewall insulating film 4a
Are selectively etched to selectively expose the surface of the contact layer 3 [FIG. 11 (b)].

Next, ohmic metal (AuGe-Ni-
Au; total film thickness is about 200 nm) and the source electrode 11a, the drain electrode 11b, and the third gate metal layer 6e are formed by the lift-off method using the above-mentioned fourth photoresist film [FIG. c)].

In the field effect transistor having this structure, the gate metal layers 6c and 6 are different from the gate length (gate opening width).
Since the cross-sectional areas of d and 6e can be made large, the gate resistance can be reduced. Further, since the protruding portion of the gate metal layer to the drain side is reduced, the gate-drain parasitic capacitance can be reduced and the high frequency characteristics can be improved.

[0010]

In this type of transistor, the gate opening width is made fine for higher frequencies (0.2 to 0.25 .mu.m in the above example), and a recess portion is often provided. Therefore, the aspect ratio here becomes worse and the step becomes steep. On the other hand, in order to reduce the gate resistance, the gate metal layer needs to be formed to have a certain thickness or more, so that the metal layer is formed so as to completely fill the gate opening. However, it is difficult to completely fill the inside of the opening by sputtering or vapor deposition having a low step coverage, and as shown in FIG.
2 easily occurs. Further, the barrier layer becomes extremely thin in the opening even if it does not become a void, and a situation in which the barrier function cannot be fulfilled is occurring, resulting in deterioration of reliability.

Further, since the line width of the gate electrode has been miniaturized, stress is concentrated on the Schottky junction portion of the gate metal layer (in particular, the end portion in contact with the sidewall insulating film 4a).
It has become apparent in recent years. The problem of "stress concentration on the edge of the gate electrode" becomes remarkable especially when the gate electrode is formed in a thick film and when the gate electrode is formed asymmetrically. When the semiconductor layer is operated for a long time (for example, 1000 hours) in the state where the stress concentration occurs, the crystallinity of the semiconductor layer in the Schottky junction portion deteriorates, resulting in deterioration of characteristics such as reduction of gm and fluctuation of drain current.

The present invention has been made in view of such a situation, and an object thereof is to firstly prevent generation of voids in the gate electrode in the gate opening. Secondly, it is to enhance the barrier property to the Schottky metal against the good conductive metal, and the third is
First, the stress concentration on the end of the Schottky gate is relaxed. And by achieving these,
It is intended to manufacture a field-effect transistor having a low gate resistance and an excellent high-frequency characteristic with a high yield, and also to improve the reliability of the product.

[0013]

In order to achieve the above object, according to the present invention, a gate electrode (6a, 6a, which forms a Schottky junction with an active layer (2) on a semiconductor substrate (1, 2, 3). 6b) and a field-effect transistor having a source electrode (11a) and a drain electrode (11b) electrically connected to the active layer, the gate electrode (6a, 6b) having a substantially γ shape. A semiconductor device, characterized in that the source-side overhang is formed to be larger than the drain-side overhang, and a gate wiring (8) is formed on the source-side overhang of the gate electrode. Provided.

According to the invention, (1) a step of forming an insulating film (4) on a semiconductor substrate (1, 2, 3) having an active layer, and (2) a gate opening () in the insulating film. 101)
And (3) forming the metal layers (6a, 6b) forming a Schottky junction with the active layer (3) to a film thickness smaller than that of the insulating film. 4) A step of forming a gate wiring (8) on the metal layer (6a, 6b) by a selective plating method, and (5) a step of patterning the metal layer to form a gate electrode (6). A method for manufacturing a semiconductor device is provided.

[0015]

A characteristic point of the field effect transistor of the present invention is that the gate wiring is formed on the protruding portion of the gate electrode on the source side. With such a configuration, it is possible to reduce the thickness of the gate electrode while suppressing an increase in gate resistance. Then, by making the film thickness of the gate electrode sufficiently smaller than the film thickness of the insulating film in which the gate opening is formed, it becomes possible to prevent the generation of voids in the gate metal layer in the gate opening, and Relief of stress at the key joint can be realized. Further, since the gate wiring is formed on the protruding portion of the gate electrode, that is, the good conductive metal film is formed in the region where the barrier metal can be formed thickly, so that the barrier property against the gate wiring is sufficiently secured. Will be able to.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. [First Embodiment] FIGS. 1 to 7 are views showing the steps of forming a metal electrode in the first embodiment of the present invention in the order of steps, and are views (a) in each drawing. FIG. 4B is a plan view, and FIG. 6B is a process sectional view taken along the line AA ′ of FIG.

In the method of manufacturing the field effect transistor of the first embodiment, first, a semiconductor substrate in which the operating layer 2 and the contact layer 3 are grown on the GaAs substrate 1 by the molecular beam epitaxial method is manufactured. Next, a photolithography technique and a wet etching method are applied to this semiconductor substrate to selectively etch the contact layer 3 on the semiconductor substrate to a width of about 1.3 μm, and then a SiO ₂ film is formed by the LP-CVD method. The interlayer insulating film 4 is formed by forming a film with a thickness of about 500 nm. Then, a chemically amplified resist is applied to 500
i line (wavelength 365 nm) using spin-coating with a film thickness of about nm and using a phase shift mask method called edge transmission type
A first photoresist film 5 having a gate opening pattern 101a with an opening line width of 0.25 μm is formed by lithography.
Are formed (FIGS. 1A and 1B).

Next, the first photoresist film 5 and MIE (Ma) using a mixed gas of CHF ₃ / O ₂ as a mask are used.
Selective etching of the interlayer insulating film 4 is performed by gnetoron Ion etching to form a gate opening 101 that exposes a part of the operating layer 2, and the first photoresist film 5 is removed by ashing [FIG. a), (b)].

Next, WSix is deposited on the entire surface of the semiconductor substrate by a sputtering method to a film thickness of about 100 nm to form a first gate metal layer 6a, and subsequently, TiN is deposited by a sputtering method to a film thickness of about 80 nm. Thicker, more Pt 10
The second gate metal layer 6b is formed by depositing each to a thickness of about nm. Next, apply about 1 photo resist for i-line.
A second photoresist film 7 having a gate wiring pattern-shaped opening is formed by utilizing a lithography technique in which the opening is formed in a reverse tapered cross-sectional shape with a thickness of μm. Next, gold (Au) is selectively plated using the second photoresist film 7 as a mask and the first and second gate metal layers 6a and 6b as power feeding layers to form a film having a thickness of 600 n.
A gate wiring 8 of about m is formed [FIG.
(B)].

Next, the second photoresist film 7 is removed, a new photoresist is applied, and then patterned into the shape of the gate electrode by the i-line lithography technique to form the third photoresist film 9. . Then, using the third photoresist film 9 as a mask, the second gate metal layer 6 is formed.
b (TiN-Pt) is formed by an ion milling method using argon (Ar) gas, and the first gate metal layer 6a (W
The Six) in MIE method using gas such as SF _6, are selectively etched to form a gate electrode 6. At this time, the interlayer insulating film 4 is also slightly etched [see FIG.
(A), (b)].

Further, using the third photoresist film 9 as a mask, the interlayer insulating film 4 is formed by the wet etching method.
Are selectively etched. In this step, the interlayer insulating film 4 remains only on the source-side protruding portion side of the gate electrode 6, and is completely removed from under the drain-side protruding portion [FIGS. 5A and 5B].

Further, the third photoresist film 9 is removed, and Si is formed by LP-CVD from above the semiconductor substrate.
O ₂ is deposited to a film thickness of about 100 nm to form the protective film 10 (FIGS. 6A and 6B). Next, a fourth photoresist film (not shown) having openings having a pattern of source openings and drain openings is formed, and the protective film 8 is selectively etched using this as a mask by a wet etching method. A source opening 102 and a drain opening 103 that expose the surface of the contact layer 3 are formed. Then, a metal layer of AuGe-Ni-Au as an ohmic metal is deposited to a total film thickness of about 200 nm, and a source electrode 11a and a drain electrode 11b are formed by a lift-off method using a fourth photoresist film (not shown) [ Figure 7
(A), (b)].

FIG. 8 is a plan view showing the overall structure of the field effect transistor thus formed. In the figure, the portions shown in FIGS. 1A to 7A are surrounded by broken lines. As shown in FIG. 8, the two gate wirings 8 are formed so as to be drawn out from the gate pad 8a. In the illustrated example, the number of gate wirings drawn from the gate pad 8a is two,
More gate wirings can be arranged in a comb shape.

In a normal GaAs MESFET, the distance between the gate electrode and the source electrode is 2 to 3 μm.
Therefore, in the above-described embodiment, the gate wiring 8
Can have a line width of about 1 μm. Further, since the void problem and the stress concentration problem at the gate end portion do not occur in this gate wiring, it can be formed sufficiently thick, which can contribute to the reduction of the gate resistance. Since the low-resistance gate wiring 8 to the Schottky gate are the thin-film gate metal layers 6a and 6b, the resistance is increased in this portion, but the influence is minor because the distance is relatively short. . Furthermore, in this embodiment,
In addition to shortening the protruding portion of the gate electrode on the drain side, by completely removing the interlayer insulating film 4 between the drain side contact layer 3 and the gate electrode 6, the gate-
The parasitic capacitance between drains is further reduced.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. Note that FIG.
(A)-(c) is process order sectional drawing for demonstrating the formation method of the metal electrode in the 2nd Example of this invention. In this embodiment, after performing the same steps as the steps of the first embodiment shown in FIGS. 1 to 4, in the etching step for the interlayer insulating film 4 shown in FIG. 5 of the first embodiment, By shortening the etching time, as shown in FIG. 9A, etching is performed so as to leave a part of the interlayer insulating film 4 in contact with the overhanging portion on the drain side of the gate electrodes (6a, 6b).

Thereafter, the third photoresist film 9 is removed by the same process as in the first embodiment, and LP-
SiO ₂ is deposited by CVD to a thickness of about 100 nm to form a protective film 10 covering the entire surface [FIG.
(B)]. Then, a fourth photoresist film (not shown) having openings in the shape of the source opening and the drain opening to be formed is formed, and the protective film 10 is selectively etched by the wet etching method using this as a mask.
Further, a source electrode 11a and a drain electrode 11b are formed by depositing an ohmic metal film and lift-off using this fourth photoresist film [FIG. 9 (c)].

In the present embodiment, as shown in FIG. 9C, since a part of the interlayer insulating film 4 which is in contact with the protruding portion of the gate electrode on the drain side is left, the interlayer insulating film 4 in this portion is left.
In the case of the first embodiment in which the above is completely removed [(b) of FIG. 7]
Compared with, the effect of reducing the parasitic capacitance between the gate electrode and the drain electrode is reduced, but since the surface of the operating layer 2 is not exposed during the manufacturing process, it is possible to prevent the characteristic deterioration that may occur due to the exposure. There are advantages. further,
Since the interlayer insulating film 4 is provided also on the drain side of the gate electrode and supports the gate electrode, the stress at the drain side end of the gate electrode can be reduced as compared with the case of the first embodiment.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention described in the claims. For example, the materials, dimensions, etc. used in the embodiments can be changed appropriately. Further, in the embodiment, the transistor having the recessed portion has been described, but instead of this method, the surface of the semiconductor substrate may be flattened. In addition, the present invention is an ordinary MESFET.
However, the present invention is not limited to this.
The operating layer 2 may be a transistor including a heterojunction.

[0029]

As described above, in the field effect transistor according to the present invention, the gate electrode has a substantially γ shape, and the source side projecting portion is longer than the drain side, and the gate wiring is provided on the source side projecting portion. Since it is formed, the following effects can be enjoyed.

Since the gate resistance can be suppressed to a low level even if the gate electrode is formed thin, it is possible to prevent the gate opening from being filled with the gate metal material, and the void of the gate electrode material can be filled in the opening. Occurrences can be prevented. Since the gate wiring is formed on the flat portion where the barrier metal can be formed thickly, sufficient barrier property can be secured. Since the metal layer for forming the Schottky junction can be thinly formed, the stress generated at the gate end can be relieved. In addition to making the gate electrode asymmetrical, if the interlayer insulating film on the drain side is removed, a further gate-
The drain-to-drain parasitic capacitance can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view in one manufacturing process stage for explaining a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a plan view and a cross-sectional view in a manufacturing process that follows the process of FIG. 1 for explaining the manufacturing process of the first embodiment of the present invention.

FIG. 3 is a plan view and a sectional view in a manufacturing process that follows the process of FIG. 2 for explaining the manufacturing process of the first embodiment of the present invention.

FIG. 4 is a plan view and a sectional view in a manufacturing process that follows the process of FIG. 3 for explaining the manufacturing process of the first embodiment of the present invention.

FIG. 5 is a plan view and a sectional view in a manufacturing process that follows the process of FIG. 4 for explaining the manufacturing process of the first embodiment of the present invention.

FIG. 6 is a plan view and a sectional view in a manufacturing process that follows the process of FIG. 5 for explaining the manufacturing process of the first embodiment of the present invention.

FIG. 7 is a plan view and a sectional view in a manufacturing process that follows the process of FIG. 6 for explaining the manufacturing process of the first embodiment of the present invention.

FIG. 8 is a plan view of the field effect transistor according to the first embodiment of the present invention.

9A to 9C are sectional views in order of the processes, for illustrating a second embodiment of the present invention.

FIG. 10 is a part of a sectional view in order of steps for explaining a conventional example.

11A to 11C are sectional views in order of the processes in the process following the process of FIG. 10 for explaining the conventional example.

FIG. 12 is a cross-sectional view for explaining the problems of the conventional example.

[Explanation of symbols]

 1 GaAs substrate 2 operation layer 3 contact layer 4 interlayer insulating film 4a sidewall insulating film 5 first photoresist film 6 gate electrodes 6a, 6c first gate metal layers 6b, 6d second gate metal layer 6e third gate Metal layer 7 Second photoresist film 8 Gate wiring 8a Gate pad 9 Third photoresist film 10 Protective film 11a Source electrode 11b Drain electrode 12 Void 101 Gate opening 101a Gate opening pattern 102 Source opening 103 Drain opening

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/872

Claims (6)

[Claims] 1. A semiconductor device comprising a field effect transistor having a gate electrode forming a Schottky junction with an active layer on a semiconductor substrate, and a source electrode and a drain electrode electrically connected to the active layer, The gate electrode is generally γ-shaped, and the source-side overhang is larger than the drain-side overhang, and a gate wiring is formed on the source-side overhang of the gate electrode. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the film thickness of the gate electrode is smaller than the film thickness of the interlayer insulating film in which the gate opening is formed. 3. The semiconductor device according to claim 1, wherein the interlayer insulating film is completely or almost entirely removed from under the drain side protruding portion of the gate electrode. 4. The metal of the first layer, wherein the gate electrode forms a Schottky junction with an active layer, and the metal of the second layer, which serves as a barrier between the metal layer of the first layer and the gate wiring. The semiconductor device according to claim 1, further comprising a layer. 5. A step of (1) forming an insulating film on a semiconductor substrate having an active layer, (2) a step of forming a gate opening in the insulating film, and (3) a Schottky junction with the active layer. Forming a metal layer having a thickness smaller than that of the insulating film, and (4) forming a gate wiring on the portion of the metal layer extending above the insulating film by selective plating. A method of manufacturing a semiconductor device, comprising: a forming step; and (5) a step of patterning the metal layer to form a gate electrode. 6. A step of (1) forming a contact layer on a semiconductor substrate having an active layer, and (2) a step of forming an opening larger than a gate opening to be formed later in the contact layer. ) Forming an insulating film on the semiconductor substrate having an active layer and a contact layer, and (4)
A step of exposing a part of the surface of the active layer by forming a gate opening in a portion of the insulating film above the opening of the contact layer; and (5) a metal layer forming a Schottky junction with the active layer. And (6) forming a gate wiring on the portion of the metal layer extending over the insulating film by a selective plating method. (7) a step of patterning the metal layer to form a gate electrode, the method for manufacturing a semiconductor device.