JPH0730110A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and its manufacturing method which can increase the level of integration of a MOS type transistor. CONSTITUTION:Gate oxide films 21-24 and 14 are formed on a semiconductor substrate 1, a thin-film formed layer of a strip shape is formed on these gate oxide films, and a conductive polysilicon layer is formed as if covering the thin-film formed layer. It is then treated with etchback to form conductive spacers 11a and 11b. Then, after the thin-film formed layer is removed, conductive spacers 15a and 15b are formed in the same method. This constitutes a semiconductor device forming a source drain diffusion layer 16 by means of the self-alignment method with conductive spacers 11a, 15b, and 11b, 15b as masks, as well as its manufacturing method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a MOS type transistor is miniaturized and integrated by using a conductive spacer, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a MOS transistor can be highly integrated by reducing the element size within a range where a scaling law is established. If the device can be miniaturized, the degree of integration can be increased, but there is a limit to the miniaturization of the MOS transistor even if the self-alignment technique is used due to the design rule determined by the exposure technique, the etching technique, etc. . Therefore, in order to further increase the degree of integration, it is necessary to wait for the performance of the manufacturing apparatus to be improved, and it takes time and cost to develop it.

An example of a conventional method for manufacturing a MOS transistor will be described with reference to FIG. 12
As shown in (a), a thermal oxide film 2 which is a gate oxide film is formed on a semiconductor substrate 1, a conductive polysilicon layer 3 is formed so as to cover the thermal oxide film 2, and a polysilicon layer 3 is formed on the polysilicon layer 3. A resist film is deposited on the entire surface and patterned to form a resist mask 4. Subsequently, as shown in FIG. 12B, the polysilicon layers 3 are selectively etched by the resist mask 4 to form the conductive layers 3 ₁ and 3 3 serving as gate electrodes.
Form ₂ . If necessary, an acid resistant thin film such as a silicon nitride film is deposited on the surfaces of the conductive layers 3 ₁ and 3 ₂ .
After that, the dopant is ion-implanted by a self-alignment method (self-alignment method) using the conductive layers 3 ₁ and 3 ₂ as a mask to form the shallow diffusion layer 6.

Subsequently, as shown in FIG. 12C, a silicon dioxide layer 5 is formed so as to cover the conductive layers 3 ₁ and 3 ₂ .
The silicon dioxide layer 5 is etched back to form spacer oxide films 5a and 5b as shown in FIG. After that, the dopant is ion-implanted into the semiconductor substrate 1 using the conductive layers 3 ₁ and 3 ₂ and the spacer oxide films 5a and 5b as masks to form the source / drain diffusion layers 7. Incidentally, FIG.
Is an LDD (Lightly Doped Drain) type MOS transistor and has a symmetrical structure. By forming a spacer oxide film on only one side, a MOS transistor having an asymmetrical structure can be formed.

[0005]

In the conventional MOS transistor, there is a limit that the miniaturization of the element can be achieved depending on the exposure accuracy and the etching accuracy. As a method for overcoming this manufacturing limit, as shown in FIG. 12, a conductive layer 3 is formed by using a resist mask 4 processed and formed in one photomask step.
₁ and 3 ₂ are formed, the width L of the conductive layers 3 ₁ and 3 ₂ is set to a limit value, and the shallow diffusion layer 6 is formed by the self-alignment method using the conductive layers 3 ₁ and 3 ₂ . Further, spacer oxide films 5a and 5a are formed on both sides of the conductive layers 3 ₁ and 3 _2.
There is a method of forming b and forming the source / drain diffusion layer 7 by a self-alignment method to make it finer without depending on the exposure accuracy or the like. However,
As shown in the above example, the channel width L of the conductive layers 3 ₁ and 3 ₂ which are the gate electrodes is regulated by the design rule based on the exposure accuracy and the etching accuracy, and the channel width L should be narrower than this. I can't. In other words, even if the self-alignment method is used to miniaturize the element, there is a limit to miniaturization, and if it is attempted to further increase the degree of integration, it is necessary to wait for the development of manufacturing equipment and manufacturing technology, There is a problem that miniaturization cannot be achieved.

The present invention has been made in view of the above-mentioned problems, and provides a semiconductor device and a method of manufacturing the same which can further increase the degree of integration of MOS transistors.

[0007]

In order to achieve the above-mentioned object, the semiconductor device of the present invention comprises a source / drain diffusion layer, and the gate electrode or floating gate of the semiconductor device comprises a conductive spacer. It is characterized by that. The conductive spacer may be composed of first and second conductive spacers that are in contact with each other, and the first and second conductive spacers may be formed of conductive sidewalls and an oxide film. . Furthermore, the semiconductor device of the present invention includes source / drain diffusion layers, and the first and second gate oxide films formed under the first and second conductive spacers have different film thicknesses. It is what Further, the semiconductor device of the present invention comprises a source / drain diffusion layer, first and second conductive spacers forming a gate electrode or a floating gate and in contact with each other, and a circle of the first and second conductive spacers. It is characterized in that third and fourth spacers respectively formed on the arc-shaped portions are formed.

Further, the semiconductor device of the present invention is provided with the source / drain diffusion layers, and the first and second gate oxide films formed on the surface of the semiconductor substrate are in contact with each other to be floating gates in contact with the gate oxide film. Conductive spacer, a flattening treatment layer for reducing the aspect ratio of the first and second conductive spacers, and an insulating film covering the flattening treatment layer and the first and second conductive spacers. And a control gate layer formed on the insulating film.

According to the method of manufacturing a semiconductor device of the present invention, a rectangular thin film forming layer is formed on the first gate oxide film formed on the surface of the semiconductor substrate, and both sides of the rectangular thin film forming layer are formed. A first conductive spacer is formed at an end, the rectangular thin film forming layer is removed, a second gate oxide film is formed, and a second conductive spacer is formed on a sidewall of the first conductive spacer. And a source / drain diffusion layer is formed by using the first and second conductive spacers as a mask.

In the method of manufacturing a semiconductor device of the present invention, a thermal oxidation step of forming a thermal oxide film to be a gate oxide film on the surface of a semiconductor substrate and a step of forming a thin film forming layer at a low temperature on the thermal oxide film. A patterning step of selectively etching the thin film forming layer to set an element spacing, depositing a first conductive layer covering the patterned thin film forming layer, and etching the first conductive layer. Forming a conductive spacer on the side wall of the thin film forming layer, and removing the entire thin film forming layer, or an etching step of leaving a part of the vapor phase growth layer on the side wall of the conductive spacer. And a step of forming a source / drain diffusion layer using the conductive spacers or the like formed in the etching step as a mask.

Also, the method of manufacturing a semiconductor device of the present invention comprises a step of forming a thermal diffusion layer to be a first gate oxide film on the surface of a semiconductor substrate, and a protective film such as a nitride film covering the thermal diffusion layer. A step of forming, a step of forming a thin film forming layer on the protective film, a patterning step of selectively etching the thin film forming layer to set element intervals, and a first step of covering the patterned thin film forming layer. Depositing a conductive layer, etching the first conductive layer to form first conductive spacers on both side walls of the thin film forming layer, the thin film forming layer and the protective film therebelow. Removing the thermal oxide film to expose the surface of the semiconductor substrate; forming a thermal oxide film to be a second gate oxide film on the exposed semiconductor substrate; and the first conductive layer. Second conductive layer covering the spacer Depositing, etching the second conductive layer to form a second conductive spacer on a sidewall of the first conductive spacer, and using the first and second conductive spacers as a mask And a diffusion step of forming a source / drain diffusion layer.

In the method of manufacturing a semiconductor device of the present invention, a step of forming a thermal oxide film to be a gate oxide film on the surface of a semiconductor substrate and a step of forming a protective film such as a nitride film covering the thermal oxide film. A step of depositing a thin film forming layer on the protective film, a patterning step of selectively etching the thin film forming layer to set an element interval, and a first conductive layer covering the patterned thin film forming layer. A step of depositing, a step of etching the first conductive layer to form first conductive spacers on both side walls of the thin film forming layer, a step of forming the thin film forming layer, the protective film thereunder, and the gate oxidation. An etching step for exposing the surface of the semiconductor substrate by removing the film; a step for forming a thermal oxide film to be a second gate oxide film on the exposed semiconductor substrate; and a step for forming the first conductive spacer. Second to cover Depositing a conductive layer, etching the second conductive layer to form a second conductive spacer on a sidewall of the first conductive spacer, and the first and second conductive spacers A diffusion step of forming a source / drain diffusion layer by ion-implanting a dopant using the mask as a mask, a planarization processing step of reducing the aspect ratio of the first and second conductive spacers, and a planarization processing step after the planarization processing step. The method is characterized by including a step of forming an insulating layer and an etching step of patterning a conductive layer covering the insulating layer to form a control gate layer.

[0013]

According to the above-described means, the semiconductor device of the present invention forms the conductive spacer on the side wall of the patterned thin film forming layer such as the vapor phase growth layer, and the conductive spacer is formed as M.
A gate electrode or a floating gate of an OS type transistor, which is not restricted by a design rule set by the exposure accuracy of a semiconductor manufacturing apparatus.
By reducing the element size, the degree of integration of the semiconductor device can be increased. According to the method of manufacturing a semiconductor device of the present invention, the conductive spacer formed on the side wall of the patterned thin film forming layer such as the vapor phase growth layer is used as the gate electrode or floating gate of the MOS type transistor, and the conductive spacer is formed. Is a manufacturing method of forming a source / drain diffusion layer by a self-alignment method using as a mask,
Since the gate width can be formed narrow without being restricted by the design rule, the element size can be formed small.

Further, according to the method of manufacturing the semiconductor device having the floating gate by lowering the aspect ratio of the conductive spacers by the flattening process step, the degree of integration of the semiconductor device in which the nonvolatile semiconductor memory elements are integrated can be further enhanced. Is something that can be done. Further, according to the semiconductor device and the manufacturing method thereof of the present invention, when the gate electrode or the floating gate is formed by using the two conductive spacers, the film thickness of the gate oxide film and the left and right widths of the conductive spacers. It is possible to form a MOS transistor having various characteristics due to an asymmetrical shape, since each of them can be changed. Further, the capacitance between the gate oxide film and the substrate can be made different by making the thickness of the gate oxide film directly below the first and second conductive spacers different.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. 1 to 3
Shows a manufacturing process of a semiconductor device according to the present invention,
It is sectional drawing which shows the one Example. As shown in FIG. 1A, the semiconductor substrate 1 is thermally oxidized to form a thermal oxide film 2 having a thickness of about 200Å to be a first gate oxide film on the surface thereof. As a protective film for the thermal oxide film 2, a silicon nitride film (Si ₃ N ₄ ) 8 having a thickness of 200 Å or less is formed by a vapor phase growth method (CVD method). Further, an LTO film (Low Temperature Oxid) such as a silicon oxide film is deposited by a low pressure (LP) CVD method at a low temperature of about 350 ° C. The LTO film 3, which is a vapor phase growth layer, has a thickness of 300.
It is desirable to set it to 0Å or less. Further, a resist film is deposited on the entire surface of the LTO film 3 and patterned to form a resist mask 10. The width L ₁ of this resist mask is
Ideally, the minimum resolution dimension of the manufacturing apparatus is set, but some margin may be given.

Next, as shown in FIG. 1B, the LTO film 3 is exposed to R by the patterned resist mask 10.
IE (Reacting Ion Etching) method strip or rectangular semiconductor substrate surface is etched by, for example LTO film 9 _1,
9 ₂ is formed. Immediately below the LTO films 9 ₁ and 9 ₂ is RI.
Silicon nitride films 8 ₁ and 8 ₂ patterned by the E method or the CDE (Chemical Dry Etching) method are formed. Thereafter, as shown in FIG. 1C, a conductive polysilicon layer 11 is deposited by the CVD method, and as shown in FIG. 1D, the polysilicon layer 11 is etched by isotropic etching by the RIE method. The conductive spacers 11a and 11b are formed by backing.

2A, which follows FIG. 1D, a resist film is deposited on the entire surface and then patterned to form a resist mask 12, and L exposed from the resist mask 12 is exposed.
This is a step of etching the TO films 9 ₁ and 9 ₂ by the RIE method, and then the resist mask 12 is removed. Subsequently, as shown in FIG. 2B, a silicon nitride film 13 having a thickness of 200 Å or less is formed by the CVD method so as to cover the conductive spacers 11a and 11b. After that, Figure 2
As shown in (c), the silicon nitride film 13 is etched back by the RIE method or the CDE method to conduct the conductive spacers 1.
Silicon nitride films 13 ₁ and 13 ₂ are formed on the side walls of 1a and 11b. Then, as shown in FIG. 2D, the conductive spacers 11a and 11b and the silicon nitride films 13 ₁ and 13 _{2 are formed.}
Using the mask as a mask, the exposed thermal oxide film 2 is removed by a self-alignment method to form gate oxide films 2 _{1 to} 2 ₄ .

3 (a) following the manufacturing process of FIG. 2 (d).
Is a step of forming a thermal oxide film 14 serving as a second gate oxide film on the exposed surface of the semiconductor substrate 1 by a thermal oxidation step. In this thermal oxidation step, thermal oxide films are also formed on the surfaces of the conductive spacers 11a and 11b. The thermal oxide film 14 is formed to a thickness of about 120Å, which is thinner than the thermal oxide film 2. As shown in FIG. 3B, the silicon nitride films 13 ₁ , 13 ₂
After the etching is removed, a conductive polysilicon layer 15 is deposited by LPCVD so as to cover the conductive spacers 11a and 11b. Then, as shown in FIG.
The polysilicon layer 15 is etched back by the RIE method to form the conductive spacers 15a and 15b on the sidewalls of the conductive spacers 11a and 11b. After that, FIG. 3 (d)
, The conductive spacers 11a, 15a and 11
A source / drain diffusion layer 16 is formed by ion-implanting a dopant by a self-alignment method using b and 15b as a mask. An oxide film is formed on the exposed surfaces of the conductive spacers 15a and 15b. After that, a passivation film and the like are formed to form a semiconductor device using the conductive spacer as a gate electrode.

By the manufacturing process as described above, MOS type transistors having the conductive spacers 11a, 15a and 11b, 15b as gate electrodes, so-called spacers,
A gate transistor is formed. In this MOS type transistor, two elements adjacent to the minimum resolution dimension L are formed, and an element having a size half the conventional element size is formed. In addition, the conductive spacers 11a and 15a
Asymmetrical MOS transistors depending on the size of the width of the MOS transistor, or symmetric MO transistors if the conductive spacers have the same width.
An S transistor can be formed.

Next, another embodiment of the present invention will be described with reference to FIG.
It will be described based on. 4A is a cross-sectional view showing the manufacturing process following FIG. 2A, in which the resist mask is removed after the LTO film is removed, and as shown in FIG.
Silicon nitride films 8 ₁ , 8 by RIE or CDE
Remove ₂ . As shown in FIG. 4C, a conductive polysilicon layer 15 is deposited by the CVD method so as to cover the conductive spacers 11a and 11b. After that, FIG. 4 (d)
As shown in FIG. 3, the polysilicon layer 15 is etched back by the RIE method to form the conductive spacers 15a and 15b on the side walls of the conductive spacers 11a and 11b, respectively. Subsequently, as shown in FIG. 4E, a source / drain diffusion layer 16 is formed by ion implantation of a dopant by a self-alignment method using the conductive spacers 11a, 15a and 11b, 15b as a mask. In such a manufacturing process, the thermal oxide film 2 formed first is used as a gate oxide film, and the silicon nitride film covering the thermal oxide film 2 is formed to have a relatively large thickness. Of the conductive spacers 11a, 15a and 11b, 1
A spacer gate transistor having 5b as a gate electrode is formed.

Next, another embodiment of the present invention will be described with reference to FIG.
It will be described based on. Although the manufacturing process is substantially the same as the manufacturing process of FIGS. 1 to 3, an LTO film or the like is formed on the thermal oxide film 2 without forming a silicon nitride film as a protective film. Only the conductive spacers 11a and 11b are used as gate electrodes. As shown in FIG.
After patterning the resist film to form a resist mask 12 and exposing the LTO films 9 ₁ and 9 ₂ through the openings, as shown in FIG. 5B, LT is formed by RIE.
The O films 9 ₁ and 9 ₂ are removed. As shown in FIG. 5 (c),
By a self-alignment method using the conductive spacers 11a and 11b as a mask, a dopant is ion-implanted,
The source / drain diffusion layer 16 is formed. An oxide film is formed on the surfaces of the conductive spacers 11a and 11b simultaneously with the diffusion process. Although the protective film such as the nitride film is removed from the thermal oxide film 2 in the embodiment of FIG. 5, it is obvious that the LTO film may be deposited after forming the protective film.

Next, another embodiment of the present invention will be described with reference to FIG.
It will be described based on. The manufacturing process is the same as that of the embodiment of FIG. 5, but the LTO layers 9 ₁ and 9 ₂ are conductive polysilicon layers. As shown in FIG. 6A, the resist film is patterned to form a resist mask 12, and the conductive polysilicon layers 9 ₁ ′ and 9 ₂ ′ are selectively exposed through the openings of the resist mask 12. There is. As shown in FIG. 6B, by removing the conductive polysilicon layers 9 ₁ ′ and 9 ₂ ′ exposed from the resist mask 12, the conductive polysilicon layers 9 a are formed on the sidewalls of the conductive spacers 11 a and 11 b. , 9b are formed. After that, FIG.
As shown in (c), the source / drain diffusion layer 16 is formed by ion implantation of a dopant by a self-alignment method using the conductive spacers 11a and 11b and the conductive polysilicon layers 9a and 9b as a mask. It In this diffusion process, thermal oxide films are formed on the surfaces of the conductive spacers 11a and 11b and the conductive polysilicon layers 9a and 9b. In the case of this embodiment, the element interval L may be set to the minimum resolution dimension, and in this semiconductor device, the conductive spacer 11a and the conductive polysilicon layer 9a are used as the gate electrode.

Next, another embodiment of the present invention will be described with reference to FIG.
It will be explained based on. FIG. 7 shows a MOS transistor having a floating gate, in which a control gate layer is formed through a flattening process step of reducing the aspect ratio of the conductive spacer. FIG. 7A is a schematic diagram of FIGS.
7 shows a manufacturing process following the embodiment of FIG. 4 or FIG.
On the semiconductor substrate 1, the gate oxide film 2 is formed relatively thick and the gate oxide film 14 thinner than the thickness of the gate oxide film 2 is formed. These gate oxide films 2,
Conductive spacers 20 are formed on the surface 14. The conductive spacer 20 is one conductive spacer as in the above-described embodiment, one made of a conductive spacer and a conductive polysilicon layer, or a conductive layer made of one conductive spacer, and this conductive layer is used as a floating gate. To do. The source / drain diffusion layer 16 is formed by ion-implanting a dopant using the conductive spacer 20 as a mask. A silicon oxide film 20a is formed on the surface of the conductive spacer 20 by a diffusion process.

As shown in FIG. 7B, the LTO layer 17 is formed so as to cover the conductive spacers 20. Then, as shown in FIG. 7C, SOG (Spin
-on-Glass) layer 18 is formed. Subsequently, as shown in FIG. 7D, the SOG layer 18 is etched back by the RIE method. The oxide film 20a formed on the surface of the conductive spacer 20 is removed with diluted hydrogen fluoride water. The diluted hydrogen fluoride water etches the silicon oxide film 20a with a high selection ratio with respect to the polysilicon layer. Since the silicon oxide film 20a is removed, the tip of the conductive spacer 20 is scraped.
Although the residue 18a of the SOG layer is formed by the flattening process, it is desirable not to remain. After that, FIG.
After the ONO film 19 is deposited so as to cover the conductive spacers 20, as shown in FIG.
And the polycide layer 21 is patterned to form a control gate layer. As shown in FIG. 7, an insulating film is formed on the conductive spacers 20, and a conductive layer such as a polycide layer is formed on the insulating film to form a nonvolatile semiconductor memory element having a floating gate and a control gate. To be done. Such a spacer gate transistor can be used as an EPROM or a flash EEPROM.

In the spacer gate transistor as described above, 16 _D is a drain diffusion layer and 16 _S is a source diffusion layer as shown in the sectional view of FIG. For example, when the gate film thickness on one side is increased, the source is grounded, a voltage is applied to the drain, and a gate voltage is applied, it is difficult to form a channel on the drain side, a depletion layer a is formed, and a channel biased to the source side b is formed. A MOS transistor having a so-called diode structure is formed. Further, since the thickness of the gate electrode can be increased, the resistance of the gate electrode can be reduced. still,
By making the thicknesses of the gate oxide films equal, bilaterally symmetrical MOS type transistors can be formed.

As a matter of course, the source / drain diffusion layer is formed as shown in FIG.
As shown in FIG. 9A, the dopant may be injected perpendicularly to the semiconductor substrate using the conductive spacer 20 as a mask. However, as shown in FIG. 9B, the dopant is obliquely ion-implanted. By doing so, the source / drain diffusion layer can be deeply formed inside the channel, and the channel width can be narrowed. Also, by asymmetrically implanting the dopant into only one side, the asymmetric MO
An S-type transistor can be formed. Also, FIG.
As shown in (c) and (d), since the offset region is formed by obliquely implanting the dopant,
As a result, an offset gate type transistor or an offset gate type flash memory cell can be formed.

Next, another embodiment of the present invention, LDD
A MOS transistor having a (Lightly Doped Drain) structure will be described with reference to FIG. As shown in FIG. 10A, a dopant is ion-implanted using the conductive spacer 20 as a mask to form a shallow diffusion layer 22, and then a polysilicon layer 22 is formed as shown in FIG. 10B. . As shown in FIG. 10C, the polysilicon layer 22 is etched back by the RIE method to form the second spacers 22a and 22b on the arc-shaped portion of the conductive spacer 20. After that, the source / drain diffusion layers 16 _{D and} 16 _S are formed using the conductive spacers 20 and the second spacers 22a and 22b as masks, whereby the LDD structure MOS transistor is formed. Of course, by forming a control gate on the conductive spacers 20 and the spacers 22a and 22b, an M having a floating gate is formed.
An OS transistor can be formed. Of course, a conductive spacer on only one side as shown in FIG. 5 may be formed, and the conductive spacer may be formed on the arc-shaped portion of this conductive spacer to form a gate electrode or a floating gate.

Further, FIG. 11 shows a conductive spacer
An example is shown in which the side wall having conductivity and the oxide film are formed. In FIG. 11A, a thermal oxide film serving as a relatively thick gate oxide film is formed on a semiconductor substrate, a rectangular or strip-shaped LTO film 9 is formed, and a sidewall oxide film 23 having conductivity is formed on the side wall thereof. After the formation of the polysilicon, a polysilicon layer 24 is deposited. Thereafter, as shown in FIG. 11B, the polysilicon layer 24 is etched back by the RIE method to form the sidewall polysilicon layer 24.
a is formed. Then, as shown in FIG.
The TO film 9 is removed, the gate oxide film 14 is formed again, and the conductive sidewall / spacer oxide film 23b and the sidewall / polysilicon layer 24b are formed. Thus, the sidewall / spacer oxide films 23a, 23
Spacer gate transistors can be formed with b as the conductive spacer.

Needless to say, the LTO film of the above embodiment is not limited to the embodiment, but the vapor phase growth layer (HTO, High Temperation Oxide) at a temperature of 800 ° C. or lower, and the plasma C
A thin film formed by VD or a sputtering method, various thin film forming layers made of TEOS (tri-ethylene-ortho-silicate) or O ₃ -TEOS (tetraethoxysilane) system can be used. Also, except for the HTO film, the LTO film, plasma CVD, sputtering method, TEOS (tri-ethylene
A relatively high selectivity (etching rate) with respect to the thermal oxide film can be obtained during wet etching by using a thin film forming layer of ortho silicate) or O ₃ -TEOS (tetraethoxysilane). That is, the oxide film such as the LTO film to be removed can be removed quickly, and the lateral etching can be reduced. Further, by forming the thin film forming layer at a low temperature, it is possible to perform the next step without forming a protective film such as a silicon nitride film such as a gate oxide film. In the case of the HTO film, the gate oxide film may be damaged, so it is necessary to increase the thickness of the nitride film or the like to provide sufficient protection.

The semiconductor device of the present invention is a spacer gate transistor using a conductive spacer of various forms as described above as a gate electrode or a floating gate of a MOS type transistor, and manufacture of the semiconductor device of the present invention. According to the method, the gate width of the MOS transistor can be made narrower than the width of the conventional gate electrode without being restricted by the design rule. That is, if the distance L shown in the above embodiment is the same as the conventional gate width L, it is possible to form an element having a size approximately half that of the conventional MOS transistor. Needless to say, the inter-element distance L is not limited to the gate width L of the conventional MOS transistor. Also, the spacer gate transistor according to the present invention and the conventional MO
It is obvious that S transistors may be mixed to form a semiconductor device.

[0031]

As described above, according to the present invention, the MOS
Type so-called spacer gate transistor in which the gate electrode or floating gate of the transistor is formed of a conductive spacer or a conductive sidewall oxide film. It is easy to use a MOS transistor with a gate width narrower than the wiring width according to the design rules. There is an advantage that it can be formed.
Therefore, there is an effect that the degree of integration of the semiconductor device can be dramatically increased by the existing semiconductor manufacturing apparatus without being restricted by the design rule. Further, according to the present invention, since the element size can be made about half that of the conventional MOS type transistor, when it is used as a memory element of a semiconductor memory device or a non-volatile semiconductor memory device, the degree of integration of the memory element is dramatically increased. There is an effect that can be enhanced to.

Further, according to the present invention, if the gate electrode uses two conductive spacers, the film thickness of the gate oxide film immediately below one conductive spacer is increased and the film thickness of the other is decreased. Therefore, the resistance value of the gate electrode is reduced, and there is an advantage that a MOS transistor having high frequency characteristics can be formed. Further, since the offset portion can be easily formed by adjusting the width of the conductive spacer, the diode type MOS transistor can be easily formed. That is, it is possible to easily form a symmetrical or asymmetrical MOS type transistor or LDD structure MOS transistor having a small element size.

[Brief description of drawings]

1A to 1D are cross-sectional views of an embodiment of a method for manufacturing a semiconductor device according to the present invention.

2A to 2D are cross-sectional views showing the manufacturing process, following FIG. 1D.

3A to 3D are cross-sectional views showing the manufacturing process following FIG. 2D.

4A to 4E are cross-sectional views showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

5A to 5C are sectional views showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

6A to 6C are sectional views showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

7A to 7E are cross-sectional views showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view for explaining a spacer gate transistor.

FIG. 9 is a diagram showing a method of forming source / drain diffusion layers.

10A to 10C are cross-sectional views showing a spacer gate transistor having an LDD structure which is another embodiment of the method for manufacturing a semiconductor device according to the present invention.

11A to 11C are cross-sectional views showing a spacer gate transistor having a sidewall structure which is another embodiment of the method for manufacturing a semiconductor device according to the present invention.

12A to 12D are cross-sectional views showing a manufacturing process for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 Semiconductor Substrate 2 Thermal Oxide Film 8, 8 ₁ , 8 ₂ Silicon Nitride Film 9, 9 ₁ , 9 ₂ LTO Film (Thin Film Forming Layer) 10, 12 Resist Mask 11 Polysilicon Layer 11a, 11b Conductive Spacer 13, 13 ₁ , 13 ₂ Silicon nitride film 14 Thermal oxide film 15 Conductive polysilicon layers 15a, 15b Conductive spacer 16 Source / drain diffusion layer 16 _D Drain diffusion layer 16 _S Source diffusion layer 17 LTO film 18 SOG film 19 ONO film 20 Conductivity Spacer 20a Thermal oxide film 21 Polycide layer 22 Shallow diffusion layer 23a, 23b Sidewall / spacer oxide film 24a, 24b Sidewall / polysilicon layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (10)

[Claims] 1. A semiconductor device having a source / drain diffusion layer, wherein the gate electrode or the floating gate of the semiconductor device comprises a conductive spacer. 2. A semiconductor device having a source / drain diffusion layer, wherein the gate electrode or the floating gate of the semiconductor device comprises first and second conductive spacers in contact with each other. 3. The semiconductor device according to claim 2, wherein the first and second conductive spacers are composed of conductive sidewalls and an oxide film. 4. A semiconductor device having a source / drain diffusion layer, wherein the first and second conductive spacers are in contact with each other at a gate electrode or a floating gate of the semiconductor device, and the first and second conductive spacers. A semiconductor device comprising a third spacer and a fourth spacer respectively formed on the arcuate portion of the spacer. 5. A semiconductor device having a source / drain diffusion layer, comprising a gate oxide film formed on a surface of a semiconductor substrate, and first and second conductive spacers which are in contact with each other on the gate oxide film. A floating gate; a planarization treatment layer for reducing the aspect ratio of the first and second conductive spacers; an insulating film covering the planarization treatment layer and the first and second conductive spacers; A semiconductor device comprising a control gate layer formed on a film. 6. The semiconductor device according to claim 2, wherein the first and second gate oxide films formed under the first and second conductive spacers have different film thicknesses. 7. A method of manufacturing a semiconductor device, wherein the first gate oxide film formed on the surface of the semiconductor substrate comprises:
A rectangular thin film forming layer is formed, first conductive spacers are formed at both ends of the rectangular thin film forming layer, the rectangular thin film forming layer is removed, and then a second gate oxide film is formed. A second conductive spacer is formed on a sidewall of the first conductive spacer, and a source / drain diffusion layer is formed using the first and second conductive spacers as a mask. Device manufacturing method. 8. A method of manufacturing a semiconductor device, comprising: a thermal oxidation step of forming a thermal oxide film to be a gate oxide film on a surface of a semiconductor substrate; and a step of forming a thin film forming layer at a low temperature on the thermal oxide film. A patterning step of selectively etching the thin film forming layer to set an element spacing, depositing a first conductive layer covering the patterned thin film forming layer, and etching the first conductive layer. A step of forming a conductive spacer on the side wall of the thin film forming layer, and an etching step of removing all of the thin film forming layer or leaving a part of the vapor phase growth layer on the side wall of the conductive spacer. And a step of forming a source / drain diffusion layer using the conductive spacers or the like formed in the etching step as a mask, the method for manufacturing a semiconductor device. 9. A method of manufacturing a semiconductor device, comprising: forming a thermal diffusion layer to be a first gate oxide film on a surface of a semiconductor substrate; and forming a protective film such as a nitride film covering the thermal diffusion layer. A step of forming a thin film forming layer on the protective film, a patterning step of selectively etching the thin film forming layer to set an element interval, and a first conductive layer covering the patterned thin film forming layer. Depositing a layer, etching the first conductive layer to form first conductive spacers on both side walls of the thin film forming layer, and forming the thin film forming layer and the protective film thereunder. Removing the thermal oxide film to expose the surface of the semiconductor substrate; forming a thermal oxide film to serve as a second gate oxide film on the exposed semiconductor substrate; and the first conductive spacer. Second conductive layer covering the And a step of etching the second conductive layer to form a second conductive spacer on a sidewall of the first conductive spacer, and masking the first and second conductive spacers. And a diffusion step of forming a source / drain diffusion layer as described above, and a method for manufacturing a semiconductor device. 10. A method of manufacturing a semiconductor device, comprising the steps of forming a thermal oxide film to be a gate oxide film on the surface of a semiconductor substrate, and forming a protective film such as a nitride film covering the thermal oxide film. A step of depositing a thin film forming layer on the protective film, a patterning step of selectively etching the thin film forming layer to set element intervals, and a first conductive layer covering the patterned thin film forming layer And a step of etching the first conductive layer to form first conductive spacers on both side walls of the thin film forming layer, the thin film forming layer and the protective film and the gate oxide film below the thin film forming layer. Etching to remove the surface of the semiconductor substrate to expose the surface of the semiconductor substrate, a step of forming a thermal oxide film to be a second gate oxide film on the exposed semiconductor substrate, and a step of covering the first conductive spacer. First Depositing a second conductive layer; etching the second conductive layer to form a second conductive spacer on a sidewall of the first conductive spacer; and the first and second conductive layers. Process of forming a source / drain diffusion layer by ion-implanting a dopant using a conductive spacer as a mask, a planarizing process for reducing an aspect ratio of the first and second conductive spacers, and the planarizing process And a step of forming an insulating layer, and a step of patterning a conductive layer covering the insulating layer to form a control gate layer, the manufacturing method of the semiconductor device.