JPH07300337A - Crystalline low-melting glass for cover coat for thick-film electronic circuit - Google Patents
Crystalline low-melting glass for cover coat for thick-film electronic circuitInfo
- Publication number
- JPH07300337A JPH07300337A JP4001601A JP160192A JPH07300337A JP H07300337 A JPH07300337 A JP H07300337A JP 4001601 A JP4001601 A JP 4001601A JP 160192 A JP160192 A JP 160192A JP H07300337 A JPH07300337 A JP H07300337A
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- glass
- electronic circuit
- melting glass
- film electronic
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Classifications
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/12—Silica-free oxide glass compositions
- C03C3/253—Silica-free oxide glass compositions containing germanium
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/062—Glass compositions containing silica with less than 40% silica by weight
- C03C3/07—Glass compositions containing silica with less than 40% silica by weight containing lead
- C03C3/072—Glass compositions containing silica with less than 40% silica by weight containing lead containing boron
- C03C3/074—Glass compositions containing silica with less than 40% silica by weight containing lead containing boron containing zinc
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/12—Silica-free oxide glass compositions
- C03C3/14—Silica-free oxide glass compositions containing boron
- C03C3/142—Silica-free oxide glass compositions containing boron containing lead
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
- C03C8/02—Frit compositions, i.e. in a powdered or comminuted form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Geochemistry & Mineralogy (AREA)
- Materials Engineering (AREA)
- Organic Chemistry (AREA)
- Life Sciences & Earth Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Glass Compositions (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、厚膜電子回路のカバー
コートに適した結晶性低融点ガラスに関するものであ
り、さらに詳しくは、厚膜電子回路の抵抗値の変化を抑
制するカバーコート用結晶性低融点ガラスに関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystalline low melting point glass suitable for a cover coat of a thick film electronic circuit, and more particularly to a cover coat for suppressing a change in resistance value of the thick film electronic circuit. The present invention relates to a crystalline low melting point glass.
【０００２】[0002]
【従来の技術】周知のように、厚膜電子回路において
は、セラミック製の基板上に導体ペーストや抵抗体等を
印刷し、これを焼成した後、基板上の電子回路を保護す
るために基板表面にガラスカバーを形成する。2. Description of the Related Art As is well known, in thick film electronic circuits, a conductor paste, a resistor, etc. are printed on a ceramic substrate, and after firing this, the substrate is used to protect the electronic circuit on the substrate. Form a glass cover on the surface.
【０００３】従来、このような電子回路のカバーコート
用ガラスとしては、ＰｂＯ−Ｂ2 Ｏ 3 系の非晶質低融点
ガラスが用いられてきた。Conventionally, a cover coat for such an electronic circuit is used.
Glass for use is PbO-B2 O 3 Amorphous low melting point of the system
Glass has been used.
【０００４】しかし、近年、厚膜電子回路は高密度化の
傾向にあるため、各抵抗体や導体も小さくなりつつあ
る。その為、基板の熱膨張率と印刷焼成抵抗体の熱膨張
率との差により印刷焼成抵抗体中に応力が発生し、焼成
した後、抵抗体にマイクロクラックを生じ、その結果、
抵抗体の抵抗値が変化してしまうという問題が生じてい
る。However, in recent years, thick film electronic circuits have tended to have higher densities, so that the resistors and conductors are becoming smaller. Therefore, a stress is generated in the printed firing resistor due to the difference between the coefficient of thermal expansion of the substrate and the coefficient of thermal expansion of the printed firing resistor, and after firing, microcracks occur in the resistor, and as a result,
There is a problem that the resistance value of the resistor changes.
【０００５】[0005]
【発明が解決しようとする課題】本発明の課題は、厚膜
電子回路の抵抗値の変化を抑制することを特徴とする厚
膜電子回路のカバーコートに適したガラスを提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a glass suitable for a cover coat of a thick film electronic circuit, which is characterized by suppressing a change in resistance value of the thick film electronic circuit.
【０００６】[0006]
【課題を解決するための手段】本発明では、前記課題を
解決するために、ＰｂＯ ３１〜４９重量％、ＺｎＯ
３５〜５０重量％、Ｂ2 Ｏ3 １５〜２０重量％を
有し、さらにＧｅＯ2単独で３〜１０重量％もしくはＧ
ｅＯ2 とＳｉＯ2 の混合系で２〜１０重量％を含む組成
を主成分とする結晶性低融点ガラスを用いた。According to the present invention, in order to solve the above-mentioned problems, 31 to 49% by weight of PbO, ZnO
35 to 50% by weight, B 2 O 3 15 to 20% by weight, and GeO 2 alone 3 to 10% by weight or G
A crystalline low melting point glass whose main component is a composition containing 2 to 10% by weight of a mixed system of eO 2 and SiO 2 .
【０００７】ＰｂＺｎ2 Ｂ2 Ｏ6 の結晶相を持つ低融点
ガラスを得るために必要な酸化物組成は、ＰｂＯ：４
８．９８重量％、ＺｎＯ：３５．７１重量％、Ｂ2 Ｏ
3 ：１５．３０重量％となる。このような結晶相を得る
ためには、本質的に上記組成比が望ましい。しかし、前
記三元素だけでは、カバーコートガラスとして用いた際
に、ガラスの失透が起こり、下部の抵抗体のレーザトリ
ム時に支障を生じる。この失透を抑制するため、ガラス
ネットワークを強化して、過度の結晶化を抑制する元素
が必要となる。The oxide composition required for obtaining a low melting point glass having a crystal phase of PbZn 2 B 2 O 6 is PbO: 4.
8.98 wt%, ZnO: 35.71 wt%, B 2 O
3 : It becomes 15.30% by weight. In order to obtain such a crystal phase, the above composition ratio is essentially desirable. However, when only the above three elements are used, devitrification of the glass occurs when it is used as a cover coat glass, and an obstacle occurs during laser trimming of the resistor below. In order to suppress this devitrification, an element that strengthens the glass network and suppresses excessive crystallization is required.
【０００８】これに対して、本発明では、ＧｅＯ2 を用
いて結晶化ならびに失透を抑制することに成功した。ま
た、同様の効果をＧｅＯ2 とＳｉＯ2 の混合系において
も確認した。前記４元素（ＳｉＯ2 とＧｅＯ2 の混合系
の場合は５元素）を主成分とし、必要に応じて、ガラス
の着色の為にＣｒ2 Ｏ3 等の顔料を添加し、耐水性の向
上のためにＳｎＯ2 等を添加する。また、一般に結晶化
ガラスの融点は、非晶質ガラスの融点に比べて高温度で
ある。しかし、ＰｂＯ−ＺｎＯ−Ｂ2 Ｏ3 −ＧｅＯ2 系
のガラス粉末の結晶化速度を示差熱分析により測定し、
ＧｅＯ2 の増加に伴う結晶化温度の上昇を観察したとこ
ろ、ガラス組成を本発明の組成に限定することにより５
００−６００℃で焼成可能であることを見出した。On the other hand, the present invention succeeded in suppressing crystallization and devitrification by using GeO 2 . The same effect was also confirmed in a mixed system of GeO 2 and SiO 2 . The above 4 elements (5 elements in the case of a mixed system of SiO 2 and GeO 2 ) are the main components, and if necessary, a pigment such as Cr 2 O 3 is added for coloring the glass to improve the water resistance. Therefore, SnO 2 or the like is added. Further, the melting point of crystallized glass is generally higher than the melting point of amorphous glass. However, the crystallization rate of the glass powder of PbO-ZnO-B 2 O 3 -GeO 2 system was measured by differential thermal analysis,
Observation of an increase in crystallization temperature with an increase in GeO 2 revealed that the glass composition was limited to the composition of the present invention.
It has been found that firing is possible at 00-600 ° C.
【０００９】前記組成中のＺｎＯは、ガラスの結晶化の
必須元素であるが、その反応性のため、ＺｎＳｎＯ3 や
Ｚｎ2 ＳｎＯ4 のような結晶相も生成する。その結果、
目的とするＰｂＺｎ2 Ｂ2 Ｏ6 結晶相を確実に得るため
には、計算値（３５．７１重量％）以上が必要となる。
しかし、５０重量％付近より結晶化が極端に促進される
ので、３５〜５０重量％を使用範囲とする。ZnO in the above composition is an essential element for crystallization of glass, but due to its reactivity, it also forms a crystalline phase such as ZnSnO 3 or Zn 2 SnO 4 . as a result,
The calculated value (35.71% by weight) or more is required to reliably obtain the desired PbZn 2 B 2 O 6 crystal phase.
However, since crystallization is extremely accelerated from around 50% by weight, the range of use is 35 to 50% by weight.
【００１０】また、ＰｂＯは、ＺｎＯがＰｂＺｎ2 Ｂ2
Ｏ6 以外の結晶相にも使用されるため、計算値よりも少
ない量で使用可能である。ただし３１重量％以下では、
ガラスの結晶化温度が高くなりすぎて好ましくない。As for PbO, ZnO is PbZn 2 B 2
Since it is also used for a crystal phase other than O 6 , it can be used in an amount smaller than the calculated value. However, below 31% by weight,
The crystallization temperature of glass becomes too high, which is not preferable.
【００１１】また、Ｂ2 Ｏ3 は、ガラス中にあっても水
と容易に反応する為、耐湿性の向上のためには少ない方
が望ましい。しかし、融点を下げるフラックスとしても
作用するため、本発明のガラス使用温度範囲では１５〜
２０重量％が好ましい。Further, since B 2 O 3 easily reacts with water even in the glass, it is desirable that the amount is small in order to improve the moisture resistance. However, since it also acts as a flux for lowering the melting point, it is 15 to 15 in the glass operating temperature range of the present invention.
20% by weight is preferred.
【００１２】また、ＧｅＯ2 は、結晶化抑制効果を持っ
ており、適正な結晶化度合、ならびに透明度を得るため
には３−１０重量％の重量比が必要となる。この重量比
はモル数に換算すると、０．０３ｍｏｌｅ−０．１０ｍ
ｏｌｅに相当する（１００ｇのガラスの場合）。そし
て、ＧｅＯ2 とＳｉＯ2 の混合系においても、総量が同
モル数の範囲での使用が可能であり、これを重量％で示
すと、使用可能総量は２〜１０重量％である。GeO 2 has an effect of suppressing crystallization, and a weight ratio of 3 to 10% by weight is required to obtain an appropriate degree of crystallization and transparency. This weight ratio is 0.03 mole-0.10 m when converted to the number of moles.
Corresponds to ole (for 100 g of glass). Even in a mixed system of GeO 2 and SiO 2 , the total amount can be used within the range of the same number of moles. When this is expressed in weight%, the total usable amount is 2 to 10 weight%.
【００１３】本発明にかかる厚膜電子回路のカバーコー
ト用ガラスを製造するに当たっては、各成分の原料を配
合してバッチとし、１０００−１４００℃で１−２時間
加熱、溶融し、得られた溶融ガラスを水砕した後、粉砕
機により平均粒径２μｍ程度に微紛砕して粉末ガラスと
した。得られた粉末ガラスを溶媒およびビヒクルと混練
し、ペースト状として厚膜電子回路にスクリーン印刷
し、乾燥後、５００−６００℃で焼成し、溶解，結晶化
させた。In producing the glass for a cover coat of a thick film electronic circuit according to the present invention, raw materials of each component were blended into a batch, which was obtained by heating and melting at 1000-1400 ° C. for 1-2 hours. The molten glass was water-pulverized and then finely pulverized with a pulverizer to an average particle size of about 2 μm to obtain powder glass. The powder glass thus obtained was kneaded with a solvent and a vehicle, screen-printed as a paste on a thick film electronic circuit, dried and then baked at 500-600 ° C. for dissolution and crystallization.
【００１４】[0014]
【作用】厚膜電子回路における抵抗値変化の抑制は、抵
抗体のマイクロクラックを防止することにより実現でき
る。非晶質ガラスに比べ、本発明の結晶化ガラスは熱膨
張率が小さいため、本発明の結晶化ガラスを用いて厚膜
電子回路をカバーすれば、基板の熱膨張により生ずる応
力の集中を抑制することができ、抵抗体のマイクロクラ
ックを防止することが可能となる。The suppression of the resistance change in the thick film electronic circuit can be realized by preventing the microcracks of the resistor. Since the crystallized glass of the present invention has a smaller coefficient of thermal expansion than the amorphous glass, covering the thick film electronic circuit with the crystallized glass of the present invention suppresses the concentration of stress caused by the thermal expansion of the substrate. Therefore, it is possible to prevent the microcracks of the resistor.
【００１５】[0015]
（結晶生成状態の観察）表１に示す１２種の組成（実施
例１〜９、比較例１〜３）をもつ平均粒径２μｍのガラ
ス粉末と、エチルセルロースとα−ターピネオールから
成る有機バインダーを混合、分散させたペーストを作成
し、Ａｌ2 Ｏ3 基板（熱膨張係数約６０×１０-7 ℃-1
（５０−３５０℃））上にスクリーン印刷した。そし
て、その乾燥片を５００−６００℃の焼成温度にて焼成
し、走査形電子顕微鏡にて結晶の生成状態を観察し、そ
の失透の有無を表１に示した。(Observation of Crystal Formation State) Glass powder having an average particle diameter of 2 μm having 12 kinds of compositions shown in Table 1 (Examples 1 to 9 and Comparative Examples 1 to 3) and an organic binder composed of ethyl cellulose and α-terpineol were mixed. , A dispersed paste is prepared, and an Al 2 O 3 substrate (coefficient of thermal expansion of about 60 × 10 -7 ℃ -1
(50-350 ° C)). Then, the dried pieces were fired at a firing temperature of 500 to 600 ° C., and the state of crystal formation was observed with a scanning electron microscope, and the presence or absence of devitrification is shown in Table 1.
【００１６】（抵抗値の変化率測定）導体ペーストを印
刷、焼成したＡｌ2 Ｏ3 基板上に抵抗体を印刷、焼成し
た後、ＰｂＯ ３７．２７重量％、Ｂ2 Ｏ3 １６．８
５重量％、ＺｎＯ ３７．１８重量％、ＳｎＯ ２．８
３重量％、Ｃｒ2 Ｏ3 １．１０重量％、ＧｅＯ2 １．
８９重量％、ＳｉＯ2 １．３９重量％から本質的に成
るガラスペーストをスクリーン印刷し、試験片とした
（実施例２と同組成）。(Measurement of Rate of Change of Resistance Value) After printing and firing a conductor paste on which an Al 2 O 3 substrate was printed and fired, 37.27% by weight of PbO and 16.8 of B 2 O 3 were added.
5% by weight, ZnO 37.18% by weight, SnO 2.8
3% by weight, Cr 2 O 3 1.10% by weight, GeO 2 1.
A glass paste essentially consisting of 89% by weight and 1.39% by weight of SiO 2 was screen-printed to give a test piece (same composition as in Example 2).
【００１７】また、これと比較するために、ＰｂＯ ６
０．４重量％、Ｂ2 Ｏ3 １１．４重量％、ＳｉＯ2
１８．２重量％から本質的に成るガラスペーストを用い
て同様に試験片を作成した（比較例４）。For comparison with this, PbO 6
0.4% by weight, B 2 O 3 11.4% by weight, SiO 2
A test piece was likewise prepared with a glass paste consisting essentially of 18.2% by weight (Comparative Example 4).
【００１８】抵抗体は、０．８×０．８ｍｍ、１．０×
１．０ｍｍ，２．０×２．０ｍｍの３種類の大きさのも
のを、各測定抵抗値に対して各１０個使用した。測定抵
抗値は、厚膜抵抗の一般的範囲である１．５Ωから１Ｍ
Ωまでとし、その間の値として、３．０Ω、１０Ω、１
００Ω、１ＫΩ、１０ＫΩ、１００ＫΩを採用した。The resistor is 0.8 × 0.8 mm, 1.0 ×
Ten pieces of three sizes of 1.0 mm and 2.0 × 2.0 mm were used for each measured resistance value. The measured resistance value is 1.5Ω which is a general range of thick film resistance to 1M.
Up to Ω, and values in between are 3.0Ω, 10Ω, 1
00Ω, 1KΩ, 10KΩ and 100KΩ were adopted.
【００１９】それぞれの試験片を−４０℃〜１５０℃の
冷熱サイクル中に１０００サイクル放置し、抵抗値の変
化率を測定した。測定結果は、表２に示すように、抵抗
値の変化率が１％以上であった抵抗体の数で表した。Each test piece was allowed to stand for 1000 cycles during a cooling / heating cycle of -40 ° C. to 150 ° C., and the rate of change in resistance value was measured. As shown in Table 2, the measurement results are represented by the number of resistors whose resistance change rate was 1% or more.
【００２０】同様に作成した試験片を、１５０℃の条件
下に１０００時間放置した場合と、８５℃、湿度８５％
の条件下に１０００時間放置した場合についても抵抗値
の変化率を測定し、それぞれ表３，表４に示した。A test piece prepared in the same manner was left under the condition of 150 ° C. for 1000 hours and at 85 ° C. and a humidity of 85%.
The rate of change in resistance value was measured also when the sample was left for 1000 hours under the conditions described in Table 3 and Table 4, respectively.
【００２１】[0021]
【表１】 [Table 1]
【００２２】[0022]
【表２】 [Table 2]
【００２３】[0023]
【表３】 [Table 3]
【００２４】[0024]
【表４】 [Table 4]
【００２５】[0025]
【発明の効果】本発明の結晶性低融点ガラスを厚膜電子
回路のカバーガラスとして用いることによって、厚膜電
子回路の抵抗値の変化を抑制することができるようにな
り、厚膜電子回路の高密度化に対応できる。By using the crystalline low melting point glass of the present invention as a cover glass for a thick film electronic circuit, it becomes possible to suppress a change in the resistance value of the thick film electronic circuit. It can handle high density.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中川 聖一 神奈川県横浜市港北区新吉田町4997 デュ ポン ジャパン リミテッド 中央技術研 究所内 (72)発明者 バリー イー テイラー 神奈川県横浜市港北区新吉田町4997 デュ ポン ジャパン リミテッド 中央技術研 究所内 (72)発明者 ジェローム デー スミス 神奈川県横浜市港北区新吉田町4997 デュ ポン ジャパン リミテッド 中央技術研 究所内 (72)発明者 長坂 崇 愛知県刈谷市昭和町１丁目１番地 日本電 装株式会社内 (72)発明者 大谷 祐司 愛知県刈谷市昭和町１丁目１番地 日本電 装株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiichi Nakagawa 4997 Shinyoshida-cho, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture DuPont Japan Limited Central Research Institute (72) Inventor Barry E. Taylor Shinyoshida, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Machi 4997 DuPont Japan Limited Central Technical Research Laboratory (72) Inventor Jerome Day Smith 4997 Shinyoshida-cho, Kohoku Ward, Yokohama City, Kanagawa Prefecture 4997 DuPont Japan Limited Central Technical Research Laboratory (72) Inventor Takashi Nagasaka Showa, Kariya City, Aichi Prefecture 1-chome, Nihon Denso Co., Ltd. (72) Inventor Yuji Otani 1-1, Showa-cho, Kariya city, Aichi Nihon Denso Co., Ltd.
Claims (3)
融点ガラス。1. A crystalline low melting point for a cover coat of a thick film electronic circuit, which is mainly composed of PbO 31 to 49% by weight ZnO 35 to 50% by weight B 2 O 3 15 to 20% by weight GeO 2 3 to 10% by weight. Glass.
融点ガラス。2. A cover for a thick film electronic circuit containing PbO 31-49% by weight ZnO 35-50% by weight B 2 O 3 15-20% by weight a mixture of GeO 2 and SiO 2 2-10% by weight as a main component. Crystalline low melting point glass for coating.
量％以下のＣｒ2 Ｏ3 とを含有することを特徴とする請
求項１または２に記載の厚膜電子回路のカバーコート用
結晶性低融点ガラス。3. The crystal for cover coat of a thick film electronic circuit according to claim 1, further comprising 3 wt% or less of SnO 2 and 3 wt% or less of Cr 2 O 3. Low melting point glass.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04001601A JP3105979B2 (en) | 1992-01-08 | 1992-01-08 | Crystalline low melting point glass for cover coating of thick film electronic circuits |
| DE69300110T DE69300110T2 (en) | 1992-01-08 | 1993-01-06 | Partially crystallizable low-melting glass composition. |
| KR1019930000111A KR950014693B1 (en) | 1992-01-08 | 1993-01-07 | Partially crystallizable low melting glass |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04001601A JP3105979B2 (en) | 1992-01-08 | 1992-01-08 | Crystalline low melting point glass for cover coating of thick film electronic circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07300337A true JPH07300337A (en) | 1995-11-14 |
| JP3105979B2 JP3105979B2 (en) | 2000-11-06 |
Family
ID=11506024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04001601A Expired - Fee Related JP3105979B2 (en) | 1992-01-08 | 1992-01-08 | Crystalline low melting point glass for cover coating of thick film electronic circuits |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3105979B2 (en) |
| KR (1) | KR950014693B1 (en) |
| DE (1) | DE69300110T2 (en) |
-
1992
- 1992-01-08 JP JP04001601A patent/JP3105979B2/en not_active Expired - Fee Related
-
1993
- 1993-01-06 DE DE69300110T patent/DE69300110T2/en not_active Expired - Lifetime
- 1993-01-07 KR KR1019930000111A patent/KR950014693B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930016361A (en) | 1993-08-26 |
| KR950014693B1 (en) | 1995-12-13 |
| DE69300110T2 (en) | 1995-10-26 |
| JP3105979B2 (en) | 2000-11-06 |
| DE69300110D1 (en) | 1995-05-24 |
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