JPH0729984A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a fluctuation in the potential of an interconnection for supplying standard voltage without increasing power consumption and a chip area. CONSTITUTION:In a multilayer interconnection ECL IC, an interconnection 2 for supplying reference voltage VREF which is formed with a second-layer metal film and an interconnection 3 for supplying ground power supply voltage which is formed with a third-layer metal film are so located as to overlap each other. An MIM capacitor is fabricated with the overlapped parts of the interconnections 2, 3 and an interlayer insulating film formed between the interconnections 2 and 3. Using this MIM capacitor, a fluctuation in the potential of the interconnection 2 when a gate circuit is switched is prevented and thereby reference voltage VREF is supplied stably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, an emitter-coupled logic IC (hereinafter "ECL").
It is suitable for application to "IC").

[0002]

2. Description of the Related Art ECL ICs are widely used in large-scale computers and the like as bipolar digital ICs that can operate at high speed and can be easily highly integrated, and research and development are being actively conducted.

FIG. 5 shows an example of a gate circuit of a conventional ECL IC, which is an example of a 3-input gate circuit. 5, the differential amplifier is constituted by transistors Q ₁₁ to Q ₁₃ and the transistor Q _14. Transistor Q ₁₁ ~
An input signal is supplied to each base of Q ₁₃ , while a predetermined reference voltage V _REF generated by a bias circuit (reference voltage circuit) not shown is supplied to the base of the transistor Q ₁₄ . A power supply voltage V _CC = 0V (ground power supply voltage) is supplied to the collectors of the transistors Q _{11 to} Q ₁₃ via a load resistor R ₁₁ and to the collector of the transistor Q ₁₄ via a load resistor R _12. To be done. It is commonly connected to the respective emitters and emitter of the transistor Q ₁₄ of the transistor Q ₁₁ to Q _13, the constant current circuit consisting of a common emitter connected to the transistors Q ₁₅ load resistor R ₁₃ Metropolitan is connected. One end of the load resistor R ₁₃ has a negative power supply voltage V _EE (for example, -5.2).
V) is supplied. A constant voltage according to a desired constant current is supplied to the base of the transistor Q ₁₅ .

[0004] transistor Q ₁₁ output of the inverter consisting to Q ₁₃ and the load resistor R ₁₁ Metropolitan is supplied to the base of the transistor Q ₁₆ constituting an emitter follower circuit, the line adjustment of the power amplifier and the output level by the transistor Q ₁₆ Be seen. Similarly, the output of the inverter composed of the transistor Q ₁₄ load resistor R ₁₂ Metropolitan is supplied to the base of the transistor Q ₁₇ constituting an emitter follower circuit, the adjustment of the power amplifier and the output level is performed by the transistor Q _17. The negative power supply voltage V _EE is supplied to the emitters of the transistors Q ₁₆ and Q ₁₇ via load resistors R ₁₄ and R ₁₅ , respectively. In this case, the OR output is taken out from the emitter of the transistor Q _{17 and} the NOR output is taken out from the emitter of the transistor Q ₁₆ .

In the gate circuit shown in FIG. 5 configured as described above, when a voltage sufficiently higher than the reference voltage V _REF is input to any one of the bases of the transistors Q _{11 to} Q ₁₃ , the transistor becomes conductive. Then, the emitter current determined by the constant current circuit composed of the transistor Q ₁₅ and the load resistor R ₁₃ flows, while the transistor Q ₁₄ is cut off. In addition, all the voltages input to the bases of the transistors Q _{11 to} Q ₁₃ are the reference voltage V _REF.
These transistors Q ₁₁ ~
Q ₁₃ is cut off, while the transistor Q ₁₄ is turned on and the emitter current determined by the constant current circuit composed of the transistor Q ₁₅ and the load resistor R ₁₃ flows. That is,
Depending on whether the transistor Q ₁₁ to Q voltage input to the base ₁₃ is sufficiently high or sufficiently lower than the reference voltage V _REF, the switching of the emitter current between transistors Q ₁₁ to Q ₁₃ and the transistor Q ₁₄ Done.

[0006]

By the way, large-scale E
In the CLIC, when the emitter current is switched in the gate circuit, that is, when the gate circuit is switched, a large amount of current may flow through the wiring for supplying the reference voltage V _REF . Therefore, the reference voltage V
There has been a problem that the potential of the wiring for supplying _REF changes greatly, and as a result, the noise margin (noise margin) decreases and the gate delay time t _pd changes.

For example, FIG. 6 shows an example of the measurement result of the input / output characteristics of the gate circuit of the conventional ECL IC. From this, the reference voltage V _REF greatly increases when the input signal rises from the low level to the high level. You can see that This increase in the reference voltage V _REF causes an increase in the gate delay time t _pd .

In order to suppress the fluctuation of the potential of the wiring for supplying the reference voltage V _REF as described above, the power of the bias circuit for generating the reference voltage V _REF is raised or the reference voltage V _{REF is changed.}
It is conceivable to increase the width of the supply wiring to lower its impedance.
This is not preferable because it increases the power consumption of the CLIC and the chip area.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing the fluctuation of the potential of the wiring for supplying the reference voltage without increasing the power consumption and the chip area. .

[0010]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention has a wiring (2) for supplying a reference voltage and a power supply which are electrically insulated from each other by an interlayer insulating film (4). The wiring (3) for voltage supply is provided so that at least a part thereof overlaps each other, and the wiring (2) for supplying the reference voltage, the interlayer insulating film (4), and the wiring (3 for power supply voltage) of the overlapping portion are provided. And) form a capacitor (C ₁ ).

In a preferred embodiment of the semiconductor integrated circuit device according to the present invention, the power supply voltage supply wiring (3) is a ground power supply voltage supply wiring.

In a preferred embodiment of the semiconductor integrated circuit device according to the present invention, the wiring (2) for supplying the reference voltage and the wiring (3) for supplying the power supply voltage are formed of a metal such as aluminum or aluminum alloy.

A semiconductor integrated circuit device according to the present invention is, for example, an ECL IC and has a wiring (2) for supplying a reference voltage.
Is for supplying the reference voltage of the gate circuit, and the wiring (3) for supplying the power supply voltage is for supplying the ground power supply voltage of the gate circuit.

[0014]

According to the semiconductor integrated circuit device of the present invention configured as described above, even if the potential of the reference voltage supply wiring (2) is varied, the reference voltage supply wiring (2) is generated. Since the capacitor (C ₁ ) formed by the interlayer insulating film (4) and the power supply voltage supply wiring (3) acts to stabilize the potential of the reference voltage supply wiring (2), the reference voltage The fluctuation of the potential of the supply wiring (2) can be suppressed. For example, in the ECL IC, even when a large amount of current flows through the reference voltage supply wiring (2) when the gate circuit is switched, the reference voltage supply wiring (2), the interlayer insulating film (4), and the power supply voltage supply are supplied. By the action of the capacitor (C ₁ ) formed by the wiring (3) for supplying the voltage, it is possible to suppress the fluctuation of the potential of the wiring (2) for supplying the reference voltage.

As described above, the fluctuation of the potential of the wiring for supplying the reference voltage can be suppressed without increasing the power consumption and the chip area.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an ECL IC will be described below with reference to the drawings. FIG. 1 shows a gate circuit of an ECL IC according to an embodiment of the present invention, which is an example of a 3-input gate circuit.

In FIG. 1, transistors Q _{1 to} Q ₃ and transistor Q ₄ form a differential amplifier. To the respective bases of the transistors Q ₁ to Q ₃ are the input signal is supplied, whereas, on the base of the transistor Q ₄ are predetermined reference voltage V _REF generated by a bias circuit not shown is supplied. Each of the collectors of the transistors Q _{1 to} Q ₃ is connected via a load resistor R _1, and the collector of the transistor Q ₄ is connected via a load resistor R ₂ .
Power supply voltage V _CC = 0V (ground power supply voltage) is supplied to each. It is commonly connected to the respective emitters and emitter of the transistor Q ₄ of the transistor Q ₁ to Q _3, a constant current circuit consisting of a common emitter connected to the transistors Q ₅ load resistance R ₃ Metropolitan is connected. One end of the load resistor R ₃ has a negative power supply voltage V _EE (for example, -5.2).
V) is supplied. Further, a constant voltage according to a desired constant current is applied to the base of the transistor Q ₅ .

The output of the inverter composed of the transistors Q ₁ to Q ₃ load resistor R ₁ Metropolitan is supplied to the base of the transistor Q ₆ constituting the emitter follower circuit, the line adjustment of the power amplifier and the output level by the transistor Q ₆ Be seen. Similarly, the output of the inverter composed of the transistors Q ₄ load resistor R ₂ Metropolitan is supplied to the base of the transistor Q ₇ constituting the emitter follower circuit, the adjustment of the power amplifier and the output level is performed by the transistor Q _7. The negative power supply voltage V _EE is supplied to the emitters of the transistors Q ₆ and Q ₇ via load resistors R ₄ and R ₅ , respectively. In this case, the OR output is taken out from the emitter of the transistor Q _{7 and} the NOR output is taken out from the emitter of the transistor Q ₆ .

The above-mentioned configuration is the conventional ECL shown in FIG.
Similar to the IC gate circuit, but in this embodiment, in addition to this, a wiring for supplying the reference voltage V _REF to the base of the transistor Q ₄ and V _CC = 0V, that is, a ground power supply voltage is supplied. The capacitor C ₁ is connected in parallel between the wiring and the wiring. Further, in this case, the capacitor C ₂ is also connected in parallel between the wiring for supplying the voltage to the base of the transistor Q ₅ forming the constant current circuit and the wiring for supplying the power supply voltage V _EE . .

In the gate circuit shown in FIG. 1 constructed as described above, like the gate circuit of the conventional ECL IC shown in FIG. 5, the reference voltage V _{REF is} applied to any one of the bases of the transistors Q _{1 to} Q _3. When a voltage sufficiently higher than that is input, the transistor becomes conductive and the emitter current determined by the constant current circuit consisting of the transistor Q ₅ and the load resistor R ₃ flows, while the transistor Q ₄ is cut off. In addition, all the voltages input to the bases of the transistors Q _{1 to} Q ₃ are the reference voltage V _REF.
These transistors Q ₁ ~
Q ₃ is cut off, while transistor Q ₄ is conducting and an emitter current determined by the constant current circuit consisting of transistor Q ₅ and load resistor R ₃ flows. That is,
Depending on whether the transistor Q ₁ voltage input to the base of the to Q ₃ is sufficiently high or sufficiently lower than the reference voltage V _REF, the switching of the emitter current between transistors Q ₁ to Q ₃ and the transistor Q ₄ Done.

FIG. 2 shows an essential part of an example of the structure of the ECL IC according to this embodiment, and particularly shows a wiring layout pattern.

In a large-scale ECL IC, a multilayer wiring of three layers or more is usually used to secure a wiring for supplying a ground power supply voltage capable of flowing a large current, but in this embodiment, , The above-mentioned capacitors C ₁ and C ₂ are formed by utilizing this multilayer wiring.

That is, in FIG. 2, reference numeral 1 is a wiring for supplying the power supply voltage V _EE , 2 is a wiring for supplying the reference voltage V _REF , and 3 is a wiring for supplying the ground power supply voltage. in this case,
The wiring 1 for supplying the power supply voltage V _EE is made of the first metal film,
The wiring 2 for supplying the reference voltage V _REF is formed of the second layer metal film, and the wiring 3 for supplying the ground power supply voltage is formed of the third layer metal film. As the metal film, specifically, for example, an aluminum film or an aluminum alloy film is used.

In this case, the wiring 3 for supplying the ground power supply voltage
_Are provided so as to cover the wiring 2 for supplying the reference voltage V _REF . FIG. 3 is a cross section taken along line 3-3 of FIG. 2, showing a laminated structure of a portion in which the wiring 3 for supplying the ground power supply voltage and the wiring 2 for supplying the reference voltage V _REF overlap each other. . In FIG. 3, reference numeral 4 denotes an interlayer insulating film for electrically insulating the wiring 3 for supplying the ground power supply voltage and the wiring 2 for supplying the reference voltage V _REF from each other. As shown in FIG. 3, in this case, the wiring 2 for supplying the reference voltage V _REF , the interlayer insulating film 4, and the wiring 3 for supplying the ground power supply voltage are metal-
A capacitor having an insulator-metal (MIM) structure is formed, and the MIM capacitor constitutes the capacitor C ₁ shown in FIG.

Specifically, the capacitance of the capacitor C ₁ formed by this MIM capacitor is as follows, for example.

Now, assuming that the wiring 2 for supplying the reference voltage V _REF has a width of 12.8 μm and a length of 5500 μm (5.5 mm), the wiring 2 for supplying the reference voltage V _REF , the interlayer insulating film 4 and the ground. The capacitance value of the MIM capacitor formed by the wiring 3 for supplying the power supply voltage is 0.9 pF per 1 mm of the length of the wiring 2 for supplying the reference voltage V _REF . In addition, the decoupling capacitance of one gate bench is (0.9 pF / mm) × 5.5 mm = 4.95 pF. However, as the interlayer insulating film 4, a Si ₃ N ₄ film formed by the low pressure CVD method was used.

When V _EE = -5.2V, the power consumption of the whole chip is 8.9W, of which the power consumption of the bias circuit is 1.3W, which is about 14% of the power consumption of the whole chip. is there. On the other hand, in order to suppress the fluctuation of the reference voltage V _REF , it is necessary to increase the power of the bias circuit to cope with the fluctuation of the reference voltage V _REF without providing the capacitor C ₁ formed of the MIM capacitor as in this embodiment.
The power consumption of the bias circuit increases to about 2.3 W, and the power consumption of the entire chip increases to about 9.9 W.

[0028] Figure 4, this was connected to a capacitor C ₁ consisting of MIM capacitor between the reference voltage V _REF supply wiring 2 and the ground power supply voltage line 3 for supplying to suppress variation in reference voltage V _REF An example of the measurement result of the input / output characteristics when 40 gate circuits according to an embodiment are simultaneously switched is shown. However, as shown in the inset diagram of FIG. 4, as the MIM capacitor forming the capacitor C ₁ , four MIM capacitors each having a capacitance of ₁ pF were connected in parallel to make a total of 4 pF.

As can be seen by comparing FIG. 4 with FIG. 6, the capacitor C _{1 formed} of an MIM capacitor is connected between the wiring 2 for supplying the reference voltage V _REF and the wiring 3 for supplying the ground power supply voltage. In the gate circuit according to the embodiment, the fluctuation of the reference voltage V _REF when the gate circuit is switched is suppressed to be extremely small as compared with the conventional gate circuit in which the capacitor C ₁ is not connected.

In this embodiment, the capacitor C ₂ connected between the wiring for supplying the voltage to the base of the transistor Q ₅ constituting the constant current circuit and the wiring 1 for supplying the power source voltage V _EE is also MIM. It is composed of a capacitor. Although illustration is omitted, in this case, the wiring for supplying voltage to the base of the transistor Q ₅ is formed by the second-layer metal film, and the base of the transistor Q ₅ formed by the second-layer metal film is formed. A wiring for supplying a voltage to the power supply voltage V _EE and a wiring for supplying a power supply voltage V _EE are provided so that at least a part thereof overlaps with each other, and an MIM capacitor can be formed by these wiring and an interlayer insulating film between them. , This MIM capacitor makes the capacitor C ₂
Can be configured. Since the capacitor C ₂ is connected between the wiring for supplying the voltage to the base of the transistor Q ₅ and the wiring 1 for supplying the power supply voltage V _EE, which constitutes the constant current circuit, the transistor Q ₂ is connected.
The fluctuation of the voltage supplied to the base of ₅ can be suppressed.

As described above, according to this embodiment, the wiring 3 for supplying the ground power supply voltage formed of the third layer metal film and the reference voltage V _REF formed of the second layer metal film.
Supply wiring 2 is provided so as to overlap with each other, and M is formed by the wiring 2 for supplying the reference voltage V _REF , the interlayer insulating film 4 and the wiring 3 for supplying the ground power supply voltage in the overlapping portion.
Since the IM capacitor constitutes the capacitor C ₁ shown in FIG. 1, the action of the capacitor C ₁ causes the reference voltage V when the gate circuit is switched.
The fluctuation of _REF can be effectively suppressed. As a result, stable operation and high-speed operation of the ECL IC can be realized without increasing the power consumption of the ECL IC and the chip area.

Although one embodiment of the present invention has been specifically described above, the present invention is not limited to the above embodiment, and various modifications can be made based on the technical idea of the present invention. .

For example, although the case where the present invention is applied to the ECL IC has been described in the above-mentioned one embodiment, the present invention is directed to another semiconductor using a wiring for supplying a reference voltage and a wiring for supplying a power supply voltage. Integrated circuit device, eg M
It can also be applied to an OS static RAM or the like.

[0034]

As described above, according to the present invention,
It is possible to realize a semiconductor integrated circuit device capable of suppressing the fluctuation of the potential of the wiring for supplying the reference voltage without increasing the power consumption and the chip area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a gate circuit of an ECL IC according to an embodiment of the present invention.

FIG. 2 is a plan view showing a main part of an example of the structure of the ECL IC according to the embodiment of the present invention.

FIG. 3 is an enlarged sectional view taken along line 3-3 of FIG.

FIG. 4 is a graph showing an example of measurement results of input / output characteristics of a gate circuit of an ECL IC according to an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a gate circuit of a conventional ECL IC.

FIG. 6 is a graph showing an example of measurement results of input / output characteristics of a gate circuit of a conventional ECL IC.

[Explanation of symbols]

2 Wiring for supplying reference voltage V _REF 3 Wiring for supplying ground power supply voltage 4 Interlayer insulating film C ₁ , C ₂ Capacitor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 8832-4M H01L 27/04 C

Claims (4)

[Claims] 1. A wiring for supplying a reference voltage and a wiring for supplying a power supply voltage, which are electrically insulated from each other by an interlayer insulating film, are provided so as to at least partially overlap with each other, and the reference voltage in the overlapping portion. A semiconductor integrated circuit device in which a capacitor is formed by a supply wire, the interlayer insulating film, and the power supply voltage supply wire. 2. The semiconductor integrated circuit device according to claim 1, wherein the wiring for supplying the power supply voltage is a wiring for supplying the ground power supply voltage. 3. The semiconductor integrated circuit device according to claim 1, wherein the wiring for supplying the reference voltage and the wiring for supplying the power supply voltage are formed of metal. 4. The semiconductor integrated circuit device is an ECL IC
The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein