JPH0729931U - Signal level monitoring circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] The signal level is judged to be normal only when the input signal is at the same level for a preset time or longer by monitoring both the "H" length and the "L" length. To do. [Structure] A first frequency dividing circuit 1 and a second frequency dividing circuit 2 having the same structure are provided, and a clock pulse CK is inputted to each of them. A circuit 3 is provided which is set by the output of the first frequency dividing circuit 1 and reset by the output of the second frequency dividing circuit 2. Further, the input signal IN resets the first frequency divider circuit 1, and the inverted signal of the input signal IN resets the second frequency divider circuit 2. With the above configuration, the first frequency dividing circuit 1 and the second frequency dividing circuit 2
Monitor the input signal IN when it is "H" and "L"
Each time is monitored.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a signal level monitoring circuit that outputs a detection signal when a signal level input to a logic circuit in an electronic device becomes “H” or “L”.

[0002]

[Prior art]

 Conventionally, as a circuit that monitors the signal level, the signal level is sampled multiple times by the sampling clock, and the level of the input signal is detected by whether or not the signal level continuously matches the number of times of sampling. It was FIG. 5 shows a timing chart of a conventional signal level monitoring circuit. When the signal level becomes "H", the data is sampled a plurality of times (twice in this example) by the sampling clock, and if all the results are "H", it is determined that the input signal is "H".

[0003]

[Problems to be solved by the device]

 However, in the above method, as shown on the right side of FIG. 5, when the signal level is generated as, for example, when noise is accidentally input twice or more every sampling period, this conventional signal level monitoring is performed. In the circuit, there is a problem in that all input signal levels become "H" at successive sampling timings, and therefore it is erroneously determined that a correct input signal has been input.

An object of the present invention is to monitor a signal level of "H" and "L" so that a normal signal level is obtained only when an input signal is at the same level for a preset time or longer. It is to provide a signal level monitoring circuit for determining.

[0005]

[Means for Solving the Problems]

 FIG. 1 is a block diagram of a signal level monitoring circuit according to the present invention.

The clock pulse CK for sampling the input signal is input to the first frequency dividing circuit 1 and the second frequency dividing circuit 2, and the output of the first frequency dividing circuit 1 is a direct set of the flip-flop 3. The output of the second frequency dividing circuit 2 is input to the direct reset terminal of the flip-flop 3. The input signal IN and its inverted signal are input to the first frequency dividing circuit 1 and the second frequency dividing circuit 2 as reset signals, respectively. The frequency division ratios of the first frequency dividing circuit 1 and the second frequency dividing circuit 2 are the same.

[0007]

[Action]

 In the above configuration, when the input signal IN is "H", it is in an active state. When the input signal IN is "L", that is, inactive, the first frequency dividing circuit 1 is in the reset state, and the second frequency dividing circuit 2 keeps counting the clock pulse CK. In this state, when the input signal IN becomes "H", that is, the active state, the first frequency dividing circuit 1 starts frequency division. When the first frequency dividing circuit 1 counts the clock pulse CK for a certain period of time, the flip-flop 3 is set by its output. At this time, the second frequency dividing circuit 2 is in the reset state. Then, when the input signal IN changes from "H" to "L" and this state is maintained, the first frequency dividing circuit 1 is reset and the second frequency dividing circuit 2 counts the clock pulse CK. Therefore, if the input signal IN is kept at "L" until the output of the second frequency dividing circuit 2 is output, the flip-flop 3 is reset and the output falls to "L".

By the above operation, when noise or the like does not occur on the input signal IN, the output of the flip-flop 3 also changes to “H” or “L” according to the level of IN. When IN drops to "L" due to noise or the like while maintaining "H", the first frequency dividing circuit 1 is immediately reset and the second frequency dividing circuit 2 starts counting. When IN returns to "H" again, the second frequency dividing circuit 2 is immediately reset and its output does not appear at the terminal R of the flip-flop 3. Since the flip-flop 3 maintains the state until then, unless the output from the second frequency divider circuit 2 is output, even if a short-time signal such as noise is input to the input IN, the output is You will not be affected.

Since the first frequency dividing circuit 1 and the second frequency dividing circuit 2 have the same frequency division ratio, the monitoring characteristics when the input signal is active and when the input signal is inactive are Will be the same.

[0010]

【Example】

 FIG. 2 shows a circuit diagram of an embodiment of the present invention.

In this embodiment, the first frequency dividing circuit 1 is formed by connecting the D flip-flop FF1 to the T-type flip-flop, connecting the two stages, and further outputting the output of the second stage FF1. It is configured by being connected to a clock input terminal of a 3-stage D-type flip-flop FF1. The D terminal of the third FF1 is fixed to the "H" level in order to prevent the FF1 from performing the toggle operation.

The second flip-flop circuit 2 is also composed of three D-type flip-flops FF1 similarly to the first frequency dividing circuit 1. The input signal IN is connected to the reset terminal of each flip-flop of the first frequency dividing circuit 1, and the inverted signal of IN is connected to the reset terminal of each FF1 of the second frequency dividing circuit 2.

FIG. 3 shows a timing chart of the signal level monitoring circuit shown in FIG.

When the input signal IN is in the non-active state (“L”), the outputs EP1 and EP2 of each FF1 of the first frequency dividing circuit 1 do not toggle and the output ES of the third stage FF1 is Stay inactive. On the other hand, the outputs EN1 and EN2 of each FF1 of the second frequency dividing circuit 2 are toggled, the output ER of the third stage FF1 is in the active state, and FF2 is reset to set Q0 to "L".

In, when IN becomes “H”, that is, when it becomes active, this time, EP1 and EP2 start the toggle operation, ES becomes active at the time of, and Q0 becomes “H”. At this time, since each FF1 of the second frequency dividing circuit 2 is reset, ER is in the "H" non-active state. Until the point of time, EP1 and EP2 continue the toggle operation, and ES keeps the active state.

On the other hand, during the period from to, the input signal IN changes to "L" three times as shown in a to c, but the ER output of the second frequency dividing circuit 2 is activated during each "L". There is no toggle operation of each FF1 output of the second frequency dividing circuit 2 for the time required for That is, in the present embodiment, since the FF1 has three stages, the ER becomes active when the clock pulse CK issues four times, but in the period of a to c, the CK has a maximum of three. Therefore, the ER cannot be activated. Therefore, at this time, since each FF1 of the second frequency dividing circuit 2 is immediately reset, the change of the input signal during the period from does not appear in Q0.

FIG. 4 shows a timing chart when the input signal IN changes from “H” to “L”. Compared with FIG. 3, the level of the input signal IN and the level of the output Q0 are compared. The basic operation is the same except that FIG.

In the embodiment, each of the first frequency dividing circuit 1 and the second frequency dividing circuit 2 has three flip-flops, but the number of stages may be arbitrary. If the number of stages is increased, the length of the signal that can be excluded can be increased, and if the clock frequency is also increased, the accuracy of setting the length of the excluded signal can be increased.

[0019]

[Effect of device]

 According to the present invention, since two frequency dividing circuits are provided and the active level and the non-active level of the input signal are monitored respectively, erroneous determination is made by sampling an erroneous signal such as noise. It is possible to monitor the level of the input signal with high reliability.

[Brief description of drawings]

FIG. 1 shows a block diagram of a signal level monitoring circuit according to the present invention.

FIG. 2 shows a circuit diagram of an embodiment of the present invention.

FIG. 3 shows a timing chart of the signal level monitoring circuit.

FIG. 4 shows a timing chart of the signal level monitoring circuit.

FIG. 5 shows a timing chart of a conventional signal level monitoring circuit.

[Explanation of symbols]

 1-first frequency divider circuit 2-second frequency divider circuit 3-flip-flop CK-input clock pulse IN-input signal

Claims (2)

[Scope of utility model registration request] 1. A first frequency divider circuit for resetting an input signal when the input signal is non-active and for dividing an input clock pulse when the input signal is active; and for resetting when the input signal is active, the input signal being non-active. A second frequency divider circuit for dividing the input clock pulse at the time of, and an active detection level of the input signal is set by the output of the first frequency divider circuit, and is output by the second frequency divider circuit. A signal level monitoring circuit comprising: a circuit that resets and outputs a non-active detection level of an input signal. 2. The signal level monitoring circuit according to claim 1, wherein the frequency dividing ratios of the first frequency dividing circuit and the second frequency dividing circuit are the same.