JPH07299203A - Microcomputer chip for game machine control - Google Patents

Abstract

PURPOSE:To prohibit the change in probability after inspection in a microprocessor for game machine. CONSTITUTION:This chip is constituted of a built-in ROE, a built-in RAM on which data for user program is written and data reload from the outside is prohibited, an identification means which detects the validity of a program written by scanning the built-in ROM, a central processing unit to execute a game program based on an application program written on the built-in ROM and under data, and a random number generation circuit which transmits a random number to the central processing unit based on a signal from the the application program. The random number generation circuit is constituted of a pre-settable counter 42, and a first register 43 and a second register 44 which store by latching the numeric value of a down counter when the signals from a load register to write the number of count and a winning sensor 2 are received, and transmits latched random number data to the central processing unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application program (equipment control program or equipment control program which is mounted on a pachinko gaming machine, a spinning-type gaming machine, an arrange ball, a jean ball gaming machine, etc. The present invention relates to a semiconductor chip configured to prevent fraud of (data).

A gaming machine such as a pachinko machine is a product that cannot be sold unless it has passed the certification and type verification of the gaming machine in accordance with the rules of the National Public Safety Commission based on the rules of the Business Act of Customs and Microprocessors. Must also pass the type test conducted by a third-party inspection organization, apply for the certification to a third-party supervisory organization for those that have passed this type, and market the game machines that have passed the certification. It is a mechanism that can be distributed to other companies, and can be used for sales at pachinko halls.

Therefore, after receiving the type approval, a third party performs a modification such as replacing the board of the game machine, replacing the chip, modifying the microprocessor, rewriting the ROM of the microprocessor, etc., and playing illegal games. There is a case where it is used as a machine, and preventing the modification after passing the type is an issue today.

[0004]

2. Description of the Related Art A conventional game machine of this type includes a device that continuously operates an electric accessory, a device that electrically controls the electric accessory, and a circuit that is integrated with a microprocessor. It is known to control the rotation of a rotating drum in a torso-type game machine, and those circuits that pass the type test of a third-party inspection organization will emit a winning ball to the player with a certain probability. Is configured to.
In the case of gaming machines, it is obliged to store application programs and data in a predetermined address area. In addition, many gaming machines are programmed to make a big hit or a small hit when a ball enters a predetermined winning opening, and it is required that the big hit or the small hit come out with a predetermined probability. Random numbers are created programmatically, and a random number generation circuit is installed to satisfy that condition. Pachinko machine is 2m
The central processing unit is reset at intervals of sec.
All processing is done within 2 m sec., Random numbers are updated within this process, and at the same time ball winnings are also examined within this 2 m sec. That is, the winning determination and the random number update are performed at fixed timings. For this reason, a method such as the mixed congruential method is used for the random number generation, but in any case, the random number generation pattern has regularity and there is no possibility of being illegal.

[0005]

However, in the case of such a conventional microprocessor, even if a third party modifies the control program and data in the circuit after passing the type test, it is only the product that has passed the type test and the appearance. It is difficult to distinguish and it is likely to be handled as a product that has passed the type test. Therefore, there is an inconvenience that such a fraudulent act on a game machine by a third party cannot be sufficiently prevented. If such fraud is left unchecked, the player will suffer disadvantages and the credibility of the public third-party inspection agency that conducts the type test will be damaged, and the significance of the type test will diminish. There is a risk. In addition, there are various methods for generating random numbers, so it takes time for the inspection organization to confirm whether or not a big hit can occur with a predetermined probability, and it is difficult to obtain test results. There is the inconvenience of being tampered with. Therefore, the present invention has been made in view of the above-mentioned drawbacks of the prior art. In addition to providing a configuration for preventing unauthorized modification of a microprocessor incorporated in a gaming machine, the random number generation circuit itself is also housed in a chip. Built-in ROM in the onboard microprocessor
The control circuit has a function for preventing falsification of programs, data, and random numbers.

According to the basic concept of the present invention, if a random number generating circuit is incorporated in a fraud prevention chip and a numerical value (probability) output from the random number generating circuit is operated based on a program written in an internal ROM, It is easy to see what kind of probability is selected by looking at the program, which makes it easy to check the type, and even if you try to change the probability after passing the type, it will be detected by the program check so that the random number can not be illegal. It is to be.

[0007]

That is, the invention according to claim 1 is a built-in ROM, a built-in RAM in which data for a user program is written, which prohibits data rewriting from the outside, and a program written in the built-in ROM. Scans the built-in ROM to see if it is certified or not.
Identification means for detecting whether the program written in M is illegal, a central processing unit for executing the game program based on the application program and user data written in the built-in ROM, and based on a signal from the application program A random number generation circuit for transmitting a random number to the central processing unit, wherein the random number generation circuit receives a signal from a presettable down counter, a load register for writing a count number to the counter, and a winning sensor. It is composed of a first register and a second register for latching and storing the value of the down counter,
A gaming machine control microcomputer chip configured to transmit the latched random number data to a central processing unit.

According to the second aspect of the present invention, is the built-in ROM, the built-in RAM in which the data for the user program is written prohibited from being rewritten from the outside, and the program written in the built-in ROM are certified? Identification means for scanning whether or not the program written in the built-in ROM is illegal by scanning the built-in ROM, and central processing for executing the game program based on the application program and user data written in the built-in ROM A random number generating circuit for transmitting a random number to the central processing unit based on a signal from an application program, wherein the random number generating circuit receives a free-running counter and a numerical value of the counter and is input from a load register. Send a reset signal to the counter when it reaches a number Constructed a number of the down counter at the time of receiving the signal from the comparator a winning sensor in a first register and a second register for storing latches,
A gaming machine control microcomputer chip configured to transmit the latched random number data to a central processing unit.

[0009]

In the microcomputer chip according to the present invention, it is checked whether or not the program written in the ROM incorporated in the chip has passed the inspection, and if it is correct, the device is operated.
Control program and RAM written in ROM built in chip
The central processing unit controls the game machine based on the data written in. In the device according to the present invention, the program is prohibited from operating outside the designated area, and each program control circuit prohibits the program from reading the data of the storage means outside the chip. Therefore, access to the external storage means is prohibited during execution of the program. Note that if the ROM in the chip is made of a rewrite-protected ROM, the program cannot be rewritten after receiving the permission. On the other hand, the probability information such as jackpots written in the program is input to the reload register of the random number generation circuit, and the input numerical value m (10
0,200) etc. determine the probability of a big hit. And the presettable counter or the free running counter is 0, 1, based on the frequency oscillated from the clock.
2, 3, ..., M-1, m, 0, 1, 2, 3, ..., M-
1, m ... are repeated and the count number of the counter at the time of receiving the prize signal transmitted from the prize sensor is read and latched in the first register or the second register, and the latched count number is read. Send to central controller. Therefore, the counter itself only counts based on the clock frequency, and the count number of the counter is changed by the numerical value input from the reload register, so that it is possible to determine the jackpot probability only by looking at the program. Further, since the numerical value that determines the winning probability is input from the program written in the built-in ROM, it is impossible to change the winning probability after the inspection is completed.

[0010]

The present invention will be described in detail below with reference to the illustrated embodiments. As shown in FIG. 1, the operating system considered by the gaming machine control microcomputer chip and the collation device for detecting an illegal program in the chip is a chip (development chip) with a built-in EPROM produced by an IC maker as shown in FIG. It is wholesaled from a machine microcomputer chip maker to a game machine development maker, and the development maker uses the EPROM built-in chip to create a program for game machine control within a range conforming to the law, and inspects the game machine for third party inspection. Submit to the institution to apply for type test. The inspection organization tests whether the program written in the EPROM with a built-in chip is appropriate and notifies the development maker of the test result (whether it passes or not). ROM that passed the test
The data is sent from the inspection organization to the microcomputer chip maker as compatible ROM data, and there is an identification code (including data such as the date of approval and the selection number of the encryption key code) corresponding to each model for each ROM. An identification code encrypted by a predetermined encryption algorithm (for example, field eight) and a check code calculated based on the program stored in the ROM, the identification code, and the encrypted identification code are added. The third-party inspection body creates a correspondence table of the passed models and the identification numbers given to them. Then, the compatible ROM data and the identification code are sent to, for example, a public ROM writing organization,
The writing agency is the IC maker (or chip maker)
Rewrite-protected ROM for mass production (eg fuse R
The OM) built-in chip (mass production chip) is provided, and the ROM data which has passed the type test and the identification code and the encrypted identification code are written in a predetermined format, and the rewriting prohibition process is performed on the ROM.

Next, a ROM built-in ROM-embedded chip in which the ROM data of the type test passed, the identification code, the encrypted identification code and the like are written is delivered from the ROM writing organization, and the development maker uses the gaming machine based on the delivered chip. Produced, applied for certification to a third-party supervisory organization, and the gaming machines that have passed the certification test are delivered to the pachinko hall and used for sales. The pachinko hall side will apply for certification to the supervisory agency in order to operate using products that have passed such certification, and the business is permitted.

The gaming machine control chip of the present invention has a structure as shown in the block diagram of FIG. In FIG. 2, 5 is
Central processing unit (C which executes and controls game machine programs
PU), which is connected to a clock generation circuit 6 that generates a clock required for operation in the CPU 5. The CPU 5 uses a parallel input / output port for inputting or outputting various external data via various buses, an application program for game, an identification code for collation, and encrypts it based on a predetermined encryption key code. The rewritable built-in RO in which the check code calculated by the predetermined algorithm (field rate, cyclic redundancy check) from the identification code and error code for verification, the application program, the identification code and the error code is written.
M7, a built-in RAM8 for temporarily storing game control data, and a ROM7 in the procedure described later when these match based on the recognition code input from the external device
The check code of the data is calculated and compared with the check code written in the built-in ROM 7 in advance.
An identification circuit 9 as an identification means for outputting the contents of the M7 data (identification code and encrypted identification code or error code) and the contents of the RAM8 data to an external device, and a counter / timer circuit 10 for setting time and controlling various timings.
And a watchdog timer (WDT) 12 for monitoring the abnormal operation of the CPU, and an illegal address execution prohibition control circuit (IAT) for prohibiting execution of a program other than the built-in ROM 7.
G) 14 is connected to the reset circuit 16, 18 is a memory control circuit of the built-in ROM 7, and 20 is R of the ROM 7.
It is a memory program control circuit for OM writing. The error code is transmitted when the identification number is incorrect when the check code comparison result is correct. Further, 1 is a random number generating circuit mounted in the chip, and the numerical value output from the random number generating circuit 1 is a numerical value within a predetermined numerical value m (natural number), and the numerical value is a central value via an internal data bus. It is input to the processing device 5. The numerical value output from the random number generation circuit 1 is the chattering removal circuit 3 based on the signal from the winning sensor 2 installed in the gaming machine.
The value at the time of input is output via (chip built-in).

Next, FIG. 3 shows a concrete block diagram of the discrimination circuit 9, which includes a data input / output circuit 22 for inputting / outputting data of the discrimination circuit 9 and a data input / output circuit.
In the case of verification by an external device via 22, the trigger timing is adjusted based on the trigger timing pulse input from the external device, and information on the communication speed (baud
A timing generation circuit 24 for outputting a rate), an address counter 26 connected to an address bus for generating an address when accessing the ROM and RAM of the chip and a sequential access operation of the addresses, and a data bus for the chip. Parallel / serial conversion circuit 28, divider / timer circuit 30 for generating a reference clock for each block, determining the baud rate during serial data transmission, and monitoring the timer during each operation, and an identification code input from an external device And a recognition code judging circuit 32 for judging the coincidence with a previously stored recognition code, and the same method as the predetermined algorithm described above based on the program, the identification code, the encrypted identification code and the error code written in the chip built-in ROM 7. ROM check circuit 34 that calculates the check code by
And the data input / output circuit 22, timing generation circuit 24,
Address counter 26, parallel / serial conversion circuit 28,
Divider / timer circuit 30, recognition code determination circuit 32 and R
The ID control circuit 36 controls the operation of the OM check circuit 34. After confirming the identification code sent from the collation device, the ID control circuit 36 issues a bus open request to put the central processing unit 5 into a floating state, and suspends the CPU 5. Further, in the data input / output circuit 22, as shown in FIG. 4, it is possible that a third party mischievously or for some reason causes an excessive current to flow to the SD terminal of the microcomputer chip to destroy the circuit. A self-diagnosis circuit 21 is incorporated so as not to operate the game machine in some cases. This self-diagnosis circuit 21 is CP
An oscillation circuit 21a that receives a fetch cycle from U5 and oscillates a predetermined check pulse twice, and an OR circuit 21b that outputs the check pulse oscillated from the oscillation circuit 21a and an output terminal 21.
c, output circuit 21d (having a buffer function), input circuit
21e (having a buffer function), which is connected to a comparison circuit 21g via an input terminal 21f.
A pulse is directly input to the g from the check pulse oscillating circuit 21a.
21 g is output to the reset circuit 16.

Next, the random number generation circuit 1 and the chattering removal circuit 3 are constructed as shown in FIG. That is, the n-bit user setting register 40, the reload register 41 connected to the register 40, and the reload register 4
The second register comprises an n-bit presettable down counter 42 connected to 1, an n-bit first register 43 for latching and storing the numerical value output from the counter 42, and an n-bit second register 44. The random number data transferred to 44 is transferred to the central processing unit 4 via the internal data bus. The n-bit presettable down counter 42 is, for example, a 12 MHz clock generation circuit 6
A clock signal is input from and a predetermined number is counted based on the clock signal. The value to be counted by the counter 42 is changed based on the input signal from the reload register 41, but is changed only when the count end signal is input as shown in the figure.

The chattering removing circuit 3 receives the input signal of 12 MHz from the winning sensor 2 and the clock signal of the clock generating circuit 6 as 1/2 ¹³ , 1/2 ¹⁴ , 1/2 ¹⁵ ,
Produces a sampling clock signal by 1/2 ^16-divided prescaler 45, the clock signal one period shorter than the chattering, based on the clock signal selected by the sampling clock selector 46 and the clock selector 46 for selecting the clock signal produced the It is configured to remove ingredients.

Further, the output signal of the chattering removing circuit 3 is the first register 43 and the first flip-flop circuit 47.
Is output to the latch data internal data bus composed of the second flip-flop circuit 48, the OR circuit 49, the one clock delays 50 and 51, and the decode circuit 52 of the second register. That is, if the empty flag of the random number data latched in the first register is empty, the empty flag is set. The user confirms the empty flag and reads the random number data transferred to the second register. After reading, the empty flag is cleared.

On the other hand, in the built-in ROM 7 of the chip, for example, as shown in FIG. 5, an area from address 0000H to address 3FDFH is used as a user program area (application program area), and an identification code from 32FE from address 3FE0H and an encrypted identification. The code and the selection number of the encryption key code are written. And 4000H
7E00 from address to 7DFF as unused area
512 bytes RAM from H address to 7FFFH RAM
It has a dedicated address and further has an unused area from 8000H to FFFFH. For example, the address control of the memory normally controls so that the data contents cannot be read from the 3FC0H address to the 3FFFH address.
In this embodiment, the capacity of the RAM is configured to be switched by 256/512 bytes by the switching device.

Next, FIG. 7 shows a second embodiment of the random number generating circuit 1 according to the present invention, and the chattering removing circuit 3 is constructed in the same manner as the first embodiment.
Instead of the presettable down counter 42 of the first embodiment, an n-bit free running counter 42b is used, and the counter 42b is directly fed from the reload register 41.
Install an n-bit comparator 60 without inputting to
Numerical data m of reload register 41 and counter 42b
The output data of the counter 4 is input to the comparator 60 and the counter 4
When the output data of 2b matches the data of the reload register 41, a reset signal is sent to the counter 42b to clear the value of the counter 42b to 0. This n-bit counter 42b also has, for example, 1
A clock signal is input from the 2 MHz clock generation circuit 6, and a predetermined number (m) is counted based on the signal. The numerical value to be counted by the counter 42 is changed based on the input data from the reload register 41, but is changed only when the counted numerical value matches the numerical value (m) previously input from the reload register 41 as shown in the figure. It is configured to be able to.

The microcomputer chip according to the embodiment of the present invention having the above-described structure operates as follows. In the microcomputer chip, when the power is turned on, the check pulse oscillation circuit 21a in the self-diagnosis circuit 21 in the data input / output circuit 22 of the identification circuit No. 9 receives the fetch cycle, and the output terminal 21c and the comparison circuit. 21 g
To the output circuit 21
d, the input circuit 21e, and the pulse input via the input terminal 21f are compared. If the pulses match, comparison circuit 21
g does not output to the reset circuit 16 and does not match
Comparison circuit 21 (when there is no pulse coming from the input terminal)
Since the circuit is abnormal from g, a reset signal is output to the reset circuit 16 to reset the gaming machine control CPU 5,
Prevent the gaming machine from operating. When there is no abnormality or when a collation signal from an external device is input, the ID control circuit 36 of the identification circuit 9 puts the CPU 5 of the chip in a floating state (reset), and then writes the internal ROM 7 to the ROM check circuit 34. Instruct to check the written data.

The ROM check circuit 34 accesses the ROM 7 built in the microcomputer chip and calculates a check code according to a predetermined algorithm while sequentially scanning the program, the identification code and the encrypted identification code. In this embodiment, the check code is calculated by a field eight developed by Nippon Telegraph and Telephone Corporation or a cyclic redundancy check. The calculated check code is R
The calculated check code previously described in the predetermined address of the OM7 is collated, and when the two do not match, the gaming machine is stopped, and when they match, the gaming machine is operated. At this time, in the CPU 5, the IATG 14 constantly monitors the address where the program is running, and interrupts when the IATG 14 is out of the specified address range to operate the reset circuit. In addition, the WDT 12 detects a malfunction (runaway) due to noise or the like and restores the normal state. Note that the control of the game machine by the program is performed via the parallel I / O port.

Next, when the game machine is operating based on the program written in the built-in ROM and a ball enters the winning opening 2 of the game machine, a detection signal is first sent through the chattering removing circuit 3 as shown in FIG. Input to the first register,
The numerical value (random number) of the counter at that time is stored. The stored random number data is transferred to the second register,
It is transmitted to the central processing unit 5, and it is decided whether or not the numerical value of the random number is a big hit. When the numerical values match, the winning character acts as a big hit, and when they do not match, it is not a big hit. Do not operate things.

For example, the probability described in the program is 1
At the time of 1/000, input 999 to the counter, make the counter repeat counting from 0 to 999, and at the time of receiving the detection signal output when the ball enters the winning opening 2. The count value p-1 (p-1 ≤ 999) of the counter input to the first register is latched and the central processing unit 5 makes a determination, and when p-1 = 999, it is a big hit (probability is 1/1000). . Here, when the counter is 8 bits (n = 8), the maximum probability is 1/256 because it can count only up to 255. However, if a 16-bit counter is used, it can count up to 65535 and the probability is 1/65536. Can take up to. Further, if it is configured such that the judgment of the numerical value output from the plurality of random number generation circuits is performed in two ways and a big hit is made when all the judgments match, for example, an 8-bit counter 2
If one is used, the probability can be reduced to 1/65536. In addition, although the case where one random number generating circuit is used has been described in the present embodiment, the present invention is not limited to this, and a plurality of random number generating circuits may be used according to the number of big hits, small hits and the like.

A built-in ROM is used to determine this probability.
Since it is determined by the program input to the counter from the program area of, the change of the probability after the end of the verification is checked as the program modification, and thus it is virtually impossible.

[0024]

As described above, in the microcomputer chip according to the present invention, the random number generation circuit is built in the chip, and the range in which the random number is output is based on the data written in the program area of the internal ROM. In addition, since the program in the built-in ROM is configured to be checked by the identification circuit at the time of starting the game machine, the probability of a big hit by a third-party inspection organization can be easily determined, and the big hit, small hit, etc. The probability of occurring cannot be modified after the assay. As a result, the player can enjoy the game with peace of mind.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an operation system of an apparatus according to the present invention.

FIG. 2 is a block diagram of a microcomputer chip according to the present invention.

FIG. 3 is a block diagram of an identification circuit circuit in a chip.

FIG. 4 is a block diagram of a self-diagnosis circuit incorporated in a data input circuit.

FIG. 5 is a diagram showing addresses of programs and the like stored in a built-in ROM and RAM.

FIG. 6 is a block diagram showing a first embodiment of a random number generation circuit built in the chip.

FIG. 7 is a block diagram showing a second embodiment of the random number generation circuit built in the chip.

[Explanation of symbols]

1 random number generation circuit 2 winning sensor 3 chattering removal circuit 5 central processing unit (CPU) 6 clock generation circuit 7 rewrite prohibition built-in ROM 8 built-in RAM 9 identification circuit 10 counter / timer circuit 11 parallel input / output port 12 watchdog timer (WDT) ) 14 Illegal address execution prohibition control circuit (IAT
G) 16 reset circuit 18 memory control circuit 20 memory program control circuit 21 self-diagnosis circuit 21a check pulse generation circuit 21b OR circuit 21c output terminal 21d output circuit 21e input circuit 21f input terminal 21g comparison circuit 21h switching circuit 22 data input / output circuit 24 Timing generation circuit 26 Address counter 28 Parallel / serial conversion circuit 30 Divider / timer circuit 32 Recognition code judgment circuit 34 ROM check circuit 36 ID control circuit 40 User setting register 41 Reload register 42 Presettable counter 42b Free running counter 43 First register 44 Second register 45 Prescaler 46 Clock selector 47 First flip-flop 48 Second flip-flop 49 OR circuit 50,51 1 clock delay 52 Decode circuit 60 Comparator

Claims (2)

[Claims] 1. A built-in ROM, a built-in RAM in which data for a user program is written, which prohibits rewriting of data from the outside, and a built-in ROM as to whether the program written in the built-in ROM is certified or not. Means for scanning whether or not the program written in the built-in ROM is illegal, a central processing unit for executing the game program based on the application program and user data written in the built-in ROM, and the application program And a signal from a winning sensor, which comprises a random number generation circuit for transmitting a random number to the central processing unit based on a signal from Latches and stores the value of the down counter at the time of receiving A gaming machine control microcomputer chip, comprising a first register and a second register, and configured to transmit latched random number data to a central processing unit. 2. A built-in ROM, a built-in RAM in which data for a user program is written, which prohibits rewriting of data from the outside, and a built-in ROM as to whether or not the program written in the built-in ROM is certified. Means for scanning whether or not the program written in the built-in ROM is illegal, a central processing unit for executing the game program based on the application program and user data written in the built-in ROM, and the application program A random number generating circuit for transmitting a random number to the central processing unit based on the signal from the random number generating circuit, and the random number generating circuit receives a free running counter and a numerical value of the counter and reaches the numerical value input from the load register. A comparator and a winning prize sending a reset signal to the counter. A first register and a second register for latching and storing the value of the down counter at the time of receiving the signal from the sensor, and transmitting the latched random number data to the central processing unit. A microcomputer chip for controlling a gaming machine characterized by: