JP2001353336A - Microcomputer tip for game machine control which is used for development - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer tip for a development, of which the constitution is the same as a built-in ROM being packaged, and which can be repeatedly rewritten, for a tip wherein a program after passing a model examination can be prevented from being modified. SOLUTION: This microcomputer tip for controlling a game machine for the development is equipped with the rewritable built-in ROM, a built-in RAM, an identification means, and a central processing device. In this case, the built-in ROM stores identification codes for respective models of the game machine, and check codes which are calculated based on coded identification codes. The built-in RAM prohibits rewriting of data from the outside. The identification means compares the calculation of a check code and a check code stored in the rewritable built-in ROM by scanning the rewritable built-in ROM regarding whether a program in the rewritable built-in ROM, which is written, is authorized one or not when a right/wrong check agrees with a recognition code, based on the recognition code transmitted from the outside. The central processing device performs a game program based on an application program written in the rewritable built-in ROM and user data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application program (equipment control program, Data) related to the semiconductor chip to start, especially when the game machine development maker develops an application program, if the program does not conform to the law, the semiconductor chip is configured to be re-writable and rewritten after certification The purpose of the present invention is to develop a chip that can be prevented from being modified into a program that operates outside legal standards while being written in an impossible internal ROM.

A game machine such as a pachinko machine is a product that cannot be sold unless it has passed the certification and type approval of the game machine in accordance with the rules of the National Public Safety Commission based on the rules of the Customs Business Act. Must also pass the type test conducted by a third-party inspection organization, apply for certification to a third-party regulatory agency for those that have passed this type, and sell the gaming machines that have passed the certification to the market. It can be distributed to pachinko parlors and used for business.

[0003] For this reason, after receiving a model pass, a third party modifies the board of the gaming machine, replaces the chip, modifies the microprocessor, rewrites the ROM of the microprocessor, etc. It is conceivable to use it as a machine, and it is an issue today to prevent remodeling after passing the model.

[0004]

2. Description of the Related Art A conventional game machine of this type has a circuit integrated with a microprocessor, and a device for continuously operating an electric accessory, a device for electrically controlling an electric accessory, etc. It is known to control the rotation of a rotating torso in a barrel-type game machine, and those circuits that pass the type test of a third-party inspection organization release a winning ball to the user with a predetermined probability. It is configured to be.
In the case of a gaming machine, application programs and data are required to be stored in a predetermined address area.

[0005]

However, in the case of such a conventional microprocessor, even if a third party modifies a control program or data in a circuit after passing the type test, it is not possible to obtain a product that has passed the type test and only looks. It is hard to distinguish and it is likely to be treated as a product that has passed the type test. For this reason, there is an inconvenience that it is not possible to sufficiently prevent such a third party from misbehaving the gaming machine. Leaving such fraudulent unfairness would result in disadvantages for the player and damage the credibility of the public third-party inspection organization that inspects the type-accepted products, which in turn reduces the significance of conducting type tests. May come. Therefore, the present invention has been made in view of the drawbacks of the related art, and provides a configuration for preventing unauthorized modification of a microprocessor built in a gaming machine, and also provides a built-in ROM and a control in a microprocessor in the gaming machine. It is an object of the present invention to provide a circuit with a function for preventing alteration of a program or data. Further, the present invention enables a built-in ROM for writing a program, which has the same configuration as a chip for mass production, to be reused many times in the development stage.

[0006] In the conventional program check, a third-party inspection organization carefully examines the contents from various angles at the time of applying for a type test, but after passing the test, leaves the control by the inspection organization and Gaming machines equipped with a program that has passed the test have been applied for certification by a gaming machine manufacturer to a third-party supervisory authority, and products that have passed this certification are shipped to the amusement arcade. Therefore, since the gaming machine control program check is not regularly performed, it was not possible to know who and when the chip was replaced, the program was modified, or the like at any time.

[0007]

That is, according to a game machine development manufacturer, even if a chip in which a legitimate program is written is incorporated and shipped, a third party intervenes to rewrite the program or to read the ROM. There are also problems such as being unable to take responsibility for being altered. This is a single, R
This is because the modification of the OM is easily performed, and firstly, it was considered important to prevent the modification of the ROM of the passing program in preventing the illegality.

Secondly, when a program is written into a chip after passing, the work is performed by a single fair organization collectively, rather than being performed separately by each developer, and the subsequent writing to the chip is prohibited. In this case, the cost is reduced and the reliability of the chip is increased. It should be noted that the writing may be performed by the development maker side instead of being written by a fair organization. Thirdly, if a game machine with a built-in ROM can be verified by a police or other third party supervisory organization that can easily check whether or not the content of the program has passed the test, it will be fraudulent. Anxiety arises when a person is checked, and he / she does not run the risk of cheating easily. However, the verification device found that the mechanism of the device that verifies whether or not the program installed in the ROM mounted on the chip passed the model application was a simple one, or that the security of the internal software was poor. There is a possibility that the program or the circuit may be modified so that it cannot be performed. Therefore, an identification code for each device is further added to the program on the ROM written in the microcomputer chip, and an identification code encrypted by a specific encryption algorithm is added. Write the check code calculated by a predetermined algorithm while scanning the encrypted identification code sequentially, and check whether the check code written in the ROM in the chip matches when checking the program contents with a collation device or the like. Can be checked by a matching circuit provided in the chip.

That is, in the first aspect of the present invention, an application program, an identification code and an encrypted identification code for each type of gaming machine, and a check code calculated based on the application program, the identification code, and the encrypted identification code are stored in a predetermined area. Rewritable built-in RO
M, built-in RAM in which data for the user program is written to prevent external data from being rewritten, and whether or not the code is correct based on an externally transmitted recognition code. Scans the rewritable internal ROM to determine whether the program written in the rewritable internal ROM is authorized or not, calculates a check code, and rewrites the rewritable internal RO.
A gaming machine system for development having identification means for comparing with a check code stored in M, and a central processing unit for executing a gaming program based on an application program and user data written in a rewritable internal ROM. This is your microcomputer chip.

[0010] The invention according to claim 2 further comprises an illegal address execution prohibition control circuit for preventing an application program for development in the chip from accidentally accessing an address other than ROM when mounted on a gaming machine. It is characterized by the following.

[0011]

In the microcomputer chip according to the present invention, the built-in ROM that is actually mass-produced is constituted by a non-rewritable ROM. However, it is impossible that unauthorized tampering is performed at the program development stage. In this case, the built-in ROM is configured as a rewritable one, so that the developer can develop a program in the same environment as the actual ROM for mass production, and the program of the built-in ROM created by the chip for the development is used. Even if the data is written in the mass production ROM, the same function as the mounting result in the verification test can be exerted because it does not change environmentally.

In the chip according to the present invention,
The program is prohibited from operating outside the specified area, and each control circuit prohibits the program from reading data in the storage means outside the chip. Access to the storage means is prohibited. As a result, the development maker can discover an abnormal access of the application program at the development stage.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. The operation method considered by the gaming machine control microcomputer chip according to the present invention and the collation device for detecting a malicious program in the chip is a rewritable EPR produced by an IC maker as shown in FIG.
Chips with built-in OM (development chips) are wholesaled by gaming machine microcomputer manufacturers to gaming machine development manufacturers, and the development manufacturers
Using the built-in chip, create a program for gaming machine control within the range that conforms to the law, submit it to the third-party inspection organization of the gaming machine, and submit a type test application.

The inspection organization uses a rewritable chip EP.
It tests whether the program written in the ROM is appropriate or not, and notifies the development maker of the test result (whether it passed or not). The ROM data that passed the test are sent from the inspection organization to the microcomputer chip manufacturer as conforming ROM data, where identification codes (data such as permission date and encryption key code selection) corresponding to each model are sent to each ROM. Number, an identification code encrypted by a predetermined encryption algorithm (for example, field eight), a program written in a ROM, an identification code, and a check code calculated based on the encryption identification code. You. The third-party inspection organization creates a correspondence table between the passed models and the identification numbers assigned to the models. The conforming ROM data and the identification code are sent to, for example, a public ROM writing organization (which may be a writing organization of a development maker). The ROM writing organization is a mass-production rewrite-protected ROM (for example, a fuse ROM) from an IC maker (or chip maker). (2) Upon receiving the provision of the built-in chip (mass production chip), the ROM data, the identification code, and the encrypted identification code that have passed the type test are written in a predetermined format, and the ROM is subjected to the process of prohibiting rewriting.

Next, a chip (mass-production chip) with a built-in ROM that is not rewritten and on which ROM data, an identification code, an encryption identification code, and the like are written is delivered from a ROM writing organization, and based on the delivered chip. The development maker produces a gaming machine, applies it to a third-party regulatory agency for certification, and the gaming machine that passes the certification test is delivered to a pachinko hall and used for sales. The pachinko hall side will apply for accreditation to the supervisory authority to conduct business using the products that have passed the certification, and the business will be licensed. On the other hand, a third party supervisory body that is in a position to inspect the business situation includes RO in the chip.
A collation device capable of collating the contents of M is provided,
An official of a third party supervisor can go to the pachinko hall and easily inspect (collate) the contents of the chip-incorporated ROM with respect to the chips incorporated in the gaming machine by using the collation device.

The data of the chip to be verified and the outline of the verification system are as shown in FIG. 2. The rewrite-protected ROM built in the microcomputer chip contains a game program, an identification code given by the microcomputer chip manufacturer, a predetermined code, and the like. Based on the encryption key code, for example, a field code, an encrypted identification code encrypted according to an encryption procedure such as a cyclic redundancy check, and a check code calculated by a predetermined algorithm based on the game program, the identification code, and the encrypted identification code. In addition, an error code (for example, data having a format different from that of the identification number or the encryption identification number) for displaying an error in the verification device when the check code does not match is written,
The verification device demodulates the identification code read from the ROM in the chip and the encrypted identification code in the encrypted identification code data, and compares the demodulated identification code with the identification code described above.
It is configured to match the contents of the data. When the identification codes match as a result of the collation, OK is displayed, and when they do not match, NG is displayed. Further, the identification number read from the built-in ROM is displayed on the LCD of the collation device, so that the officer can visually check the identification number of the model. Further, the collating apparatus prints out the contents of the RAM built in the microcomputer chip as RAM data.

More specifically, the control program for the gaming machine has a gaming machine control board 2 mounted on the back of the gaming machine 1, and the connection terminal 4 of the matching device 3 is directly connected to the chip terminal of the gaming machine board 2. (See FIG. 3). In this embodiment, the microcomputer chip for development installed on the game machine board 2 has a configuration as shown in the block diagram of FIG.

In FIG. 4, reference numeral 5 denotes a central processing unit (CPU) for executing and controlling a game machine program.
5 is connected to a clock generator 6 for generating a clock required for operation. The CPU 5 has a parallel input / output port for inputting or outputting various external data via various buses, a game application program, an identification code for verification, and encrypts the identification code based on a predetermined encryption key code. A rewritable built-in ROM 7 'in which a check code calculated by a predetermined algorithm (feel-eight, cyclic redundancy check) from the identification code, error code, application program, identification code and error code for the verification is written; And a built-in RAM 8 for temporarily storing data, and a check code of ROM 7 'data calculated and written in the built-in ROM 7' in advance by a procedure to be described later when the codes match based on a recognition code input from an external device. And compare it with the check code An identification circuit 9 as identification means for outputting the contents of data (identification code and encrypted identification code or error code) and the contents of RAM 8 data to an external device; a counter / timer circuit 10 for setting time and controlling various timings; , CPU
Watchdog timer (WDT) 12 for monitoring abnormal operation of
And an illegal address execution prohibition control circuit (IATG) 14 for prohibiting execution of a program from a source other than the internal ROM 7, and a reset circuit 16; 18 is a memory control circuit of the internal ROM 7 '; Is a memory program control circuit for writing to the ROM. An error code is transmitted when the identification number is incorrect when the result of the check code comparison is correct. A microcomputer chip for mass production is shown in FIG.
As shown in FIG. 2, the rewritable built-in ROM 7 ′ is replaced by a write-protected built-in ROM 7 in the configuration of the microcomputer chip for development. Therefore, there is no structural difference between the development chip and the mass production chip.

FIG. 5 shows a specific block diagram of the identification circuit 9, which includes a data input / output circuit 22 for inputting / outputting data of the identification circuit 9, and a data input / output circuit 22.
A timing generation circuit 24 that adjusts the trigger timing based on a trigger timing pulse input from an external device (verification device) via 22 and outputs information (baud rate) related to a communication speed;
An address counter 26 connected to an address bus for generating addresses at the time of access and sequentially accessing the addresses, a parallel / serial conversion circuit 28 connected to a data bus of the chip, generation of a reference clock for each block, Divider / timer circuit 30 that determines the baud rate during serial data transmission and monitors the timer during each operation
A recognition code determining circuit 32 for determining whether a recognition code input from an external device matches a previously stored recognition code.
And a program written in the ROM 7 ′ with a built-in chip,
A ROM check circuit 34 for calculating a check code based on the identification code, the encrypted identification code, and the error code in the same manner as the above-described predetermined algorithm, the data input / output circuit 22, the timing generation circuit 24, the address counter 26, A serial control circuit 28, a divider / timer circuit 30, a recognition code determination circuit 32, and an ID control circuit 36 for controlling the operation of the ROM check circuit 34. After confirming the recognition code sent from the collating device, the ID control circuit 36 issues a bus release request to bring the central processing unit 5 into a floating state.
Pause. In addition, as shown in FIG. 6, the data input / output circuit 22 may be destroyed by a third party mischievously or by applying an excessive current to the SD terminal of the microcomputer chip. In such a case, a self-diagnosis circuit 21 is incorporated so as not to operate the gaming machine. The self-diagnosis circuit 21 generates a predetermined check pulse twice upon receiving a fetch cycle from the CPU 5, and outputs a check pulse transmitted from the generation circuit 21a to an OR circuit 21b, an output terminal 21c, and an output circuit 21d.
(Having a buffer function), an input circuit 21e (having a buffer function), and a circuit connected to a comparison circuit 21g via an input terminal 21f. The comparison circuit 21g receives a pulse directly from the check pulse generation circuit 21a. The comparison circuit 21g is configured to be output to the reset circuit 16. Reference numeral 21h denotes a switching circuit for switching a signal input from the ID terminal of the chip to a trigger timing pulse receiving terminal or a recognition code receiving terminal. XBP is a baud rate / pulse output terminal, and CHKD is an ID collation data output terminal.

For example, FIG.
As shown in the figure, the area from the address 0000H to the address 3FDFH is a user program area (application program area), and the identification code, the encryption identification code, and the selection number of the encryption key code are written in 32 bytes from the address 3FE0H. . The area from address 4000H to address 7DFF is set as an unused area in 7E00H.
The 512 bytes from the address to the address 7FFFH are dedicated to the RAM, and the unused area from the address 8000H to the FFFFH is used as an unused area. For example, normally, the data content cannot be read from the address 3FC0H to the address 3FFFH by memory address control. Is controlled.
In this embodiment, the capacity of the RAM is configured to be switched to 256/512 bytes by the switching device.

FIG. 9 is a block diagram of a microcomputer chip collating apparatus according to an embodiment of the present invention. A built-in RAM 42 connected to the main CPU 40 by a system bus, a built-in ROM 44 in which a control program for each device of the verification device is written,
And a security CPU 46 serially connected to the CPU 40, and a RAM 48 and a ROM 50 connected to the CPU 46. The ROM 50 is a serial input / output device SIO in a bootstrap mode for loading a program into the RAM 48.
, The program is written into the ROM 50, and after the contents are confirmed, the program cannot be read. This ROM 50 contains
A predetermined algorithm for demodulating the encrypted identification code
(Program), a plurality of encryption key codes are written. The CPU 40 is connected to the printer 54 and the serial interface RS-232C via the printer interface 52.
Connected to 56. Reference numeral 58 denotes a TTL level interface, and 60 denotes an identification code determination result of “OK”,
L for indicating "NO" or "ERR"
Reference numeral 62 denotes an ED display, various collation switches such as "start" and "print" of the collation device, and 63 a battery for supplying power to each circuit. Reference numeral 65 denotes an LCD display for displaying an identification number read from the microcomputer chip and a guide for collation.

In this embodiment, a trigger timing pulse is sent to the ROM 44 to the gaming machine control CPU 5,
A function for controlling the reception protocol based on the baud rate output from the control CPU 5, a function for performing input processing of operation keys, a function for controlling each display, and a verification of the identification code on the LCD display. A function of displaying the result, a function of causing the printer to print the contents of the RAM transmitted from the main CPU 40, and a function of
, A control program having a function of transmitting an encrypted identification code and receiving a demodulated identification code.

The RAM 42 has a work area for executing a program, an area as a transmission and reception data buffer for the gaming machine control CPU 5, and an area as a transmission and reception buffer for the security CPU 46.

In the configuration described above, the microcomputer chip and the collating device according to the embodiment of the present invention operate as follows. In the microcomputer chip, when the power is turned on when not connected to the verification device, the self-diagnosis circuit in the data input / output circuit 22 of the identification circuit 9 is used.
The check pulse generation circuit 21a in 21 receives the fetch cycle and outputs 2 to the output terminal 21c and the comparison circuit 21g.
Each time a check pulse is transmitted, the pulse is compared with a pulse input through the output circuit 21d, the input circuit 21e, and the input terminal 21f. If the pulses match, the output is not output from the comparison circuit 21g to the reset circuit 16; if not (there is no pulse coming from the input terminal), the comparison circuit 21g resets the reset circuit 16 because the circuit is abnormal. A signal is output to reset the gaming machine control CPU 5 so that the gaming machine does not operate. When there is no abnormality, C for game machine control
Since the PU 5 is not reset, the application program written in the internal ROM 7 'and the internal RAM 8
Is controlled by controlling the operation of the gaming machine in accordance with the data written in. In the CPU 5, IA
The TG 14 constantly monitors the address where the program is running, and interrupts and activates the reset circuit when the address is out of the specified address range. Further, the WDT 12 detects a malfunction (runaway) due to noise or the like and returns to a normal state. The control of the game machine by the program is parallel I
Control is performed via the / O port. Therefore, in the chip of this embodiment, the control is shifted to the control of the gaming machine without checking the contents of the program at the beginning of the start.

Next, as shown in FIG. 3, when the connection terminal 4 of the collating device 3 according to the present embodiment is connected to the terminal of the microcomputer chip, the microcomputer chip and the collating device 3 perform processing as shown in the flowchart of FIG. Activate That is, the switch of the verification device 3 is turned on, the connection terminal 4 is connected to the SD terminal of the chip, and the verification switch 62 is pressed. Then, a trigger timing pulse is transmitted under the control of the ROM 44 in the collation device 3. The microcomputer chip receives this, measures the timing in the data input / output circuit 22 of the identification circuit, and when it is confirmed, the baud rate pulse is sent from the timing generation circuit 24 to the verification device 3 through the data input / output circuit 22. Sent out.

When the data input / output circuit 22 cannot confirm the timing, the timing generator 24
Since the rate pulse is not transmitted, the collation apparatus 3 determines that an error has occurred since the baud rate pulse has not been received within a predetermined time, and displays an error. In this embodiment, the collation device 3 is configured to send a trigger timing pulse to the microcomputer chip again and receive a baud rate pulse from the microcomputer chip.

Upon receiving the baud rate pulse, the verification device 3 determines the baud rate and sends a predetermined recognition code of the verification device 3 to the microcomputer chip. On the microcomputer chip side, the transmitted recognition code is compared with a previously input recognition code in the recognition code determination circuit 32 of the identification circuit, and it is determined whether the recognition code is correct. If the recognition code cannot be confirmed within a predetermined time, the chip side waits for a trigger timing pulse, and the collating apparatus 3 determines that no data has been transmitted from the microcomputer chip within the predetermined time and displays an error on the display (""). ERR "). When the identification codes match, the ID control circuit 36 of the identification circuit 9 sets the CPU 5 of the chip in a floating state (reset state), and then the ROM check circuit.
Instruct 34 to check the data written in the built-in ROM 7 '.

The ROM check circuit 34 accesses the ROM 7 'built in the microcomputer chip and calculates a check code according to a predetermined algorithm while sequentially scanning the program, the identification code and the encrypted identification code. In the present embodiment, the calculation of the check code is performed by a field redundancy developed by Nippon Telegraph and Telephone Corporation or a cyclic redundancy check. The calculated check code is
A check is performed with a calculated check code previously written at a predetermined address in the ROM 7 '.
The M data (512 bytes) and the error code (32 bytes) stored at a predetermined address of the ROM 7 'are sent to the collation device 3, and if they match, the RAM data, the ROM 7'
The identification code and the encrypted identification code stored at the predetermined address are transmitted to the collation device 3 as serial data. The format of the data to be transmitted is specified in advance, and in this embodiment, as shown in FIG.
2 bytes), ROM identification code and encryption identification code (32 bytes), checksum, etc.
Thereafter, the microcomputer chip returns to the initial state.

Collation device 3 that has received ROM data and the like
Is to temporarily store the data in the RAM 42, check the data format and the number of data bytes, and if an error code is sent out, for example, because the identification code and the data format are set differently, the ROM 44 The control program stored in is judged as a code check error and an error is displayed on the display ("ER
R "). When the result of checking the data format and the number of data bytes is OK, the printer 54 prints 512 bytes of RAM data and transfers 32 bytes of ROM data (identification code) to the security CPU 46.
The CPU demodulates the encrypted identification code according to the demodulation program written in the ROM. A predetermined encryption key code is used for encrypting the identification code. Therefore, in the present embodiment, a plurality of encryption key codes are stored in advance in the built-in ROM 50 for confidentiality, and these are selected based on a selection number or the like written in the data of the transmitted identification code, and are stored in a predetermined manner. Is demodulated by a predetermined algorithm based on the encryption key code.

The security CPU 46 compares the demodulated identification code with the identification code sent from the ROM 7 ', and determines whether or not they match. When the identification codes match as a result of the determination, the identification code is transmitted to the central processing unit 40 and the control program written in the ROM 44 instructs the display 60 to display "OK". At this time, the identification number is displayed on the LCD,
An official of a third party supervisory authority can determine whether or not the correct ROM for the model is set on the chip by comparing a target table of the model and the identification number. If the codes do not match as a result of the collation, the result is sent to the central processing unit 40 and the control program is displayed on the display 60.
To display "NO". When the switch is turned off after the inspection, the inspection is completed.

In the present embodiment, if the demodulation algorithm of the identification code is generally known, it becomes easy to falsify the microcomputer chip built-in ROM 7 '. Therefore, a third party reads the ROM 50 connected to the security CPU 46. It is configured to sometimes automatically delete data related to the algorithm.

In this embodiment, a system in which each game machine is inspected one by one by a verification device has been described.
As shown in FIG. 1, the contents of the ROM with a built-in microcomputer chip incorporated in each gaming machine by the hall computer with this matching device 3 interposed between the cables connecting the hall computer and each gaming machine. It is also possible to make a system that checks With such a configuration, it is possible to check the gaming machines in the entire hall in a short time.

In this embodiment, the built-in ROM is a rewrite-protected ROM. However, the present invention is not limited to this, and a normal ROM may be used. However, in this case, when the gaming machine is operated, the identification circuit 9 is operated, the ID control circuit 36 brings the CPU 5 of the chip into a floating state (reset state), and then the ROM check circuit.
The ROM check circuit 34 instructs the ROM 34 'to check the data written in the built-in ROM 7', accesses the ROM 7 'built in the microcomputer chip, and scans the program, the identification code, and the encrypted identification code sequentially while performing predetermined scanning. The check code is calculated according to the algorithm of In this case as well, the check code is calculated by a field eight developed by Nippon Telegraph and Telephone Corporation or by a cyclic redundancy check.
It is preferable that the identification number is checked every time the check code is compared with the calculated check code described in advance at the predetermined address 7 '.

[0034]

As described above, in the microcomputer chip according to the present invention, after passing the type test by the third party inspection organization, it is used as a mass production chip in the built-in ROM, in addition to the application program, the identification code and the encryption code. An identification code is written, and further, a check code calculated according to a predetermined algorithm based on the application program, the identification code, and the encrypted identification code is written, and the identification code and the check code are changed when the program is modified. Therefore, even if the entire board is replaced, the chip is replaced, the internal ROM is replaced, or the contents of the program are changed, the inspection can be easily performed. Furthermore, since the contents of the ROM incorporated in the microcomputer chip incorporated in the gaming machine delivered to the hall and whether the chip itself has passed the type test can be easily checked by the collation device, In addition, the on-site inspection can be easily detected as fraudulent as compared with the conventional apparatus.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an operation system of the device according to the present invention.

FIG. 2 is a schematic diagram showing a program detection process by a microcomputer chip and a collation device.

FIG. 3 is a schematic diagram showing a state where a matching device is connected to a gaming machine.

FIG. 4 is a block diagram of a microcomputer chip for development according to the present invention.

FIG. 5 is a detailed block diagram showing an identification number matching circuit in the microcomputer chip.

FIG. 6 is a block diagram of a self-diagnosis circuit incorporated in the data input / output circuit.

FIG. 7 is a diagram showing addresses of programs and the like stored in a built-in ROM and a RAM.

FIG. 8 is a diagram showing a format of data transmitted from the microcomputer chip to the collation device.

FIG. 9 is a block diagram showing a collation device according to the present invention.

FIG. 10 is a flowchart of a procedure for detecting illegality of a microcomputer chip built-in program using the collation device according to the present invention.

FIG. 11 is a block diagram showing an example in which a microcomputer chip and a matching device according to the present invention are applied.

FIG. 12 is a block diagram of a microcomputer chip for development according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gaming machine 2 Substrate 3 Verification device 4 Connection terminal 5 Central processing unit (CPU) 6 Clock generation circuit 7 Rewrite-protected built-in ROM 7 'Writable built-in ROM 8 Built-in RAM 9 Identification circuit 10 Counter / timer circuit 11 Parallel input / output Port 12 Watchdog timer (WDT) 14 Illegal address execution prohibition control circuit (IATG) 16 Reset circuit 18 Memory control circuit 20 Memory program control circuit 21 Self-diagnosis circuit 21a Check pulse generation circuit 21b OR circuit 21c Output terminal 21d Output circuit 21e Input Circuit 21f Input terminal 21g Comparison circuit 21h Switching circuit 22 Data input / output circuit 24 Timing generation circuit 26 Address counter 28 Parallel / serial conversion circuit 30 Divider / timer circuit 32 Recognition code judgment circuit 34 ROM check circuit 36 ID control circuit 40 Main CPU 42Built RAM 44 built ROM 46 Security CPU 48 RAM 50 ROM 52 printer interface 54 printer 56 serial interface 58 TTL-level interface 60 LED indicator 62 various verification switch 63 battery 65 LCD display

Claims (2)

[Claims] 1. A rewritable storage device in which a predetermined area stores an application program, an identification code and an encrypted identification code for each type of gaming machine, and a check code calculated based on the application program, the identification code, and the encrypted identification code. When the built-in ROM, the built-in RAM in which the data for the user program is written and external data rewriting is prohibited, and whether the recognition code is correct based on the recognition code transmitted from the outside and the recognition code match. Scan the rewritable internal ROM to determine whether the program written in the rewritable internal ROM has been certified, and compare the check code with the check code stored in the rewritable internal ROM. Identification means to perform and written in rewritable internal ROM A microcomputer chip for development control of a game machine having a central processing unit for executing a game program based on an application program and user data. 2. A rewritable storage device in which a predetermined area stores an application program, an identification code and an encrypted identification code for each type of gaming machine, and a check code calculated based on the application program, the identification code, and the encrypted identification code. When the built-in ROM, the built-in RAM in which the data for the user program is written and external data rewriting is prohibited, and whether the recognition code is correct based on the recognition code transmitted from the outside and the recognition code match. Scan the rewritable internal ROM to determine whether the program written in the rewritable internal ROM has been certified, and compare the check code with the check code stored in the rewritable internal ROM. Identification means to perform and written in rewritable internal ROM A central processing unit for executing a game program based on an application program and user data, and an unauthorized address execution prohibition control circuit for prohibiting execution of a program other than the rewritable internal ROM. Microcomputer chip for gaming machine control