JPH07297719A - A/d converter - Google Patents

Abstract

PURPOSE:To simplify software for CPU control by providing an A/D control section sending a conversion start signal to an A/D converter only with application of a conversion command and giving interrupt information to a CPU only when a conversion end signal is inputted to the A/D converter. CONSTITUTION:A master clock MCK is always fed to an A/D control section 2, which receives a conversion start command AST from a CPU and starts counting the clock MCK only when the command is received. Then the control section 2 gives the clock to an A/D converter 1 as a conversion clock CK. Furthermore, the control section 2 gives a conversion start signal ST to the A/D converter 1 when the count reaches a prescribed count and then the A/D converter 1 starts the conversion. Upon the receipt of a conversion end EC from the A/D converter 1, the A/D control section 2 generates an interrupt IRQ and gives it to the CPU as the data read timing. The CPU provides a read signal RD to read the converted data. Since the CPU executes only the conversion command and data read, the control of the CPU is remarkably simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter used when converting an analog signal into a digital signal.

Generally, analog / digital (hereinafter referred to as A /
A clock (C) is used to operate the converter.
It is necessary to input analog signals to the A / D converter while controlling the timing of signals such as K), conversion start signal (ST), and data read signal (RD).

Therefore, when operating the A / D converter under the control of the CPU, the external control software becomes complicated, and it is necessary to simplify the external control software.

[0004]

2. Description of the Related Art FIG. 8 is an explanatory view of a conventional example. FIG. 8A is a configuration diagram of a main part and FIG. 8B is an example of an A / D conversion time chart.

Hereinafter, the operation of FIG. 8 will be described assuming that the analog input is 10V and the D / A conversion portion is 4 bits ("1111" becomes 15V). The code on the left side of (b) shows the waveform of the part of the same code of (a).

First, the clock (CK) in (b) is constantly supplied to the A / D converter during A / D conversion. Conversion start signal (S
Although (T) is sent from a CPU (not shown), this is a signal for starting the comparison between the analog input and the output of the D / A conversion part in the comparator 11, and the conversion end signal (EC) is A /
Since the D conversion has been completed, the CPU sends a data read signal (RD) to a flip-flop (hereinafter abbreviated as FF) to read the conversion data stored in FF as described later.

Next, in (a), the successive approximation control section 12
When the conversion start signal (ST) is input, sets "1000" to the D / A conversion part 14. Therefore, the D / A conversion part converts this to an analog value 8V and outputs it to the comparator 11, which then inputs the analog input 10V and the analog value 8V.
Are compared and the comparison result is sent to the successive approximation control unit 12.

The successive approximation control part determines the MSB from the comparison result.
"1" is judged to be correct, then "1100" is set in the D / A conversion part and compared, but at this time the analog input is smaller. Therefore, the successive approximation control unit 12 modifies and stores "11" to "10", performs the same operation as described above for the third and fourth bits, and finally sets "1010" to a flip-flop (hereinafter, FF). It is stored in 13 and the conversion end signal (EC) is sent to the CPU. As a result, the CPU sends the data read signal (RD) to FF 13 as described above, and reads the conversion data “1010” from here.

The reference voltage setting portion 15 in the figure is a D / A
It is for setting the reference voltage of the conversion part. Now,
The successive approximation type described above is known as a method that has a good balance of conversion speed, accuracy, cost, etc., but in order to operate the successive approximation control part, the clock (CK), conversion start signal (S
It is necessary to input analog signals to the A / D converter while controlling the timing of signals such as T) and data read signal (RD).

In order to reduce the power consumption, these signals are
In many cases, control is performed such that input is only made during A / D conversion.
Therefore, the software becomes complicated when operating the A / D converter under the control of the CPU.

Further, time-divisional A / D conversion control when performing A / D conversion in two or more systems is also a cause of complicating the software.

[0012]

[Problems to be Solved by the Invention] As described above, when the A / D conversion is one system, to know whether the A / D conversion is completed,
As shown in FIG. 8 (b)-, whether or not the conversion end signal (EC) has changed from H to L is monitored at certain time intervals. Further, in order to reduce the power consumption, the control signal is not input when the control signals such as the clock (CK) and the conversion end signal (EC) are not used, which complicates the software for single control.

Furthermore, with one A / D converter, two or more systems
A / D conversion is often performed (to reduce power consumption and size), but at this time, it is said that the time-division control software for making it possible to correctly switch between analog input and digital output becomes complicated. There are two problems.

It is an object of the first to third aspects of the present invention to simplify software when operating an analog / digital converter under the control of a CPU.

[0015]

FIG. 1 is a principle block diagram of the first present invention, and FIG. 2 is a principle block diagram of the third present invention. In the figure, 1 is an analog / digital converter, and 2 is a conversion start signal (ST) generated using an input clock only while a conversion start instruction (AST) from the outside is being applied. A conversion start signal is sent to the analog / digital converter, and a conversion end signal is sent from the analog / digital converter.
When (EC) is input, interrupt information (I
It is a first analog / digital control unit that generates RQ) and sends it to the computer.

Reference numeral 3 is a time division control unit having a timing generator and a selector, and 4 is a conversion start signal (ST) using an input clock only while an external conversion start instruction (AST) is being applied. A second analog / digital control unit for generating a read signal (RD) and interrupt information (IRQ).

Of the plurality of timing generators to which the clock is applied, 31 is always operated only by the timing generator instructed by the computer to output the timing output as the select signal, the data type information and the conversion start instruction. The timing generating unit 35 is a selector for sending an analog input signal corresponding to the input select signal from the plurality of analog input signals to the analog / digital converter.

[0018]

In the first aspect of the present invention, the signals shown in FIG. 8 are generated not by software but by hardware (A / D control section in FIG. 1).

The A / D control unit 2 shown in FIG.
(MCK) is always supplied, and when a conversion start instruction (AST) from the CPU (not shown) is received, the master clock (MCK) starts counting and the clock is converted only while this signal is input. It is sent to the A / D converter 1 as a clock (CK). Further, since the conversion start signal (ST) is sent to the A / D converter at the predetermined count value, the A / D converter 2 performs the conversion operation using the conversion clock.

When the conversion end (EC) from the A / D converter 1 is input, the A / D control unit 2 will interrupt (IRQ) the interrupt.
Is generated and CP is used as the data read timing.
Send to U. Therefore, the CPU sends a read signal (RD) to read the converted data.

Therefore, the CPU only performs conversion instructions and data reading, and the control is greatly simplified. Further, since the clock is supplied only during conversion, low power consumption is also achieved.

In the second aspect of the present invention, since the maximum value of the A / D conversion time is specified, the conversion end signal (EC) from the A / D converter is set.
Instead of waiting, the read signal (RD) is unconditionally sent after the maximum conversion time has elapsed in the A / D control unit.

In the third aspect of the present invention, the time division control function is configured by hardware and added, but the master clock (MCK) is also supplied to the timing generation section in the time division control function. This generator generates the timing specified by the CPU, and uses this output for analog input signal selection, conversion start instruction (AST) generation, data type information output, etc. The timing generator is composed of a plurality of timing generators.

Then, a pulse is generated by using the interrupt information (IRQ) sent by the A / D control unit and the data type information sent by the timing generation unit, and the data converted by using the pulse is held. It is configured to generate the interrupt status and send it to the computer.

Due to such a configuration, the CPU simply turns on / off each timing generator, which makes timing management unnecessary and the processing is greatly simplified.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram of an embodiment of an A / D control unit of the first present invention, FIG. 4 is a configuration diagram of an embodiment of an A / D control unit of the second present invention, and FIG. 2 is a block diagram of the embodiment of the timing generation unit in FIG. 2, FIG. 6 is an operation explanatory diagram of FIGS. 3, 5, and 7, (a) is the time chart of FIG. 3, (b) is the time chart of FIG. (c)
Is a time chart of FIG. 7. In addition, FIG.
It is an example of the A / D-conversion-device block diagram to which the 3rd this invention was applied.

The operation of FIGS. 3 to 7 will be described below. Figure 3
Since the master clock (MCK) is always input to the AND gate 21, the master clock (MCK) is used as the clock CK while the conversion start instruction (AST) is at H level. To the container 1. Also a binary counter
22 counts the clock CK, and when the count value becomes "10", for example, the decoder 23 sends a pulse for 1 CK to the A / D converter 1 as a conversion start signal (ST).

Here, the reason for delaying the transmission of the conversion start signal (ST) is that CK is not always input to the A / D converter.
This is to wait until the operation of this converter becomes stable. on the other hand,
When the conversion start signal (ST) is input to the A / D converter of FIG. 1, the H level conversion end signal (EC) is sent to the A / D control unit 2 as described above.
However, the conversion end signal changes from H level to L level when the conversion is completed.
It detects it at 24 and sends an interrupt (IRQ) to the CPU (not shown).

Therefore, as shown in FIG. 1, the CPU sends a read signal (RD) to the A / D converter to take out the data converted into a digital signal, and at the same time, outputs a conversion start instruction (AST) to H level → Set to the L level to cut off the supply of the master clock (MCK) to the A / D converter 1 in Fig. 1.

In FIG. 4, the master clock (MCK) input by the AND gate 41 is sent as a clock (CK) to the A / D converter 1 of FIG. 1 only while the conversion start instruction (AST) is at H level. , The part for applying this clock to the binary counter 42 has the same configuration as that of FIG. 3, but the count value is decoded by the decoders 43 to 45 and the conversion start signal (ST)
The parts that generate (RD) and interrupt (IRQ) are different.

Since the maximum value of the A / D conversion time is specified, the conversion end signal (EC) is not used and the decoder 44,
In 45, it was set to wait for the maximum conversion time above, and after this time passed, conversion was completed and data was read unconditionally. Interrupt (IRQ)
Are shifted by a half cycle with respect to the read signal (RD).

Further, in FIG. 5, the timing generator 31
For 1 to 313, only the timing generator corresponding to the switch SW turned on by the control of the CPU (not shown) is activated, and the timing output synchronized with the master clock is transmitted.

For example, when the switch SW1 is turned on to activate the timing A generator, the timing output shown by A in FIG. 6 (b) or the selector 35 in FIG. 2 is added to select the terminal analog input 1. Timing A
A / D converter 1 is connected to terminal analog input 1 only during H level. As a result, the analog input 1 is converted by the A / D converter 1 via the analog input 1.

At the same time, the H level at timing A is added to the A / D control unit 2 of FIG. 2 as a conversion start instruction (AST) via the OR gate 314. As a result, when the A / D control unit sends the conversion start signal (ST) to the A / D converter 1, the conversion end (EC) is input from the A / D converter, so the A / D control unit ends the conversion.
(EC) is used to generate an interrupt (IRQ) and CP not shown
Send to U.

At this time, the timing generator 31 of FIG. 5 sends the select data 1 out of the select data 1 to 3 to the CPU, so that the CPU (not shown) can know the type of the selected data. The select data 1 to 3 are the same as the data type information in claim 3.

In FIG. 7, as described above, the CP not shown
When the SW1 ON signal from U is input to the timing generator 31, while timing A in FIG. 6 (b) is at H level,
The analog input 1 is input to the A / D converter 1 via the selector 35.

At the same time, an H-level conversion start instruction (AST) is sent from the timing generation unit 31 to the A / D control unit 4, so that the clock is kept in the A / D control unit while the conversion start instruction (AST) is H. 4 and A / D converter 1.

Further, the A / D control unit 4 in FIG. 4 sends the conversion start signal (ST) using the input clock to the A / D converter 1 in FIG.
To the A / D converter 1, the A / D converter 1 starts A / D conversion.
However, since the A / D conversion is completed at the time when the A / D control unit 4 sends out the read signal (RD), the converted data appears on the input side of the data latch circuit 52.

On the other hand, the clock applied to the data latch circuit 52 is generated by ANDing the interrupt (IRQ) and the select data by the AND gate 51, and the data 1 converted by this clock is the data latch circuit. FF in 52
It is taken up by 521 (see Fig. 6 (c)).

The controller 53 has three FFs (because there are three timing generators), and the terminal D of the FF is
Since "1" is applied, "1" is output to the terminal Q of the corresponding FF by the output of the AND gate 51 (IRQ status in the figure).

Thus, the CPU can easily determine which data is latched by the latch circuit by checking the FF output of the interrupt controller circuit 53. As described above, in the case of the first and second aspects of the present invention, the CPU only outputs the conversion start instruction (AST) and reads the converted data. In the case of the third aspect of the present invention, the switches SW1 to SW3 are turned on / off. Timing management is unnecessary only by turning off, and the processing for A / D conversion is greatly simplified.

[0042]

As described above in detail, according to the present invention, when the analog / digital converter is operated under the control of the CPU, the external control software can be simplified.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a first present invention.

FIG. 2 is a principle configuration diagram of a third invention.

FIG. 3 is a configuration diagram of an embodiment of an A / D control unit of the first present invention.

FIG. 4 is a configuration diagram of an embodiment of an A / D control unit of the second present invention.

5 is a configuration diagram of an embodiment of a timing generation unit in FIG.

6A and 6B are operation explanatory diagrams of FIGS. 3, 5, and 7, in which FIG.
Time chart, (b) is the time chart of Fig. 5, (c)
Is a time chart of FIG. 7.

FIG. 7 is an example of a configuration diagram of an A / D conversion device to which the second and third inventions are applied.

8A and 8B are explanatory views of a conventional example, in which FIG.
It is an example of an A / D conversion time chart.

[Explanation of symbols]

1 A / D converter 2 1st A / D
Control unit 3 Time division control unit 4 Second A / D
Controller 31 Timing generator 35 Selector

Claims (3)

[Claims] 1. An analog / digital converter for operating an analog / digital converter (1) under the control of a computer to convert an analog signal into a digital signal, to which a conversion start instruction (AST) is applied from the outside. Only for a while
A conversion start signal (ST) is generated using the input clock, the clock and the conversion start signal are sent to the analog / digital converter, and the conversion end signal (EC) is input from the analog / digital converter. At this time, the analog / digital conversion device is provided with a first analog / digital control unit (2) for generating interrupt information (IRQ) using the converted signal and sending it to the computer. 2. In the above analog / digital converter, only while an external conversion start instruction (AST) is applied,
A second analog / digital control unit (4) for generating a conversion start signal (ST), a read signal (RD), and interrupt information (IRQ) by using an input clock. Converter. 3. The analog / digital converter according to claim 1, wherein, in the first and second analog / digital control units,
Of either one of the analog / digital control unit and the plurality of timing generators to which the clock is always applied,
Only the timing generator instructed by the computer operates to output the timing output as the select signal, the data type information and the conversion start instruction (3
1) and a selector (35) for sending an analog input signal corresponding to the input select signal among the plurality of analog input signals to the analog / digital converter, a time division control section (3) is provided, A pulse is generated using the interrupt information (IRQ) sent by the analog / digital controller and the data type information sent by the timing generator, and the data converted by using the pulse is held and the interrupt status is displayed. An analog / digital conversion device characterized in that it is configured to generate and send it to a computer.