JPH07297362A - Semiconductor module for electric power - Google Patents
Semiconductor module for electric powerInfo
- Publication number
- JPH07297362A JPH07297362A JP5228286A JP22828693A JPH07297362A JP H07297362 A JPH07297362 A JP H07297362A JP 5228286 A JP5228286 A JP 5228286A JP 22828693 A JP22828693 A JP 22828693A JP H07297362 A JPH07297362 A JP H07297362A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- semiconductor devices
- parallel
- power semiconductor
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、モジュールの底部に平
行に存在する軸線に沿い対として向かい合って導体路の
上に配置され並列接続されている複数個の半導体装置
と、導体路と接続されている密に隣接した互いに平行な
帯状の接続導体とを有する電力用半導体モジュールに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of semiconductor devices which are arranged on a conductor path and are connected in parallel, facing each other as a pair along an axis parallel to the bottom of a module, and connected to the conductor path. A power semiconductor module having closely adjacent strip-shaped parallel connection conductors.
【0002】[0002]
【従来の技術】1つのこのような電力用半導体モジュー
ルはたとえば既にヨーロッパ特許第 0427143号明細書お
よびドイツ実用新案第G9203000号明細書に記載されてい
る。近くに並び合って位置する平行な帯状の接続導体は
モジュールのインダクタンスを減ずる。ヨーロッパ特許
に記載されているモジュールでは4つの半導体装置を有
する対称な構成が示されている。BACKGROUND OF THE INVENTION One such power semiconductor module has already been described, for example, in EP 0427143 and German utility model G9203000. Parallel strip-shaped connecting conductors located next to each other reduce the inductance of the module. The module described in the European patent shows a symmetrical construction with four semiconductor devices.
【0003】たとえば1000A以上の大きい電流に対
しては、複数の半導体装置、たとえば6つまたはそれよ
りも多くの半導体装置が互いに並列に接続されなければ
ならない。公知のモジュールでは、6つまたはそれより
も多くの半導体装置が互いに並列に接続されると半導体
装置から接続導体への経路が相異なる長さを有する。モ
ジュールのなかのこの非対称性は個々の半導体装置の利
用可能な電流および電圧範囲を制限する。なぜならばモ
ジュール全体の特性が最大の寄生的インダクタンスを有
する半導体装置により決定されるからである。For large currents of, for example, 1000 A or more, a plurality of semiconductor devices, for example 6 or more, must be connected in parallel with each other. In known modules, when six or more semiconductor devices are connected in parallel with one another, the paths from the semiconductor devices to the connecting conductors have different lengths. This asymmetry within the module limits the available current and voltage range of individual semiconductor devices. This is because the characteristics of the entire module are determined by the semiconductor device having the maximum parasitic inductance.
【0004】[0004]
【発明が解決しようとする課題】本発明の課題は冒頭に
記載した種類の電力用半導体モジュールの電気的特性を
改善することである。The object of the invention is to improve the electrical properties of a power semiconductor module of the type mentioned at the outset.
【0005】[0005]
【課題を解決するための手段】上述の課題を解決するた
め、本発明においては、軸線の方向に相前後して位置す
る半導体装置の少なくとも1つの対およびたかだか各2
つの対が密に隣接した接続導体の少なくとも2つと接続
されており、半導体装置に関しての接続導体の位置が半
導体装置のすべての対に対して、または半導体装置の各
2つの対に対して等しく、また互いに相応する接続導体
が導体路の上側で電気的に互いに接続される。In order to solve the above-mentioned problems, according to the present invention, at least one pair of semiconductor devices and two at most two semiconductor devices located one behind the other in the axial direction are provided.
One pair being connected to at least two of the closely adjacent connecting conductors, the position of the connecting conductor with respect to the semiconductor device being equal for all pairs of semiconductor devices or for each two pairs of semiconductor devices, Corresponding connecting conductors are also electrically connected to one another above the conductor track.
【0006】本発明のその他の構成は請求項2以下にあ
げられている。Other structures of the present invention are set forth in the second and subsequent claims.
【0007】[0007]
【実施例】以下、図1ないし6に示す実施例により本発
明を一層詳細に説明する。EXAMPLES The present invention will be described in more detail with reference to the examples shown in FIGS.
【0008】図1による電力用半導体モジュールは金属
製の底部1を有し、その上に絶縁層2が配置されてい
る。絶縁層2は導体路3、4および5を有する。導体路
の上に対称軸線12に対して鏡面対称に半導体装置10
および11が取付けられている。これらの半導体装置は
たとえば電界効果制御される半導体デバイス6および逆
並列に接続されたダイオード7から成っている。電界効
果制御される半導体デバイスはたとえばMOSFETま
たはIGBT(絶縁ゲートバイポーラトランジスタ)で
あってよい。半導体デバイスの一方の面は直接に導体路
3と接触し、他方の面はボンドワイヤーを介して導体路
4と接触している。導体路5は制御端子との接触の役割
をする。The power semiconductor module according to FIG. 1 has a bottom 1 made of metal, on which an insulating layer 2 is arranged. The insulating layer 2 has conductor tracks 3, 4 and 5. On the conductor path, the semiconductor device 10 is mirror-symmetrical with respect to the symmetry axis 12.
And 11 are attached. These semiconductor devices include, for example, a field-effect controlled semiconductor device 6 and a diode 7 connected in antiparallel. The field effect controlled semiconductor device may be, for example, a MOSFET or an IGBT (insulated gate bipolar transistor). One side of the semiconductor device is in direct contact with the conductor track 3 and the other side is in contact with the conductor track 4 via bond wires. The conductor track 5 serves for contact with the control terminal.
【0009】導体路3、4は導体路の上に垂直に立って
いる接続導体8または9と接続されている。これらの接
続導体は帯状であり、互いに平行に位置し、また密に並
び合って配置されている。The conductor tracks 3, 4 are connected to a connecting conductor 8 or 9 which stands vertically above the conductor track. These connecting conductors are strip-shaped, are arranged parallel to each other, and are arranged closely aligned.
【0010】同じ底部1の上に、モジュールの所望の通
電能力に応じて、半導体装置10、11に等しい複数の
半導体装置が設けられている。その際に互いに鏡面対称
に向かい合って位置する半導体装置の各対は2つの接続
導体8、9を有する。半導体装置に関しての接続導体の
位置は対称軸線12の方向に半導体装置の各対に対して
等しい。すなわち底部1の上に通電能力に相応する数
の、接続導体および半導体装置から成る互いに完全に等
しいユニットが配置されている。各対の半導体装置1
0、11は接続導体8、9により並列に接続されてい
る。各対の接続導体8、9は導体路の上側で帯状または
板状の結合導体により互いに結合される。その際にすべ
ての接続導体8は第1の結合導体により、またすべての
結合導体9は第2の接続導体により電気的に一括され
る。A plurality of semiconductor devices equal to the semiconductor devices 10 and 11 are provided on the same bottom 1 according to the desired energizing ability of the module. In this case, each pair of semiconductor devices, which are mirror-symmetrically opposed to each other, has two connecting conductors 8, 9. The position of the connecting conductors with respect to the semiconductor device is equal for each pair of semiconductor devices in the direction of the axis of symmetry 12. In other words, on the bottom part 1, a completely equal number of units of connecting conductors and semiconductor devices are arranged corresponding to the current carrying capacity. Each pair of semiconductor devices 1
0 and 11 are connected in parallel by connecting conductors 8 and 9. The connecting conductors 8, 9 of each pair are connected to one another by means of a band-shaped or plate-shaped connecting conductor on the upper side of the conductor track. All connecting conductors 8 are electrically bundled together by the first coupling conductors, and all coupling conductors 9 are electrically bundled together by the second coupling conductors.
【0011】図1による配置の電気的等価回路が図3に
示されている。半導体装置の各々はIGBTおよびそれ
に並列に接続されているフリーホィーリングダイオード
7から成っている。An electrical equivalent circuit of the arrangement according to FIG. 1 is shown in FIG. Each of the semiconductor devices comprises an IGBT and a freewheeling diode 7 connected in parallel with it.
【0012】図2による実施例も金属製の底部1の上に
構成されている。ここで対称軸線12に対して鏡面対称
に、各4つの導体路15、16、17、18を有する半
導体装置27、28が向かい合って位置している。導体
路15の上にはフリーホィーリングダイオード21が配
置されており、導体路17の上には電界効果制御される
半導体デバイス20および逆並列に接続された保護ダイ
オード22が配置されている。図2による配置の電気的
等価回路が図4に示されている。それは端子+、交流、
−を有するブリッジ枝路であり、ダイオード21とIG
BT20との直列回路から成っており、IGBT20に
は保護ダイオード22が逆並列に接続されている。+端
子は導体路15に、交流端子は導体路16に、また−端
子は導体路17に相当する。導体路18はIGBT20
のゲート端子と接続されている。The embodiment according to FIG. 2 is also constructed on a bottom 1 made of metal. Here, semiconductor devices 27, 28 each having four conductor paths 15, 16, 17, 18 are located facing each other in mirror symmetry with respect to the axis of symmetry 12. A freewheeling diode 21 is arranged on the conductor track 15, and a semiconductor device 20 controlled by field effect and a protection diode 22 connected in antiparallel are arranged on the conductor track 17. The electrical equivalent circuit of the arrangement according to FIG. 2 is shown in FIG. It is terminal +, alternating current,
Is a bridge branch having-
It is composed of a series circuit with the BT 20, and a protection diode 22 is connected to the IGBT 20 in antiparallel. The + terminal corresponds to the conductor path 15, the AC terminal corresponds to the conductor path 16, and the-terminal corresponds to the conductor path 17. The conductor path 18 is an IGBT 20.
It is connected to the gate terminal of.
【0013】導体路15、16および17は、それぞれ
導体路の面に対して垂直に互いに平行にまた密に並び合
って配置されている3つの接続導体24、25および2
6と接続されている。これらの接続導体は互いに鏡面対
称に向かい合って位置する半導体装置27、28のそれ
ぞれ1つの対を並列に接続する。The conductor tracks 15, 16 and 17 are respectively three connecting conductors 24, 25 and 2 which are arranged perpendicular to the plane of the conductor track, parallel to each other and closely aligned.
It is connected with 6. These connecting conductors connect in parallel one pair of semiconductor devices 27 and 28, respectively, which are mirror-symmetrically opposed to each other.
【0014】底部1の上にモジュールの通電能力に応じ
て互いに鏡面対称に向かい合って位置する半導体装置の
別の対が配置されている。これらの別の対の半導体装置
は図1による実施例の場合と同じく第1の対と同一であ
る。それらはそれぞれ3つの接続導体24、25、26
により接触させられる。半導体装置の各対の接続導体は
再び導体路の面の上で各1つの結合導体により互いに結
合される。この場合には3つの結合導体が必要である。Another pair of semiconductor devices, which are mirror-symmetrically opposed to each other, are arranged on the bottom portion 1 in accordance with the energizing ability of the module. These other pairs of semiconductor devices are identical to the first pair, as in the embodiment according to FIG. They have three connecting conductors 24, 25, 26 respectively.
To contact. The connecting conductors of each pair of semiconductor devices are again connected to each other on the plane of the conductor track by one connecting conductor. In this case, three coupling conductors are required.
【0015】図1および図2によるモジュールの対称な
構成により、半導体デバイス6、7、20、21、22
から対応付けられている接続導体への経路は常に等し
い。この対称性は各装置に対する等しい寄生的インダク
タンス、従ってまた改善された電気的特性に通ずる。Due to the symmetrical construction of the module according to FIGS. 1 and 2, the semiconductor devices 6, 7, 20, 21, 22 are provided.
To the associated connecting conductor is always equal. This symmetry leads to equal parasitic inductances for each device and thus also improved electrical properties.
【0016】図5には、再び対称軸線12に対して鏡面
対称に向かい合って位置している半導体装置10、11
の対から成る電力用半導体モジュールが示されている。
半導体装置10、11に対して鏡面対称に同じ導体路3
の上に別の半導体装置10´、11´が配置されてお
り、第2の対称軸線29は導体路の面内に、また第1の
対称軸線12に対して直角に位置している。対10、1
1および10´、11´は単一の対の接続導体8、9に
より接触させられる。底部1の上に次いで所望の通電能
力に応じて複数のこのような二重対または四重配置が構
成されている。二重対または四重配置の各々は接続導体
対8、9により接触させられる。各四重グループの個々
の接続導体対8、9は次いで再び導体路の上側で結合導
体により接触させられている。制御端子に対して必要と
される導体路はここでは図面を見易くするために図示を
省略されている。図2によるモジュールに相応する配置
は推奨される。In FIG. 5, the semiconductor devices 10 and 11 are positioned so as to face each other in mirror symmetry with respect to the axis of symmetry 12 again.
A power semiconductor module consisting of a pair of is shown.
The same conductor path 3 is mirror-symmetrical to the semiconductor devices 10 and 11.
Another semiconductor device 10 ′, 11 ′ is arranged on top of it, the second axis of symmetry 29 being located in the plane of the conductor track and at a right angle to the first axis of symmetry 12. Pair 10, 1
1 and 10 ', 11' are contacted by a single pair of connecting conductors 8, 9. A plurality of such double pair or quadruple arrangements are then arranged on the bottom 1 depending on the desired current carrying capacity. Each double pair or quad arrangement is contacted by connecting conductor pairs 8,9. The individual connecting conductor pairs 8, 9 of each quadruple group are then again brought into contact by a connecting conductor on the upper side of the conductor track. The conductor tracks required for the control terminals are omitted here for the sake of clarity. An arrangement corresponding to the module according to FIG. 2 is recommended.
【0017】図5による二重化された鏡面対称な構成は
たとえば図2による装置に対しても応用され得る。その
場合、同じく半導体デバイス6または20、21の各々
から対応付けられている接続導体への経路は等しい。そ
れによって寄生的インダクタンスも等しく、また電力用
半導体モジュールの良好な利用可能性が保証されてい
る。The duplicated mirror-symmetrical configuration according to FIG. 5 can also be applied to the device according to FIG. In that case, the paths from each of the semiconductor devices 6 or 20, 21 to the associated connecting conductors are also equal. Thereby, the parasitic inductance is also equal and a good availability of the power semiconductor module is guaranteed.
【0018】本発明は、制御端子と接続されている導体
路の各々が接続導体と接続されており、またこれらの接
続導体が負荷電流に対する接続導体に相応して導体路の
上側で互いに接続されるようにすることによりさらに改
善される。According to the invention, each of the conductor tracks connected to the control terminal is connected to a connecting conductor and these connecting conductors are connected to one another above the conductor track corresponding to the connecting conductors for the load current. It is further improved by doing so.
【0019】図6には、互いに付属する接続導体対8、
9がどのように互いに接続されるかが示されている。こ
の接続は、それぞれ接続導体9または8を互いに結合す
る結合導体30、31により行われる。接続導体8、9
の相異なる高さは単に図面を見易くするために選ばれた
ものであり、実際にはすべての接続導体の高さは等しい
ことが目的にかなっている。結合導体30、31はケー
スのなかに位置し得る。しかし、それらがケースの上に
位置することは目的にかなっている。なぜならば、その
ようにして複数の電力用半導体モジュールを互いに並列
に接続することができるからである。FIG. 6 shows a pair of connecting conductors 8 attached to each other.
It is shown how 9 are connected to each other. This connection is made by means of coupling conductors 30, 31 which respectively connect the connection conductors 9 or 8 to one another. Connection conductors 8 and 9
The different heights of are chosen merely to make the drawing easier to see, and in practice it is intended that all connecting conductors have the same height. The coupling conductors 30, 31 may be located inside the case. However, it is purposeful that they are located on the case. This is because a plurality of power semiconductor modules can be connected in parallel with each other in this way.
【0020】図1、2及び5による実施例によれば、通
電部の十分な対称性が得られる。対称性に対する要求が
それほど高くない場合には、軸線12、29の両側に、
単に同一の、又は構造上でも互いに異なる半導体装置を
配置して十分である。その場合対称軸線12は、モジュ
ールの軸線、ここでは底部1に平行で接続導体の面に直
通に走る長手軸線になる。図5の実施例における軸線2
9は、接続導体の面及び底部1に平行に存在する軸線に
なる。According to the embodiment according to FIGS. 1, 2 and 5, sufficient symmetry of the current carrying part is obtained. If the symmetry requirements are not very high, on either side of the axes 12, 29,
It is sufficient to arrange semiconductor devices that are identical or different in structure. The axis of symmetry 12 then becomes the axis of the module, here the longitudinal axis parallel to the bottom 1 and running straight through the plane of the connecting conductor. Axis 2 in the embodiment of FIG.
9 is the axis lying parallel to the plane of the connecting conductor and the bottom 1.
【図1】第1の実施例の平面図。FIG. 1 is a plan view of a first embodiment.
【図2】第2の実施例の平面図。FIG. 2 is a plan view of the second embodiment.
【図3】図1の等価回路。FIG. 3 is an equivalent circuit of FIG.
【図4】図2の等価回路。FIG. 4 is an equivalent circuit of FIG.
【図5】第3の実施例の平面図。FIG. 5 is a plan view of the third embodiment.
【図6】図5による配置の側面図。FIG. 6 is a side view of the arrangement according to FIG.
1 金属製の底部 2 絶縁層 3〜5 導体路 6 半導体デバイス 7 ダイオード 8、9 接続導体 10、11 半導体装置 12 対称軸線 15〜18 導体路 20 半導体デバイス 21 フリーホィーリングダイオード 22 保護ダイオード 24〜26 接続導体 27、28 半導体装置 1 Metal Bottom 2 Insulating Layer 3-5 Conductor Path 6 Semiconductor Device 7 Diode 8, 9 Connection Conductor 10, 11 Semiconductor Device 12 Symmetry Axis 15-18 Conductor Path 20 Semiconductor Device 21 Free Wheeling Diode 22 Protective Diode 24- 26 connection conductor 27, 28 semiconductor device
───────────────────────────────────────────────────── フロントページの続き (71)出願人 390041531 オイペック、オイロペイツシエ、ゲゼルシ ヤフト、フユア、ライスツングスハルプラ イター、ミツト、ベシユレンクテル、ハフ ツング、ウント、コンパニ、コマンデイー ト、ゲゼルシヤフト EUPEC EUROPAEISCHE GESELLSCHAFT FUER L EISTUNGSHALBLEITER MIT BESCHRANKTER HA FTUNG + COMPANY・KOM MADITGESELLSCHAFT ドイツ連邦共和国ワルシユタインベレツケ (番地なし) (71)出願人 390039413 シーメンス アクチエンゲゼルシヤフト SIEMENS AKTIENGESEL LSCHAFT ドイツ連邦共和国 ベルリン 及び ミユ ンヘン (番地なし) (72)発明者 ゲルハルト シユルツエ ドイツ連邦共和国 59557 リツプシユタ ツト アムシヤイネバツハ 21 (72)発明者 カール‐ハインツ ゾンマー ドイツ連邦共和国 59581 ワルシユタイ ン 2 ゲーテシユトラーセ 12 (72)発明者 ラインホルト シユパンケ ドイツ連邦共和国 59909 ベストヴイツ ヒ 6 ハ‐リユプケ‐シユトラーセ 52 (72)発明者 ゲオルギ パツプ ドイツ連邦共和国 91058 エルランゲン ブンゼンシユトラーセ 16 1/3 (72)発明者 ワルター シユプリングマン ドイツ連邦共和国 91325 アデルスドル フ オーベレバツハガツセ 10 ベー (72)発明者 ペーター ツヴアンチガー ドイツ連邦共和国 90453 ニユルンベル ク 60 レンバーンシユトラーセ 45 ─────────────────────────────────────────────────── ─── Continuation of the front page (71) Applicant 390041531 Eupec, Europaitsie, Gezershyaft, Fuyuah, Rice Tungsharpruiter, Mitt, Besilyenktel, Haftung, und, Companie, Elefels Echels Echels Echels Echels Echeles Echels Eucels Eur Essels Euceles Essels BESCHRANKTER HA FTUNG + COMPANY / COMM KOM MADIT GESELLSCHAFT Germany Federal Republic of Warszytine Belekke (No address) (71) Applicant 390039413 Siemens Aktingezel Syaft SIEMENS AKTIENGES L LSCHAFT Federal Republic of Germany Berlin and Miyunchen (no street number) (72) Inventor Gerhard Schiurtze, Federal Republic of Germany 59557 Ripschutt Amsijne Batcha 21 (72) Inventor Karl-Heinz Sommer, Federal Republic of Germany 59581 Warschyutain 2 Goethesutler Se 12 (72) Inventor Reinhold Scheupanke Germany 59909 Bestweit He 6 Ha-Rhyupke-Schyutrase 52 (72) Inventor Georgi Patp Germany 91058 Erlangen Bunsen Schutlerse 16 1/3 (72) Inventor Walter Scheu Pringmann Germany 91325 Adelsdorf Oberer Bacz Haggatse 10 Be (72) Inventor Peter Zwungerger Germany 90453 Nyurnberg 60 Renbahn Schutlerse 45
Claims (7)
に沿い対として向かい合って導体路上に配置され並列接
続されている複数個の半導体装置と、導体路と接続され
ている密に隣接した互いに平行な帯状の接続導体とを有
する電力用半導体モジュールにおいて、軸線(12)の
方向に相前後して位置する半導体装置(10、11;2
7、28)の少なくとも1つの対およびたかだか各2つ
の対が密に隣接した接続導体(8、9;24、25、2
6)の少なくとも2つと接続されており、半導体装置に
関しての接続導体の位置が半導体装置のすべての対に対
して、または半導体装置の各2つの対に対して等しく、
また互いに相応する接続導体が導体路の上側で電気的に
互いに接続されていることを特徴とする電力用半導体モ
ジュール。1. A plurality of semiconductor devices, which are arranged in parallel on a conductor track and face each other as a pair along an axis parallel to the bottom of a module, and closely adjacent parallel devices connected to the conductor track. In a power semiconductor module having a strip-shaped connecting conductor, semiconductor devices (10, 11; 2) located one behind the other in the direction of the axis (12).
7, 28) and at most two pairs each of which are closely adjacent to each other (8, 9; 24, 25, 2).
6) connected to at least two and the position of the connecting conductor with respect to the semiconductor device is equal for all pairs of semiconductor devices or for each two pairs of semiconductor devices,
A power semiconductor module, characterized in that the corresponding connecting conductors are electrically connected to one another above the conductor track.
接続された各2つの対(10、11;10´、11´)
において接続導体(8、9)が2つの対の間に配置され
ていることを特徴とする請求項1記載の電力用半導体モ
ジュール。2. Two pairs (10, 11; 10 ', 11') connected in parallel, one behind the other in the direction of the axis.
2. The power semiconductor module according to claim 1, characterized in that the connecting conductors (8, 9) are arranged between the two pairs.
デバイス(6、20)であり、それらに各1つのフリー
ホィーリングダイオード(7、22)が逆並列に接続さ
れていることを特徴とする請求項1または2記載の電力
用半導体モジュール。3. The semiconductor device is a field effect controlled semiconductor device (6, 20), to which one free wheeling diode (7, 22) is connected in anti-parallel. The power semiconductor module according to claim 1 or 2.
電界効果制御される半導体デバイス(20)から成る直
列回路を含んでおり、直列回路の節点が導体路(15)
を介して、他方の2つの接続導体(25、26)に密に
隣接している第3の帯状の接続導体(24)と接続され
ており、また第3の接続導体(24)が導体路の上側で
互いに接続されていることを特徴とする請求項1または
2記載の電力用半導体モジュール。4. The semiconductor device comprises a series circuit consisting of a diode (21) and a field effect controlled semiconductor device (20), the node of the series circuit being a conductor track (15).
Via a third strip-shaped connecting conductor (24) closely adjacent to the other two connecting conductors (25, 26), and the third connecting conductor (24) is a conductor path. 3. The power semiconductor module according to claim 1, wherein the power semiconductor modules are connected to each other on the upper side of the.
半導体装置がモジュールの軸線に対し鏡面対称に構成さ
れていることを特徴とする請求項1記載の電力用半導体
モジュール。5. The power semiconductor module according to claim 1, wherein the semiconductor devices facing each other along the axis (12) are mirror-symmetrical with respect to the axis of the module.
対(10、10´、11、11´)がそれぞれ接続導体
の面に対し鏡面対称に構成されていることを特徴とする
請求項2記載の電力用半導体モジュール。6. The pair of semiconductor devices (10, 10 ′, 11, 11 ′) existing on both sides of the connection conductor are mirror-symmetrical with respect to the plane of the connection conductor. The power semiconductor module described.
り、また接続導体がケースの外側で接続導体(30、3
1)により互いに接続されていることを特徴とする請求
項1ないし6の1つに記載の電力用半導体モジュール。7. A semiconductor device is surrounded by a case, and a connecting conductor is provided outside the case.
7. The power semiconductor module according to claim 1, wherein the power semiconductor modules are connected to each other by means of 1).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP92114544 | 1992-08-26 | ||
AT92114544.7 | 1992-08-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07297362A true JPH07297362A (en) | 1995-11-10 |
JP3268081B2 JP3268081B2 (en) | 2002-03-25 |
Family
ID=8209943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22828693A Expired - Lifetime JP3268081B2 (en) | 1992-08-26 | 1993-08-20 | Power semiconductor module |
Country Status (3)
Country | Link |
---|---|
US (1) | US5459356A (en) |
JP (1) | JP3268081B2 (en) |
DE (1) | DE59304797D1 (en) |
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-
1993
- 1993-08-12 DE DE59304797T patent/DE59304797D1/en not_active Expired - Lifetime
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-
1995
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Also Published As
Publication number | Publication date |
---|---|
US5459356A (en) | 1995-10-17 |
JP3268081B2 (en) | 2002-03-25 |
DE59304797D1 (en) | 1997-01-30 |
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