JPH07296594A - Sample-hold circuit - Google Patents

Abstract

PURPOSE:To accelerate large amplitude response by connecting a switch circuit shifting sample operation and hold operation based on a mode switch output current of a switch drive circuit to the prestage of a hold capacitor. CONSTITUTION:When a voltage so as to become a sample operation state is applied to a control terminal 17, a current flows from the output terminal OUT1 to the 0UT2 side of the switch drive circuit 18, and transistors Q1, Q2, Q4, Q5 are biassed forward, and the Q3, Q6 are biassed backward. At thus time, an output voltage of a switch circuit 16 is controlled by the voltage of an input terminal 11, and the voltage of the terminal 11 is transmitted to the output terminal 14. The charge/discharge of the hold capacitor 13 is performed by the Q2, Q5. On the other hand, when the voltage so as to become a hold operation state is applied to the terminal 17, the current flows from the OUT2 to the OUT1 of the circuit 18, and the output of the circuit 16 becomes high impedance, and the voltage of the terminal 14 becomes the voltage held to the capacitor 13. Thus, the response is accelerated without increasing power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device in a digital copying machine or a digital color copying machine, an image data input device in DTP (desktop publishing) or a computer, a document reading device in a facsimile, or an image pickup device such as a VTR. , A discrete IC, a hybrid IC, or a monolithic I for high-speed processing of an output signal from a photoelectric conversion element such as a CCD that outputs an electric signal according to the amount of input light in time series.
The present invention relates to a sample and hold circuit having a C configuration.

[0002]

2. Description of the Related Art Generally, in an image input device such as a scanner of this type, a light amount distribution of a light source for illuminating a document, a CCD
Since there are factors such as the sensitivity distribution of the photoelectric conversion element such as
It is difficult to treat the photoelectric conversion signal obtained from the CCD or the like as an image signal as it is, and it is necessary to remove such an unnecessary factor. Therefore, in this type of image input device, a time series obtained from the CCD is used to change the level of the image signal in order to change the level of the image signal by following the maximum voltage detected for the image signal, for example, to determine the reference white level. A sample and hold circuit for sampling the signal of and holding the peak value is provided.

In such a sample hold circuit, for example, as shown in FIG. 16, an input buffer 2 that takes in a time series signal from a photoelectric conversion element such as a CCD from an input terminal 1 is used.
A hold capacitor 3, an output buffer 5 connected between the hold capacitor 3 and the output terminal 4,
It is composed of a switch circuit 6 for switching between a sample operation state and a hold operation state, and a switch drive circuit 8 for switching the state of the switch circuit 6 based on a control signal given to a control terminal 7. A feedback resistor R _F1 for defining the potential of the switch circuit 6 in the hold operation state is connected between the output buffer 5 and the switch circuit 6. Here, in the sample hold circuit in the illustrated embodiment, the switch circuit 6 four diodes D ₁ to D
_A bridge circuit is formed by 4 and four diodes D _{5 to} D ₈ having opposite polarities are connected in series between the connecting midpoints thereof to form a high-speed sample-hold circuit which speeds up the switching operation. . More specifically, between the _two ends of the diodes D ₁ and D ₂ , the diode D ₃ ,
The ends of D _{4 and} the ends of the diodes D _{5 to} D ₈ are connected between the output terminals OUT1 and OUT2 of the switch drive circuit 8, and the output side of the input buffer 2 is connected to the connection midpoint of the diodes D ₁ and D _2. The hold capacitor 3 (the input side of the output buffer 5) is connected to the connection midpoint of the diodes D ₃ and D ₄ , and one end of the feedback resistor R _F1 is connected to the connection midpoint of the diodes D ₆ and D _7. ing.

In such a configuration, when the control terminal 7 is set to a voltage at which the high speed sample and hold circuit is in the sampling operation state, a current flows from the output terminal OUT1 of the switch drive circuit 8 to the output terminal OUT2 side. . In this state, the diodes D _{1 to} D ₄ are forward biased and the diodes D _{5 to} D ₈ are reverse biased, and the voltage of the input terminal 1 is transmitted to the output terminal 4.

On the other hand, when the control terminal 7 is switched to a voltage at which the high-speed sample hold circuit is in the hold operation state, a current flows from the output terminal OUT2 of the switch drive circuit 8 toward the output terminal OUT1 side. Then, in the switch circuit 6, the diodes D _{1 to} D ₄ are reverse biased and the diodes D _{5 to} D ₈ are forward biased, and the output of the switch circuit 6 becomes high impedance. Therefore, output terminal 4
Is the voltage held by the hold capacitor 3 and is constant regardless of the change in the voltage of the input terminal 1.

[0006]

However, as shown in FIG.
In the case of the high-speed sample-hold circuit having the configuration as shown in FIG. 3, the hold capacitor 3 is charged and discharged when the voltage on the output side of the switch circuit 6 changes by the bias current of the switch circuit 6 having the diode bridge configuration. The large amplitude response of this circuit is limited by the bias current of the switch circuit 6. Therefore, it is necessary to increase the bias current of the switch circuit 6 in order to realize high-speed large-amplitude response, but increasing the bias current of the switch circuit 6 having the diode bridge structure increases the power consumption of the circuit. This is not desirable.

Therefore, according to the present invention, in constructing a high-speed sample-hold circuit, a switch circuit is provided which solves the problem of the large-amplitude response of the hold capacitor and can speed up the large-amplitude response without increasing the power consumption. Another object of the present invention is to provide a sample hold circuit.

Further, it is an object of the present invention to prevent destruction and deterioration of its constituent elements when such a switch circuit is realized. In addition, the switching speed at the time of mode switching between the sample operation and the hold operation is prevented from being limited by the charging / discharging of the parasitic capacitance attached to the output terminal of the switch drive circuit, etc., and the charging / discharging of the parasitic capacitance is accelerated. It is also intended to increase the mode switching speed by increasing the speed. Furthermore, it is also an object to prevent noise generated at the time of mode switching between the sample operation and the hold operation from being transmitted to the next stage through a feedback circuit which defines the potential of the hold operation state of the switch circuit. It is also an object to reduce droop generated when a part of the current of the switch circuit flows in the hold capacitor during the hold operation.

[0009]

A sample and hold circuit according to a first aspect of the present invention samples an output signal from a photoelectric conversion element such as a CCD which outputs an electric signal in accordance with the amount of input light in time series, and determines its peak value. In a sample-hold circuit provided with a hold capacitor for holding in the preceding stage of an output buffer, a switch circuit formed by a bridge circuit formed by combining a plurality of transistors to switch between a sample operation and a hold operation based on a mode switching output current of a switch drive circuit is provided. It is provided by being connected to the preceding stage of the hold capacitor. Note that this transistor does not include a diode-connected transistor.

A sample and hold circuit according to a second aspect is
In place of the switch circuit in the sample hold circuit according to claim 1, a switch circuit formed by a bridge circuit formed by combining a plurality of transistors and diodes is provided. Note that this diode includes a diode connected to a transistor.

The sample hold circuit according to claim 3 is
In place of the switch circuit in the sample hold circuit according to claim 1, a switch circuit formed by a bridge circuit formed by combining a plurality of transistors and resistors is provided. Note that this transistor does not include a diode-connected transistor.

A sample and hold circuit according to a fourth aspect is
In place of the switch circuit in the sample hold circuit according to the first aspect, a switch circuit formed by a bridge circuit formed by combining a plurality of transistors, diodes and resistors is provided. Note that this diode includes a diode connected to a transistor.

A sample and hold circuit according to claim 5 is
In addition to the configuration of the sample hold circuit according to claim 1, 2, 3 or 4, an output current limiting element is provided at the output part of the switch circuit.

A sample and hold circuit according to claim 6 is
In addition to the configuration of the sample hold circuit according to any one of claims 1, 2, 3, 4 and 5, a switching current control element for increasing a mode switching output current at the time of mode switching is set in the switch drive circuit. It is provided.

A sample and hold circuit according to a seventh aspect is
In addition to the configuration of the sample hold circuit according to claim 1, 2, 3, 4, 5 or 6, the voltage for defining the potential of the switch circuit at the time of the hold operation is different from the output voltage of the output buffer itself. A feedback circuit that generates by feedback is provided.

A sample hold circuit according to claim 8 is
In addition to the configuration of the sample hold circuit according to claim 1, 2, 3, 4, 5, 6 or 7, a droop reduction circuit for reducing droop during a hold operation is provided in the output buffer.

A sample and hold circuit according to a ninth aspect is
With respect to the configuration of the sample hold circuit according to any one of claims 1, 2, 3, 4, 5, 6, 7 or 8, a plurality of switch circuits and switch drive circuits which share the circuit elements after the hold capacitor are provided.

[0018]

In the sample hold circuit according to the first aspect of the present invention, since the switch circuit for switching between the sample operation and the hold operation is formed by the bridge circuit formed by combining a plurality of transistors, the power consumption is reduced as in the diode bridge configuration. It is possible to speed up the large-amplitude response of the switch circuit without increasing.

Also, in the sample hold circuit according to the second aspect of the invention, since the switch circuit for switching between the sample operation and the hold operation is formed by a bridge circuit formed by combining a plurality of transistors and diodes, a diode bridge configuration is provided. As described above, the large amplitude response of the switch circuit can be speeded up without increasing the power consumption.

Further, also in the sample hold circuit according to the third aspect, since the switch circuit for switching between the sample operation and the hold operation is formed by a bridge circuit formed by combining a plurality of transistors and resistors, a diode bridge configuration is provided. As described above, the large amplitude response of the switch circuit can be speeded up without increasing the power consumption. In addition, since the resistor is used, the degree of freedom in setting the bias current of the output transistor in the switch circuit is increased.

Also in the sample hold circuit according to the fourth aspect of the present invention, since the switch circuit for switching between the sample operation and the hold operation is formed by a bridge circuit formed by combining a plurality of transistors, diodes and resistors, a diode bridge configuration is adopted. As described above, the large amplitude response of the switch circuit can be speeded up without increasing the power consumption. In addition, since the resistor is used, the degree of freedom in setting the bias current of the output transistor in the switch circuit is increased.

In the sample hold circuit according to the present invention, the output portion of the switch circuit has an output current limiting element to limit the output current of the switch circuit, so that the elements forming the switch circuit are prevented from being destroyed or deteriorated. it can.

In the sample-hold circuit according to the sixth aspect, the switching-time current control element provided in the switch drive circuit makes the mode-switching output current at the time of mode switching larger than that in the steady state. The switching speed between and can be increased.

In the sample hold circuit according to the seventh aspect, the feedback circuit generates a voltage defining the potential of the switch circuit during the hold operation by feeding back an output voltage different from the output of the output buffer itself. It is possible to reduce the magnitude of noise transmitted to the output when the mode is switched.

In the sample hold circuit according to the eighth aspect, since the droop reduction circuit for reducing the droop during the hold operation is provided in the output buffer, the droop during the hold operation can be reduced.

In the sample hold circuit according to the ninth aspect, since the plurality of switch circuits and the switch drive circuit sharing the circuit elements after the hold capacitor are provided, it is possible to have a plurality of signal switching functions.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. Also in the present embodiment, the high-speed sample hold circuit basically has an input buffer 12 which takes in a time-series signal from a photoelectric conversion element such as a CCD from an input terminal 11 according to the configuration shown in FIG. Hold capacitor 13, output buffer 15 connected between this hold capacitor 13 and output terminal 14, switch circuit 16 for switching between a sample operation state and a hold operation state, and a state of this switch circuit 16 for control terminal 17 And a switch drive circuit 18 for switching based on a control signal given to the switch. Output buffer 15
A feedback resistor R _F2 is connected between the switch circuit 16 and the switch circuit 16 to form a feedback circuit 19. In the figure, V _CC indicates a positive side power source, and V _EE indicates a negative side power source (common matters in each figure).

The present embodiment is characterized in that the switch circuit 16 is formed as a bridge circuit by combining only a plurality of transistors. In other words, the Toranshijisuta Q ₁ ~Q ₃ of three of the NPN type, three of the PNP
There is a combination of a transistor Q ₄ to Q ₆ forms. That is, a bridge circuit is formed between the base and emitter of these transistors. In detail, the emitters of the transistors Q ₁ and Q ₆ are connected to each other, and these emitters are connected to the base of the transistor Q ₅ and the output terminal OUT2 side of the switch drive circuit 18. Similarly, the emitters of the transistors Q ₃ and Q ₄ are connected to each other, and these emitters are connected to the base of the transistor Q ₂ and the output terminal OUT1 side of the switch drive circuit 18. The output sides of the input buffers 12 are connected to the bases of the transistors Q ₁ and Q ₄ , respectively, and the hold capacitors 13 (the input side of the output buffer 15) are connected to the emitters of the transistors Q ₂ and Q ₅ . Further, the collector side of the transistor Q ₁ is connected to the collector side of the transistor Q ₂ ,
Similarly, the collector side of the transistor Q ₄ is connected to the collector side of the transistor Q ₅ . One end of the feedback resistor R _F2 is connected to the bases of the transistors Q ₆ and Q ₃ . Power supplies V _{CC to} V _EE are applied between the collector of the input-side transistor Q _{3 and} the collector of the transistor Q ₆ , and between the collector of the output-side transistor Q _{2 and} the collector of the transistor Q ₅ .

In such a configuration, when the control terminal 17 is set to a voltage at which the high speed sample and hold circuit of this embodiment is in the sampling operation state, the switch drive circuit 1
A current (mode switching output current) flows from the output terminal OUT1 of 8 toward the output terminal OUT2 side. In this state,
In the switch circuit 16, the transistors Q ₁ , Q ₂ ,
Q ₄ and Q ₅ are forward biased, and the remaining transistors Q ₃ and Q ₆ are reverse biased. Therefore, the switch circuit 16 is equivalently equivalent to the transistors Q ₁ , Q ₂ , Q ₄ and Q _5.
It becomes the diamond circuit configuration by. At this time, since the output voltage of the switch circuit 16 (that is, the voltage of the output terminal 14) is defined by the input voltage of the switch circuit 16 (that is, the voltage of the input terminal 11), the voltage of the input terminal 11 is applied to the output terminal 14. Transmitted. Here, the charge and discharge of the hold capacitor 13 is performed by the transistor Q _2, Q ₅ on the output side, substantially h _fe times the transistor Q ₂ with respect to the output current of the source current switch driving circuit 18, the sink current switch driving The output current of the circuit 18 can be driven up to approximately h _fe times that of the transistor Q ₅ .

On the other hand, when the control terminal 17 is set to a voltage at which the high-speed sample-hold circuit is in the hold operation state, a current (mode switching output current) flows from the output terminal OUT2 of the switch drive circuit 18 toward the output terminal OUT1. Flows. In this state, in the switch circuit 16, contrary to the above case, the transistors Q ₁ , Q ₂ , Q ₄ are reversed.
And Q ₅ are reverse biased and the remaining transistor Q
₃ and Q ₆ are forward biased. Therefore, the switch circuit 1
Since the output of 6 becomes a high impedance state, the voltage of the output terminal 14 becomes the voltage (peak voltage) held in the hold capacitor 13, and becomes constant regardless of the change in the voltage of the input terminal 11.

In this way, the sampling operation and the holding operation are performed. Switch circuit 1
6 is formed as a bridge circuit by combining only the transistors Q _{1 to} Q ₆ , and becomes a diamond circuit at the time of sample operation and becomes a high impedance state at the time of hold operation. Therefore, the switch circuit 6 having the diode bridge circuit configuration as shown in FIG. The power consumption does not increase as in the case of using, and thus the large amplitude response of the switch circuit 16 can be speeded up without any trouble. Further, even when the reverse bias cannot be applied between the collector and the emitter of the transistor used for the switch inside the discrete IC or the like, the switch circuit 16 can be configured by only the transistor.

By the way, a more specific configuration example of the entire high-speed sample-hold circuit including the switch circuit 16 having such a configuration is shown in FIG. First, the input buffer 12
PNP type transistor Q ₇ , NPN type transistor Q ₈ and resistors R ₁ and R connected to the respective emitters.
It is of the emitter-follower two-stage configuration which is formed by _2. The input terminal 11 is connected to the base of the transistor Q ₇ , and the output is taken out from the emitter side of the transistor Q ₈ so that the input voltage is equal to the output voltage.

Similarly, the output buffer 15 has a PNP type transistor Q ₉ , an NPN type transistor Q ₁₀ , and
The emitter follower has a two-stage structure formed by resistors R ₃ and R ₄ connected to the respective emitters. The input side is connected to the base of the transistor Q ₉ , and the emitter side of the transistor Q ₁₀ is connected to the output terminal 14,
The input voltage is equal to the output voltage.

On the other hand, the switch drive circuit 18 has six P
A transistor Q ₁₁ to Q ₁₆ of the NP-shaped, with six NPN type transistor Q ₁₇ to Q _22, the transistors Q ₁₃
To Q ₁₆ , Q _{19 to} Q ₂₂ , and resistors R ₅ connected to the respective emitters.
~ R ₁₂ , four resistors R _{13 to} R _16, and a transistor Q ₁₉
Is connected to the collector of the resistor R ₁₇ . Here, which form each constant current circuit and the transistor _{Q 13 ~Q 16, Q 19 ~Q} 22 and the resistor R ₅ to R ₁₂ and the resistor R _17, symmetrical transistors Q _16, Q ₂₂ are the same size, four transistors _{Q 14, Q 15, Q 20} , Q 21 is one that supplies a constant current to be the same size. Further, the resistors R _{13 to} R ₁₆ having the same resistance value constitute a level shifter, and the potential difference between the H level and the L level of the complementary control signals (IN, INB) applied to the control terminals 17 a and 17 b is determined by the transistor. The signal is transmitted to the bases of the differential pair of Q ₁₁ and Q _{12 and} the differential pair of transistors Q ₁₇ and Q ₁₈ . In the differential pair of the transistors Q _11, the differential pair and the transistor Q ₁₇ of Q _12, Q _18, in which varying the ratio of the collector current depending on the voltage difference between the control terminal 17a, 17b.

The differential pair of the transistors Q ₁₁ and Q _{12 and} the differential pair of the transistors Q ₁₇ and Q ₁₈ are composed of the transistors Q ₁₂ and
The switch circuit 1 has a configuration in which collectors of Q ₁₈ and collectors of transistors Q ₁₁ and Q ₁₇ are connected to each other.
It is connected to the 6 side. The collectors are connected to each other in such a manner that when the collector currents of the NPN type transistors Q ₁₇ and Q ₁₈ increase, the PNP type transistors Q ₁₁ and Q _{12 are connected.}
When the collector current of the NPN transistors Q ₁₇ and Q ₁₈ decreases, the PNP collector current decreases.
Since the collector current of the form transistors Q _11, Q ₁₂ of the increases, these NPN type transistors Q _17, Q ₁₈ side and a PNP transistor Q _11, Q ₁₂ side and the difference is the mode switching output current of the collector current of Is output to the switch circuit 16 side or is pulled in from the switch circuit 16 side.

Therefore, in the configuration shown in FIG. 2, the control terminals 17a and 17b are switched between the H level and the L level to switch between the sample operation state and the hold operation state. When the control terminal 17b is at the L level and the control terminal 17b is at the L level, on the contrary, when the control terminal 17a is at the L level
Is at the H level, the hold operation state is set.

The differential pairs Q ₁₁ , Q ₁₂ , Q ₁₇ , Q ₁₈ in the switch drive circuit 18 in the sample operation state.
The flow of current in the vicinity is shown by an arrow in FIG. Also, so that the differential pair _{Q 11, Q 12, Q 17} , Q 18 arrows in the showing the flow of current in the vicinity of the drawing (b) in the switch driving circuit 18 when the holding operation state.

Further, the control terminal 17a, the voltage difference between 17b, a respective differential pair Q _11, Q _12, the ratio of the collector current of the differential pair Q _17, Q ₁₈ at least two times, if possible 10 times Is set as follows.

Next, a first embodiment of the invention according to claim 2 will be described with reference to FIG. The same parts as those shown in the above-mentioned embodiments are designated by the same reference numerals (also in the following embodiments,
The same shall apply). In the present embodiment, instead of the switch circuit 16, a switch circuit 20 formed as a bridge circuit by combining a plurality of transistors and diodes is provided. Describing in comparison with the switch circuit 16, transistors Q ₁ , Q ₂ , Q ₄ , Q ₅ , which form a diamond circuit by omitting the transistors Q ₃ , Q ₆ ,
It is composed of four series-connected diodes D _{9 to} D ₁₂ connected between the bases of the transistors Q ₂ and Q ₅ .
Here, the diodes D _{9 to} D ₁₂ are connected in a polarity such that the base side of the transistor Q ₂ is the cathode side, and the connection midpoint of the diodes D ₁₀ and D ₁₁ is connected to one end of the feedback resistor R _F2 . Therefore, in the present embodiment, these diodes D _{9 to} D ₁₂ and the respective transistors Q ₁ , Q ₂ , Q.
_4, the bridge circuit across the base and emitter of Q ₅ is formed.

In such a configuration, when the control terminal 17 is set to a voltage at which the high-speed sample hold circuit of this embodiment is in the sample operation state, the switch drive circuit 1
8 flows from the output terminal OUT1 toward the output terminal OUT2 side. In this state, in the switch circuit 20, the transistors Q ₁ , Q ₂ , Q ₄ and Q ₅ are forward biased and the diodes D _{9 to} D ₁₂ are reverse biased.
Therefore, the switch circuit 20 is equivalently equivalent to the transistor Q.
_The diamond circuit configuration consists of ₁ , Q ₂ , Q ₄ and Q ₅ . At this time, the output voltage of the switch circuit 20 (that is,
Since the voltage of the output terminal 14 is defined by the input voltage of the switch circuit 20 (that is, the voltage of the input terminal 11), the voltage of the input terminal 11 is transmitted to the output terminal 14. here,
Also in this embodiment, charging and discharging of the hold capacitor 13 is performed by the transistor Q _2, Q ₅ on the output side, substantially h _fe times the transistor Q ₂ with respect to the output current of the source current switch driving circuit 18, the sync The current is almost equal to the output current of the switch drive circuit 18, h _{fe of the} transistor Q ₅ .
It can be driven up to twice.

On the other hand, when the control terminal 17 is set to a voltage at which the high speed sample hold circuit is in the hold operation state, a current flows from the output terminal OUT2 of the switch drive circuit 18 toward the output terminal OUT1 side. In this state, in the switch circuit 20, contrary to the above case, the transistors Q ₁ , Q ₂ , Q ₄ and Q ₅ are reverse biased and the diodes D _{9 to} D ₁₂ are forward biased. Therefore, the output of the switch circuit 20 is in a high impedance state, so that the voltage of the output terminal 14 becomes the voltage (peak voltage) held in the hold capacitor 13, and becomes constant regardless of the change in the voltage of the input terminal 11.

In this way, the sampling operation and the holding operation are performed. Here, switch circuit 2
0 is formed as a bridge circuit by the combination of the transistors Q ₁ , Q ₂ , Q ₄ , Q ₅ and the diodes D _{9 to} D ₁₂ , and becomes a diamond circuit at the time of sample operation.
Since the high-impedance state is set during the hold operation, the large-amplitude response of the switch circuit 20 can be speeded up without the inconvenience of increased power consumption, as in the case of the above-described embodiment.

Also, in the case of the switch circuit 20 of the present embodiment, the specific structure of the entire high speed sample hold circuit can be the same as in the case of FIG.

A second embodiment of the invention described in claim 2 will be described with reference to FIG. In this embodiment, the switch circuit 1
Instead of 6, a switch circuit 21 is provided which is formed as a bridge circuit by combining a plurality of transistors and diodes. Switch circuit 2 of the above embodiment
Explaining in comparison with 0, the transistors Q ₁ , Q ₂ , Q
Regarding ₄ and Q ₅ , diodes D ₁₃ and D ₁₄ are provided in place of the transistors Q ₁ and Q _4, and the transistors Q ₂ and Q ₅ on the output side are left. That is, instead of the diamond circuit configuration, a complementary emitter follower circuit configuration is used. Here, the diodes D ₁₃ and D ₁₄ are connected with the polarities opposite to those of the diodes D _{9 to} D ₁₂ .

In such a configuration, when the control terminal 17 is set to a voltage at which the high speed sample hold circuit of this embodiment is in the sampling operation state, the switch drive circuit 1
8 flows from the output terminal OUT1 toward the output terminal OUT2 side. In this state, in the switch circuit 21, the transistors Q ₂ and Q ₅ and the diodes D ₁₃ and D _{14 are included.}
Is forward biased, and the diodes D _{9 to} D ₁₂ are reverse biased. Therefore, the switch circuit 21 equivalently has a complementary emitter follower circuit configuration including the transistors Q ₂ and Q ₅ and the diodes D ₁₃ and D ₁₄ . At this time, the output voltage of the switch circuit 21 (that is, the output terminal 1
4) is defined by the input voltage of the switch circuit 21 (that is, the voltage of the input terminal 11), the voltage of the input terminal 11 is transmitted to the output terminal 14. Here, also in the case of the present embodiment, the charge and discharge of the hold capacitor 13 is performed by the transistors Q ₂ and Q ₅ on the output side, and the source current is almost equal to the output current of the switch drive circuit 18 by the transistor Q 2.
₂ times h _fe , and the sink current can be driven up to the output current of the switch driving circuit 18 up to h _fe times the transistor Q ₅ .

On the other hand, when the control terminal 17 is set to a voltage at which the high speed sample hold circuit is in the hold operation state, a current flows from the output terminal OUT2 of the switch drive circuit 18 toward the output terminal OUT1 side. In this state, contrary to the case in the switch circuit 21 described above, the transistors Q _2, Q ₅ and the diode D _13, D ₁₄ is reversed biased, the diode D ₉ to D ₁₂ is forward biased. Therefore, since the output of the switch circuit 21 is in a high impedance state, the voltage of the output terminal 14 becomes the voltage (peak voltage) held by the hold capacitor 13, and becomes constant regardless of the change in the voltage of the input terminal 11.

In this way, the sampling operation and the holding operation are performed. Here, switch circuit 2
1 is formed as a bridge circuit in combination with the transistor Q _2, Q ₅ and the diode D ₉ to D _14, at the time of sampling operations become complementary emitter follower circuit, since a high impedance state when the hold operation, the embodiment described above As in the case, the large-amplitude response of the switch circuit 21 can be speeded up without inconvenience that power consumption increases.

Also in the case of the switch circuit 21 of the present embodiment, the specific structure of the entire high speed sample hold circuit can be the same as in the case of FIG.

An embodiment of the invention described in claim 3 will be described with reference to FIG. In the present embodiment, instead of the switch circuit 16, a switch circuit 22 formed as a bridge circuit by combining a plurality of transistors and resistors is provided. Explaining in comparison with the switch circuit 16, resistors R ₂₃ and R ₂₄ are added to the emitter sides of the output side transistors Q ₂ and Q ₅ , respectively. Therefore, in this embodiment, a bridge circuit is formed between the resistors R ₂₃ and R ₂₄ and the base and emitter of each of the transistors Q ₁ , Q ₂ , Q ₄ and Q ₅ .

In such a configuration, the sampling operation and the holding operation of this embodiment are similar to those of the switch circuit 16 described with reference to FIG. However, in the case of the present embodiment, the transistor Q
The bias currents of ₂ and Q ₅ can be changed by the resistors R ₂₃ and R _{24 with} respect to the output current of the switch drive circuit 18.

Therefore, in the case of this embodiment, in addition to the effect of the embodiment shown in FIG. 1, the output side transistor Q ₂ ,
The degree of freedom in setting the bias current of Q ₅ can be increased by the resistors R ₂₃ and R ₂₄ .

Also, in the case of the switch circuit 22 of the present embodiment, the specific structure of the entire high speed sample hold circuit can be the same as in the case of FIG.

Further, an embodiment of the invention described in claim 4 will be described with reference to FIG. In this embodiment, the switch circuit 16
Instead, a switch circuit 23 formed as a bridge circuit by combining a plurality of transistors, diodes and resistors is provided. Explaining in comparison with the switch circuit 20 of the embodiment shown in FIG. 4, resistors R ₂₃ and R ₂₄ are respectively connected to the emitters of the output side transistors Q ₂ and Q ₅ as in the above embodiment. ing. Therefore, in this embodiment, the diodes D _{9 to} D ₁₂ and the resistor R ₃₃ ,
R ₃₄ and each of the transistors _{Q 1, Q 2, Q 4} , a bridge circuit between the base and emitter of Q ₅ is formed.

In such a structure, the sampling operation and the holding operation of this embodiment are similar to those of the switch circuit 20 described with reference to FIG. However, in the case of the present embodiment, the transistor Q
The bias currents of ₂ and Q ₅ can be changed by the resistors R ₂₃ and R _{24 with} respect to the output current of the switch drive circuit 18.

Therefore, in the case of this embodiment, in addition to the effect of the embodiment shown in FIG. 4, the output side transistor Q ₂ ,
The degree of freedom in setting the bias current of Q ₅ can be increased by the resistors R ₂₃ and R ₂₄ .

Also in the case of the switch circuit 22 of the present embodiment, the specific structure of the entire high speed sample hold circuit can be the same as that of the case of FIG.

Further, a first embodiment of the invention according to claim 5 will be described with reference to FIG. In the present embodiment, in addition to the configuration of the switch circuit 16, a switch in which a resistor R ₂₅ is added as an output current limiting element to the output section (between the emitters of the transistors Q ₂ and Q ₅ on the output side and the hold capacitor 13) is provided. A circuit 24 is provided.

According to this embodiment, the charging / discharging current to the hold capacitor 13 in the sample operation state is (voltage difference between input and output of the switch circuit 24) / (resistance R ₂₅
Resistance value) is limited to the following. Therefore, the switch circuit 2
It is possible to prevent the circuit element such as the transistor constituting 4 from being destroyed or deteriorated.

Also, in the case of the switch circuit 24 configuration of this embodiment, the specific configuration of the entire high speed sample hold circuit can be configured in the same manner as in the case of FIG.

A second embodiment of the invention described in claim 5 will be described with reference to FIG. In this embodiment, in addition to the configuration of the switch circuit 22 shown in FIG. 6, the output side of the transistor Q _2, Q transistor Q ₂₃ of NPN type the collector-base connected between the base and emitter of the _5, PNP type The switch circuit 25 is provided by adding the respective transistors Q ₂₄ as output current limiting elements. Emitters of the transistors Q _23, Q ₂₄ is connected to the connection between the resistors R _23, R _24.

In such a configuration, the sample operation,
The hold operation is performed according to the case described in FIG.

Here, the limitation of charging / discharging the hold capacitor 13 during the sampling operation is performed as follows.
First, when a current is made to flow from the switch circuit 25 to the hold capacitor 13, this current is supplied from the emitter of the PNP type transistor Q ₂ . As the emitter current of the transistor Q ₂ increases, its base current also increases, the voltage across the resistor R ₂₃ increases, and the NPN
The base-emitter voltage in the form of transistor Q ₂₃ is also increased. Further, when the current is increased to flush out the hold capacitor 13, the transistor Q ₂₃ of NPN type reaches the turned on, the collector of the transistor Q ₂₃ is connected to the base of the transistor Q _2, the transistor Q ₂ The increase of the base current is suppressed, and as a result, the increase of the emitter current of the transistor Q ₂ is suppressed. On the other hand, when a current is drawn from the hold capacitor 13 to the switch circuit 25, the above-mentioned transistor Q ₅ and Q ₂₄ and the resistor R ₂₄ are connected to the transistor Q ₅ .
The same operation is performed in the state where the polarities of the current and the voltage are opposite to those in the case of ₂ , Q ₂₃ and the resistor R ₂₃ side, and the transistor Q ₅
The increase in the emitter current of is suppressed. Therefore, it is possible to prevent the destruction and deterioration of the circuit elements such as the transistors forming the switch circuit 24. The current value that limits can be varied by changing the resistance value of the resistor R _23, R _24.

Also, in the case of the switch circuit 25 structure of this embodiment, the specific structure of the entire high-speed sample hold circuit can be the same as that of FIG.

Further, an embodiment in which an output current limiting element is added to the switch circuit 16 shown in FIG. 1 in FIG. 8 and an output current limiting element is added to the switch circuit 22 shown in FIG. However, the present invention can be similarly applied to the switch circuits 20, 21, 23 and the like shown in FIGS. 4, 5 and 7.

Next, an embodiment of the invention described in claim 6 will be described with reference to FIGS. In this embodiment, for example, instead of the switch drive circuit 18 shown in FIGS. 1 and 2, a switch drive circuit 26 in which a switching current control element is added to the configuration of the switch drive circuit 18 is provided. This switching time current control element is for controlling the current so that the output current of the switch drive circuit 26 at the time of switching between the sampling operation and the holding operation becomes larger than that in the steady state in which the sampling operation state or the hold operation state is performed. is there. In the case of this embodiment, the switching current control element is P
An NPN transistor Q ₂₅ in parallel with the NP transistor Q ₁₆ and an NPN transistor in parallel with the NPN transistor Q _22.
Shape of the transistor Q _26, the transistors Q _16, Q ₂₅ resistor R ₂₅ connected between the collectors of the transistors Q _22, Q ₂₆
, A resistor R ₂₆ connected between the collectors of the same, resistors R _{27 to} R ₃₀ connected to the emitters of the transistors Q ₁₁ , Q ₁₂ , Q ₁₇ , and Q ₁₈ forming a differential pair, and a capacitor C ₁ to.
It is an RC series circuit by C ₄ . The emitters of the added transistors Q ₂₅ and Q ₂₆ have resistors R ₃₁ and
R ₃₂ is connected. Therefore, when viewed from the differential pair side, the resistor R ₂₅ is interposed between the emitter couplings of the differential pair of the transistors Q ₁₁ and Q ₁₂ , and the resistor R ₂₅ is interposed between the emitter couplings of the differential pair of the transistors Q ₁₇ and Q _{18. 26} is interposed so that the bias currents of the transistors forming the differential pair are supplied from separate constant current circuits.

In such a configuration, the operation in the steady state during the sample operation and the hold operation is the same as that described with reference to FIG. 2, and the current flow in the vicinity of the differential pair shows that during the sample operation. It becomes like the solid arrow in FIG. 11A, and becomes like the solid arrow in FIG. 11B during the hold operation.

On the other hand, the current state when the mode changes from the hold operation state to the sample operation state is as follows. Control terminal 17a for the mode change, at the same time when the voltage of 17b changes, the transistors Q _11, Q _12, Q
_Since the emitter voltage of ₁₇ and Q ₁₈ also changes, capacitor C
Charging / discharging of _{1 to} C ₄ is performed. Of these, the capacitor C ₂
The current flowing through becomes the sink current of the transistor Q ₁₂ ,
The current flowing through the capacitor C ₃ becomes the source current of the transistor Q ₁₇ , and therefore becomes the pulse current. These currents are as shown by the broken line arrows in FIG. 11A, and are superposed on the steady-state currents shown by the solid line.

Conversely, the current state when the mode changes from the sample operating state to the hold operating state is as follows. Because of this mode change, the control terminals 17a, 1
At the same time that the voltage of 7b changes, the transistors Q ₁₁ and Q
_Since the emitter voltages of ₁₂ , Q ₁₇ , and Q ₁₈ also change, the capacitors C _{1 to} C ₄ are charged and discharged. Of these, the current flowing through the capacitor C ₁ becomes the sink current of the transistor Q ₁₁ , and the current flowing through the capacitor C ₄ is the transistor Q _18.
Since it becomes the source current of, it becomes a pulse current. These currents are as shown by the broken line arrows in FIG. 11B, and are superimposed on the steady-state currents shown by the solid line.

As a result, the mode switching output current output from the switch drive circuit 26 to the switch circuit 16 becomes larger at the time of switching than in the steady state, and the switching operation is performed at high speed.

Although the switch drive circuit 26 is applied to the switch circuit 16 shown in FIGS. 1 and 2 in FIG. 10, the switch circuit 16 is not limited to the switch circuit 16 and the switch circuit 20 described above is used. The same applies to the case of using ~ 25. Thereby, each synergistic effect is obtained.

Further, an embodiment of the invention described in claim 7 will be described with reference to FIG. In this embodiment, for example, instead of the output buffer 15 shown in FIG.
The output buffer 27 in which the transistor Q ₂₇ and the resistor R ₂₇ are added to the configuration of 5 is provided, and the feedback circuit 2 is provided by the feedback resistor R _F2 whose one end is connected to the emitter side of the transistor Q _27.
8 is formed. The transistor Q ₂₇ is of NPN type and is provided between the transistors Q ₉ and Q ₁₀ . That is, in the example shown in FIG. 2, the output of the output buffer 15 (= output terminal 14) is switched to the switch circuit 16 by the feedback resistor R _F2.
Switch circuit 16 in the hold operation state by feeding back to the side
However, in the present embodiment, the emitter voltage of the transistor Q ₂₇ is fed back as another output different from the output to the output terminal 14.

Therefore, in the output buffer 27 of this embodiment, the noise at the time of switching between the sample operation and the hold operation, which is transmitted from the switch circuit 16 to the emitter of the transistor Q ₂₇ through the feedback resistor R _F2 , is generated by the transistor Q _27.
Since it is attenuated between the base and emitter of the feedback resistor R _F2
As compared with the case where the is directly connected to the output terminal 14, the noise at the time of mode switching at the output terminal 14 is reduced.

Although an example in which the output buffer 27 and the feedback circuit 28 are applied to the switch circuit 16 shown in FIGS. 1 and 2 has been described with reference to FIG. 12, the present invention is not limited to such a switch circuit 16 and has been described above. The same can be applied to those using the switch circuits 20 to 25. Thereby, each synergistic effect is obtained. For example, an example applied to the one using the switch circuit 22 is as shown in FIG. 13, which has the output current limiting function by the switch circuit 22 and the noise reducing function at the output of the configuration of this embodiment at the same time. Becomes

An embodiment of the invention described in claim 8 will be described with reference to FIG. In the present embodiment, for example, instead of the output buffer 15 shown in FIG.
An output buffer 30 to which the droop reduction circuit 29 is added is provided. This droop reduction circuit 29 transistors Q ₂₈ of PNP type which detects a base current of the transistor Q _9, a transistor Q ₂₉ of NPN type, which is connected to the base and the hold capacitor 13 and to form a current mirror circuit of the transistors Q ₂₈ , Q ₃₀ and. In this embodiment, the transistors Q ₉ and Q ₂₈ have the same or similar characteristics, and the transistors Q ₂₉ and Q ₃₀ have the same or similar characteristics.

In such a structure, the droop in the high speed sample hold circuit mainly occurs when the base current of the transistor Q ₉ in the output buffer 30 flows into the hold capacitor 13. Here, in the case of the present embodiment, the base current of the transistor Q ₉ is detected by the transistor Q ₂₈ so that it flows into the collector of the transistor Q ₂₉ through the current mirror circuit of the transistors Q ₂₉ and Q _30. The base current of the transistor Q ₉ flowing into 13 can be suppressed as small as possible, and droop can be reduced.

In FIG. 14, an example in which the output buffer 30 having the droop reduction circuit 29 is applied to the switch circuit 16 shown in FIGS. 1 and 2 has been described, but the present invention is not limited to such a switch circuit 16. Switch circuit 2 described above
The same applies to those using 0 to 25. Thereby, each synergistic effect is obtained.

An embodiment of the invention described in claim 9 will be described with reference to FIG. In this embodiment, for example, a plurality of, for example, two sets of input terminals 11A, 1 having the configuration shown in FIG.
1B, input buffers 12A and 12B, switch circuit 16
A and 16B, switch drive circuits 18A and 18B, feedback resistors R _F2A and R _F2B are provided, and a hold capacitor 1 is provided.
3, the output terminal 14 and the output buffer 15 are commonly used.

In such a configuration, the switch circuit 1
When the 6A side is in the sample operation state and the switch circuit 16B side is in the hold operation state, the voltage of the input terminal 11A is transmitted to the output terminal 14. Conversely, when the switch circuit 16A side is in the hold operation state and the switch circuit 16B side is in the sample operation state, the voltage of the input terminal 11A is the output terminal 14
Be transmitted to. Further, when both the switch circuits 16A and 16B are brought into the hold operation state, the hold capacitor 1
The voltage held at 3 is transmitted to the output terminal 14.
It should be noted that the switch circuits 16A and 16B are both prohibited from being in the sample operation state.

Therefore, according to the present embodiment, the voltage to be sampled and held can be selected from the voltages of the input terminals 11A and 11B, and the function of switching between two input signals can be provided.

Although the configuration example in which a plurality of switch circuits 16 shown in FIG. 1 are provided has been described with reference to FIG. 15, the present invention is not limited to such a switch circuit 16 and the like, and the switch circuit 2 described above is used.
The same applies to those using 0 to 25 and the like. Thereby, each synergistic effect is obtained.

[0081]

According to the sample and hold circuit of the first aspect of the invention, the output signal from the photoelectric conversion element such as a CCD that outputs an electric signal according to the amount of input light in time series is sampled and its peak value is determined. In a sample-hold circuit provided with a hold capacitor for holding in the preceding stage of an output buffer, a switch circuit formed by a bridge circuit formed by combining a plurality of transistors to switch between a sample operation and a hold operation based on a mode switching output current of a switch drive circuit is provided. Since it is provided in front of the hold capacitor, the large amplitude response of the switch circuit can be speeded up without increasing the power consumption as in the case of the diode bridge structure.

Further, according to the sample hold circuit of the second aspect of the invention, since the switch circuit for switching between the sample operation and the hold operation is formed by the bridge circuit formed by combining a plurality of transistors and diodes, the diode bridge configuration is realized. It is possible to speed up the large amplitude response of the switch circuit without increasing the power consumption as in the case.

Further, according to the sample and hold circuit of the invention described in claim 3, since the switch circuit for switching between the sampling operation and the holding operation is formed by the bridge circuit formed by combining a plurality of transistors and resistors,
The large-amplitude response of the switch circuit can be speeded up without increasing the power consumption as in the case of the diode bridge configuration. In addition, since the resistor is used, the bias current of the output transistor in the switch circuit can be set freely. The degree can be increased.

According to the sample and hold circuit of the fourth aspect of the present invention, since the switch circuit for switching between the sample operation and the hold operation is formed by the bridge circuit formed by combining a plurality of transistors, diodes and resistors, the diode bridge configuration is realized. The large amplitude response of the switch circuit can be speeded up without increasing the power consumption as in the case, and in addition, since the resistance is used, the degree of freedom in setting the bias current of the output transistor in the switch circuit is increased. be able to.

According to the sample and hold circuit of the invention described in claim 5, in addition to the configuration of the sample and hold circuit of the invention described in claim 1, 2, 3 or 4, an output current limiting element is provided at the output part of the switch circuit. Since the switch circuit is provided so as to limit the output current of the switch circuit, it is possible to prevent breakage or deterioration of the elements forming the switch circuit.

According to the sample and hold circuit of the invention described in claim 6, in addition to the structure of the sample and hold circuit of the invention described in claim 1, 2, 3, 4 or 5, the mode for switching the mode in the switch drive circuit Since the switching current control element that makes the mode switching output current larger than that in the steady state is provided, the switching speed between the sample operation and the hold operation can be further increased.

According to the sample and hold circuit of the invention described in claim 7, in addition to the structure of the sample and hold circuit of the invention described in claim 1, 2, 3, 4, 5 or 6, Since the feedback circuit for generating the voltage defining the potential by feeding back the output voltage different from the output of the output buffer itself is provided, it is possible to reduce the noise at the time of mode switching which is transmitted to the output through the feedback circuit.

According to the sample hold circuit of the invention described in claim 8, in addition to the structure of the sample hold circuit of the invention described in claim 1, 2, 3, 4, 5, 6 or 7, the sample hold circuit holds in the output buffer. Since the droop reduction circuit for reducing the droop during the operation is provided, the droop during the hold operation can be reduced.

According to the sample and hold circuit of the invention described in claim 9, claim 1, 2, 3, 4, 5, 6, 7 or 8
With regard to the configuration of the sample hold circuit of the invention described above, since a plurality of switch circuits and switch drive circuits that share the circuit elements after the hold capacitor are provided, it is possible to have a plurality of signal switching functions.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the invention described in claim 1.

FIG. 2 is a circuit diagram showing a more specific configuration example.

FIG. 3 is a circuit diagram for explaining current flows near a differential pair during a sample operation and a hold operation.

FIG. 4 is a circuit diagram showing a first embodiment of the invention according to claim 2;

FIG. 5 is a circuit diagram showing a second embodiment of the invention according to claim 2;

FIG. 6 is a circuit diagram showing an embodiment of the invention according to claim 3;

FIG. 7 is a circuit diagram showing an embodiment of the invention described in claim 4.

FIG. 8 is a circuit diagram showing a first embodiment of the invention according to claim 5;

FIG. 9 is a circuit diagram showing a second embodiment of the invention according to claim 5;

FIG. 10 is a circuit diagram showing an embodiment of the invention described in claim 6;

FIG. 11 is a circuit diagram for explaining a current flow near a differential pair during a sample operation and a hold operation.

FIG. 12 is a circuit diagram showing an embodiment of the invention according to claim 7;

FIG. 13 is a circuit diagram showing a modification thereof.

FIG. 14 is a circuit diagram showing an embodiment of the invention according to claim 8;

FIG. 15 is a circuit diagram showing an embodiment of the invention set forth in claim 9;

FIG. 16 is a circuit diagram showing a conventional example.

[Explanation of symbols]

13 hold capacitor 15 output buffer 16 switch circuit 18 switch drive circuit 20 to 25 switch circuit 26 switch drive circuit 27 output buffer 28 feedback circuit 29 droop reduction circuit 30 output buffer Q _{1 to} Q ₆ transistor D _{9 to} D ₁₄ diode R ₂₃ , R ₂₄ resistance R ₂₅ output current limiting element Q ₂₃ , Q ₂₄ output current limiting element

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/335 Z

Claims (9)

[Claims] 1. A sample-and-hold device provided with a hold capacitor for sampling an output signal from a photoelectric conversion element such as a CCD, which outputs an electric signal corresponding to the amount of input light in time series, and holding a peak value of the output signal, in the preceding stage of an output buffer. In the circuit, a switch circuit that is formed by a bridge circuit formed by combining a plurality of transistors and that switches between a sample operation and a hold operation based on a mode switching output current of a switch drive circuit is connected to the preceding stage of the hold capacitor. Sample hold circuit. 2. A sample hold provided with a hold capacitor for sampling an output signal from a photoelectric conversion element such as a CCD that outputs an electric signal according to the amount of input light in time series and holding a peak value thereof in a front stage of an output buffer. In the circuit, a switch circuit which is formed by a bridge circuit formed by combining a plurality of transistors and diodes and switches between sample operation and hold operation based on the mode switching output current of the switch drive circuit is provided in front of the hold capacitor. A sample and hold circuit characterized in that 3. A sample-hold provided with a hold capacitor for sampling an output signal from a photoelectric conversion element such as a CCD, which outputs an electric signal corresponding to the amount of input light in time series, and holding a peak value of the output signal, in the preceding stage of the output buffer. In the circuit, a switch circuit formed by a bridge circuit composed of a combination of a plurality of transistors and resistors and switching between a sample operation and a hold operation based on a mode switching output current of a switch drive circuit is provided in front of the hold capacitor. A sample and hold circuit characterized in that 4. A sample-hold provided in front of an output buffer with a hold capacitor for sampling an output signal from a photoelectric conversion element such as a CCD that outputs an electric signal according to the amount of input light in time series and holding the peak value thereof. In the circuit, a switch circuit, which is formed by a bridge circuit formed by combining a plurality of transistors, diodes and resistors, and switches between sample operation and hold operation based on the mode switching output current of the switch drive circuit is connected to the preceding stage of the hold capacitor. A sample hold circuit, which is provided. 5. The sample-hold circuit according to claim 1, wherein an output current limiting element is provided at an output portion of the switch circuit. 6. A switching current control element for increasing a mode switching output current at the time of mode switching as compared with a steady state is provided in the switch drive circuit.
The sample hold circuit according to 3, 4, or 5. 7. A feedback circuit for generating a voltage for defining the potential of the switch circuit during the hold operation by feeding back an output voltage different from the output of the output buffer itself. , 4, 5 or 6 sample and hold circuit. 8. The sample-hold circuit according to claim 1, wherein a droop reduction circuit for reducing droop during a hold operation is provided in the output buffer. 9. A plurality of switch circuits and a switch drive circuit which share the circuit elements after the hold capacitor are provided.
Alternatively, the sample hold circuit according to item 8.