JPH07296586A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To shorten an access time by controlling a delay circuit in a timing signal generation circuit and shortening the delay time by a fixed period when an access signal is changed to the state releasing a stand-by state. CONSTITUTION:A chip enable signal CEp is inputted through a CE input buffer circuit 1, and is outputted as an inner chip enable signal CEi. The CE delay circuit 5 delays the change of the CEi to an active state to output delay chip enable signals CEid-CEid. The timing generation circuit 4 controls so that the delay time of the delay circuit 4b becomes the shortest when the CEid is an inactive state by correction circuits 4g, 4h. On the other hand, when the CEid is the active state, the circuit 4 controls in the direction suppressing the fluctuation in the delay time of the circuit 4b due to the fluctuation such as use environment and a manufacture process condition, etc. Thus, the timing of sense operation start is controlled by the pulse width of the output pulse phi2 of the circuit 4, and the needless prolongation of the access time is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a standby function for power saving, and more particularly to a semiconductor memory device capable of shortening an access time when an access is made by canceling the standby state. .

[0002]

2. Description of the Related Art Conventionally, a standby function of a semiconductor memory device is a function of reducing a power consumption by stopping a part of an internal circuit or shifting to a power saving operation in a standby state. However, when this semiconductor memory device is in the standby state, it is necessary to change the access signal from the outside to release the standby state before performing the access. Such a standby function can be used in DRAM [D
dynamic Random Access Memory] and NVDRAM [Non-Vol
If it is installed in the atile Random Access Memory], the power consumption can be reduced by lengthening the refresh cycle of the DRAM or shifting to the non-volatile mode to make the refresh operation unnecessary. Also,
Even in the case of SRAM [Static RAM] or MROM [mask ROM], power consumption can be reduced by stopping the operation of unnecessary internal circuits in the standby state. Here, a semiconductor memory device such as the SRAM will be mainly described.

FIG. 9 shows a conventional structure of a general semiconductor memory device having the standby function. This semiconductor memory device enters a standby state when a chip enable signal CEp input from an external control bus or the like is inactive, and the standby state is released when the chip enable signal CEp becomes active.

The chip enable signal CEp is input via the CE input buffer circuit 1 and sent to the address input buffer circuit 2 and the signal change detection circuit 3 as an internal chip enable signal CEi. The address input buffer circuit 2 operates only when the chip enable signal CEi is active, inputs the address signal Ap sent from an external address bus or the like, and outputs the address signal Ap. And internal address signals Ai1 and Ai2 divided into two on the lower bit side are sent to the X decoder circuit 6 and the Y decoder circuit 7, respectively.

The X decoder circuit 6 and the Y decoder circuit 7 are
Decode address signals Ai1 and Ai2 respectively to select X
A circuit for performing i, Yi and reading data from a selected memory cell on the memory cell array 8. The read data signal Mi read from this memory cell is amplified by the sense amplifier circuit 9 via the Y decoder circuit 7 and sent to the output buffer circuit 10 as the definite data signal SAi. The output buffer circuit 10 inputs an output enable signal OEp sent from an external control bus or the like as an internal output enable signal OEi via an OE input buffer circuit 11. Then, only when the output enable signal OEi is active, the definite data signal SAi is output as the data signal DOUT to an external data bus or the like, whereby data is read from the semiconductor memory device.

The address signals Ai1 and Ai2 output from the address input buffer circuit 2 are signal change detection circuits 3
Also sent to. The signal change detection circuit 3 is a circuit that detects changes in the chip enable signal CEi and the address signals Ai1 and Ai2 and outputs a pulse signal φ1 having a predetermined pulse width.

That is, the signal change detection circuit 3 shown in FIG.
As shown by 0, the chip enable signal CEi and the address signals Ai1 and Ai2 are directly sent to one input of the EXOR circuit 3a, and also to the other input of the same EXOR circuit 3a via the pulse width delay circuit 3b. It will be sent. Since the EXOR circuit 3a is an exclusive OR circuit that outputs a high level signal only when the two inputs are different, when the chip enable signal CEi changes, for example, the EXOR circuit 3a is delayed for a predetermined time by the pulse width delay circuit 3b. Outputs a high level signal. The outputs of the respective EXOR circuits 3a are combined via one OR circuit 3c and output as a pulse signal φ1, so that the chip enable signal CEi and the address signal Ai1,
When any one of Ai2 changes, this pulse signal φ1 becomes high level (active) for a predetermined pulse width.
Becomes When the address signals Ai1 and Ai2 change within a predetermined time after the chip enable signal CEi changes, the pulse width of the pulse signal φ1 is extended by the time difference between these signal changes. In FIG. 10, the address signals Ai1 and Ai2 are shown as 1-bit signals, but in reality, these are signals of a plurality of bits, and the EXOR circuit 3a and the pulse width delay circuit 3b are provided for each bit. Is provided.

The pulse signal φ1 output from the signal change detection circuit 3 is sent to the timing signal generation circuit 4 as shown in FIG. The timing signal generation circuit 4 is a circuit that delays the falling timing of the pulse signal φ1 from the high level to the low level to generate the pulse signal φ2 having a longer pulse width. That is, in this timing signal generation circuit 4, as shown in FIG. 11, the pulse signal φ1 is directly sent to one input of the OR circuit 4a, and at the same time, the other input of the same OR circuit 4a is also input via the delay circuit 4b. It will be sent.

The delay circuit 4b, as shown in FIG.
This is a circuit in which two modified inverter circuits 4c to 4f are connected in series. The modified inverter circuit 4c of the first stage is composed of P-channel and N-channel MOS transistors PI and NI, and is C
A MOS inverter circuit is constructed, and a P-channel delay MOS transistor PR whose gate is connected to the ground power supply GND is inserted between the source of the MOS transistor PI and the power supply VCC. Also, delay MOS
The transistor PR has its driving capability set lower than that of the MOS transistors PI and NI by adjusting the gate length and the like. Therefore, the modified inverter circuit 4c is
When the pulse signal φ1 rises, the MOS transistor NI is turned on and the output falls at a high speed. However, when the pulse signal φ1 falls, even if the MOS transistor PI is turned on, the drive capability of the delay MOS transistor PR is limited. The output rises with a delay.

The modified inverter circuit 4d in the second stage is a CM
MOS transistor NI forming the OS inverter circuit
N-channel delay MOS transistor NR whose gate is connected to the power supply VCC between the source of
The delay MOS transistor NR is also set to have a low driving capability. Therefore, in the case of this modified inverter circuit 4d, the output falls with a delay when the input signal rises. The modified inverter circuit 4e at the third stage has the same configuration as the first stage, and the modified inverter circuit 4f at the fourth stage has the same configuration as the second stage.
As a result, the output pulse signal .phi.1d of the delay circuit 4b becomes a signal having a wide pulse width in which the rising timing of the pulse signal .phi.1 is hardly delayed and only the falling timing is greatly delayed.

As shown in FIG. 11, the pulse signal φ1d output from the delay circuit 4b is input to the OR circuit 4a together with the pulse signal φ1 and the output of the OR circuit 4a becomes the pulse signal φ2. Therefore, this pulse signal φ2 rises along with the rise of the pulse signal φ1,
After the pulse signal φ1 falls, it falls after the delay time in the delay circuit 4b elapses.

The pulse signal φ2 output from the timing signal generating circuit 4 is sent to the sense amplifier circuit 9 as shown in FIG. In the sense amplifier circuit 9, the sense operation is started after the pulse signal φ2 falls, and the read data signal Mi read from the memory cell array 8 is started.
Is amplified and output as a finalized data signal SAi. Here, the sense operation of the sense amplifier circuit 9 is performed by the minute read data signal M read from the memory cell.
Since i is differentially amplified to be the definite data signal SAi of the logical level on the same signal line, if the sensing operation is performed before the read data signal Mi is read, the read data signal Mi is destroyed and correct definite data is obtained. The signal SAi cannot be obtained. Therefore, the timing signal generation circuit 4
The pulse signal .phi.2 output by the X decoder circuit 6 and the Y decoder circuit 7 decodes the address signals Ai1 and Ai2 and outputs the read data signal M from the memory cells of the memory cell array 8.
It is necessary to have a pulse width equal to or longer than the time required to read i securely.

The operation of read access (hereinafter referred to as "CE access") when the semiconductor memory device having the above configuration is in the standby state will be described with reference to the time chart of FIG.

Since the external chip enable signal CEp is at the low level in the standby state, it is necessary to release the standby state by first changing the chip enable signal CEp to the high level (active) in CE access. When the chip enable signal CEp goes high, the chip enable signal CEi output from the CE input buffer circuit 1 goes high with a delay of time t1. Then, the address input buffer circuit 2 for inputting the address signal Ap operates to change the outputs of the address signals Ai1 and Ai2 with a delay of time tA.

When the address signals Ai1 and Ai2 change, X
The decoder circuit 6 and the Y decoder circuit 7 decode this and perform selection Xi, Yi with a delay of time t6. Then, after a lapse of a predetermined time, the read data signal Mi is read from the memory cells of the memory cell array 8, the sense amplifier circuit 9 starts the sensing operation, and becomes the definite data signal SAi at time t3, and is output after further time t4. The data signal DOUT is output from the buffer circuit 10.

When the chip enable signal CEi changes to high level, the pulse signal φ1 output from the signal change detection circuit 3 rises to high level. Then, after the passage of time tA, the address signals Ai1 and Ai2 are
Since the pulse signal .phi.1 also changes, the pulse signal .phi.1 falls at a timing delayed by the delay time t5 of the pulse width delay circuit 3b after the address signals Ai1 and Ai2 have changed. Therefore, the pulse width tW1 of the pulse signal φ1 is the time obtained by adding the time tA to the delay time t5. The pulse signal φ2 output from the timing signal generating circuit 4 is the OR signal
Due to the delay in the circuit 4a or the like, the pulse signal .phi.1 rises with a delay of time t2, the delay circuit 4b delays the read data signal Mi, and then the pulse width tW2 falls.

Therefore, the access time at the CE access is the delay time t1 in the CE input buffer circuit 1 after the chip enable signal CEp changes to the high level.
Then, the delay time t2 in the timing signal generating circuit 4, the pulse width tW2 of the pulse signal φ2, the delay time t3 in the sense amplifier circuit 9 and the delay time t4 in the output buffer circuit 10 are summed up.

The operation of read access (hereinafter referred to as "address access") when the semiconductor memory device is already released from the standby state will be described with reference to the time chart of FIG.

Here, the chip enable signal CEp is already at the high level and does not change. When the external address signal Ap changes in this state, the address input buffer circuit 2 changes the output of the internal address signals Ai1 and Ai2 with a delay of approximately the same time tA as described above.

When the address signals Ai1 and Ai2 change, the X decoder circuit 6 and the Y decoder 6 are used as in the CE access.
The decoder circuit 7 performs the selection Xi, Yi with a delay of time t6, the read data signal Mi is amplified to the definite data signal SAi after time t3 after the sense amplifier circuit 9 starts the sensing operation, and is output after the time t4 elapses. The data signal DOUT is output from the buffer circuit 10.

Further, when the address signals Ai1 and Ai2 change, a pulse signal φ1 output from the signal change detection circuit 3
Rises to a high level and falls after the delay time t5 of the pulse width delay circuit 3b has elapsed. For this reason,
The pulse width tW1 of the pulse signal φ1 becomes a time corresponding to the delay time t5. The pulse signal φ2 output from the timing signal generation circuit 4 also rises with a delay of time t2 from the pulse signal φ1 and falls with the pulse width tW2 delayed by the delay circuit 4b.

Therefore, the access time at the time of this address access is the delay time tA in the address input buffer circuit 2 after the change of the address signal Ap, the delay time t2 in the timing signal generating circuit 4, and the pulse signal φ2. Pulse width tW2, delay time t3 in the sense amplifier circuit 9,
It is the sum of the delay times t4 in the output buffer circuit 10.

[0023]

However, in the above-mentioned conventional semiconductor memory device, the access time during CE access becomes longer than the access time during address access.
There is a problem that this becomes a factor that hinders the speeding up of the semiconductor memory device.

One of the causes for increasing the access time at the time of CE access is due to the delay of signal input in the CE input buffer circuit 1. That is, at the time of address access, time tA has passed since the external address signal Ap changed.
While the internal address signals Ai1 and Ai2 change after the elapse of time, at the time of CE access, the internal chip enable signal CEi becomes high after the time t1 has elapsed after the external chip enable signal CEp first changes to the high level. It changes to the level, and then the internal address signals Ai1 and Ai2 change after the time tA. Therefore, during CE access, an extra delay time t1 is required in the CE input buffer circuit 1 before the internal address signals Ai1 and Ai2 change, which lengthens the access time. The time t1 tends to be longer for a semiconductor memory device having a larger storage capacity, and is about 10 ns.
However, this time t1 is a time required to release the standby state, and is unavoidable for a semiconductor memory device having a standby function.

Another cause of the longer access time during CE access is that the pulse width tW2 of the pulse signal φ2 output from the timing signal generation circuit 4 becomes longer than necessary. That is, as shown in FIG. 14, the pulse width tW1 of the pulse signal φ1 at the time of address access coincides with the delay time t5 in the pulse width delay circuit 3b of the signal change detection circuit 3, and the pulse signal φ2 has this pulse. The falling edge of the signal φ1 is delayed by the delay circuit 4b of the timing signal generating circuit 4 to obtain the pulse width tW2. On the other hand, as shown in FIG. 13, the pulse width tW1 of the pulse signal φ1 during CE access is obtained by adding the delay time tA in the address input buffer circuit 2 to the delay time t5 in the pulse width delay circuit 3b. Therefore, the pulse signal φ2 has a pulse width tW2 by delaying the trailing edge of the pulse signal φ1 by the same delay circuit 4b. Therefore, the pulse width tW2 of the pulse signal φ2 at the time of CE access becomes longer than the pulse width tW2 at the time of address access by the time tA, and the start of the sense operation of the sense amplifier circuit 9 is delayed accordingly. Then, the pulse width tW of the pulse signal φ2 at the time of address access
If 2 is a time sufficient for reading the read data signal Mi, the pulse width tW of the pulse signal φ2 during this CE access
2 delays the sense operation of the sense amplifier circuit 9 more than necessary, and the access time during CE access is unnecessarily long.

The present invention solves the above-mentioned conventional problem, and shortens the delay time of the delay circuit of the timing signal generating circuit to make the access time longer than necessary when the standby state is released to perform the access. It is an object of the present invention to provide a semiconductor memory device that does not have such a problem.

[0027]

A semiconductor memory device of the present invention is a semiconductor device having a function of stopping a part of an internal circuit or shifting to a power saving operation when an access signal indicates a standby state. A storage device,
A signal change detection circuit that generates a pulse signal that is active for a predetermined period when the access signal changes to a state where the standby state is released and when the address signal changes, and active in the pulse signal generated by the signal change detection circuit And a timing signal generating circuit for generating a pulse signal having a wider pulse width in the active period by delaying the timing of changing from inactive to a pulse signal of the pulse signal generated by the timing signal generating circuit. In a semiconductor memory device that controls a data read operation according to a pulse width, a delay circuit in the timing signal generation circuit is controlled when the access signal changes to a state where a standby state is released, and the delay circuit is controlled for a certain period. The delay time control circuit that shortens the delay time of It has been kicked, the objects can be achieved.

Further, preferably, in the timing signal generating circuit in the semiconductor memory device of the present invention, the delay time of the delay circuit is controlled so as to suppress the change of the delay time according to the variation of use environment, manufacturing process condition and the like. In the semiconductor memory device provided with the correction circuit, the delay time control circuit controls the correction circuit when the access signal changes to the state of releasing the standby state, and the delay circuit of the delay circuit The delay time is controlled to be near the shortest time in the control range.

Further, preferably, the delay circuit in the timing signal generating circuit in the semiconductor memory device of the present invention comprises a delay MO between the CMOS inverter circuit and the power supply.
It comprises a circuit in which a plurality of stages of modified inverter circuits interposing an S transistor and in which the delay time is extended as the driving capability of the delay MOS transistor is lowered are connected in series, and the correction circuit applies the access signal to the gate. The output voltage of the output circuit of the detection MOS transistor is applied as a drive voltage to the gate of the delay MOS transistor of the modified inverter circuit, and the drive voltage is in a state in which the access signal indicates a standby state. In some cases, the voltage becomes a voltage for driving the delay MOS transistor near the maximum capacity, and when the access signal is in the state where the standby state is released, this drive capacity depends on the drive capacity of the detection MOS transistor. The higher the voltage, the higher the voltage that suppresses the driving capability of the delay MOS transistor. In the semiconductor memory device as described above, the delay time control circuit delays the timing at which the standby state of the access signal changes to the state of releasing the standby state for a certain period and applies the delayed signal to the gate of the detection MOS transistor. .

[0030]

When the access signal is in the state where the standby state is released, this access signal does not change,
The signal change detection circuit generates a pulse signal that is active for a predetermined period only when the address signal changes due to address access. However, when the access signal indicates the standby state, when the access signal changes to the state to release the standby state by the standby release access and the address signal fetched inside changes after that. Since the pulse signals that are active for the respective predetermined periods are generated, the active period of this pulse signal is extended by the time required from the change of the access signal to the change of the address signal. Further, conventionally, this causes the pulse width of the pulse signal generated by the timing signal generating circuit to be longer than necessary.

According to the first aspect of the present invention, when the access signal changes to the state of releasing the standby state, the delay time control circuit controls the delay circuit in the timing signal generating circuit to delay the delay time of the delay circuit for a fixed period. To shorten. Therefore, at the time of standby release access, the pulse width of the pulse signal generated by the timing signal generation circuit can be shortened by shortening the delay time, and the extension of the pulse signal generated by the signal change detection circuit can be offset to cancel the address access. The pulse width can be almost the same.

As a result, according to the invention of claim 1, the pulse width of the pulse signal generated by the timing signal generating circuit at the time of standby release access can be shortened to about the same as the pulse width at the time of address access. It is possible to prevent the access time from being lengthened by wasting more time than necessary for the data read operation at the time of standby release access.

According to the second aspect of the present invention, there is shown a case where the delay circuit of the timing signal generating circuit is provided with a correction circuit for suppressing a change in delay time according to a change in use environment, manufacturing process conditions and the like. .

In this case, the delay time control circuit controls the correction circuit at the time of standby release access to control the delay time of the delay circuit to be near the shortest time of the control range. Then, for example, if the delay time becomes the shortest in the fluctuation range according to changes in the environment or conditions,
At the time of address access, the correction circuit controls the delay time of the delay circuit so as to increase the delay time, and this delay time is almost the maximum time of the control range. Further, at the time of standby release access, the correction circuit controls the delay time to be the shortest time within the control range. Therefore, the pulse width of the pulse signal generated by the timing signal generation circuit corresponds to the almost longest delay time in the control range during address access, and changes to the shortest delay time in the control range during standby release access. Since it depends on the time obtained by adding the extension amount in the detection circuit, these pulse widths can be made approximately the same.

However, when the delay time becomes the longest in the variation range according to the variation of the use environment or the manufacturing process condition, the correction circuit controls the delay time of the delay circuit to be shortened at the time of address access, Since the correction circuit controls the delay time to be the shortest in the control range even during the standby release access, the delay time is the shortest time in the control range in any case. Therefore, in this case, the pulse width of the pulse signal generated by the timing signal generation circuit is longer in the standby release access than in the address access by the extension of the signal change detection circuit. When the delay time is in the middle of these, the pulse width at the time of standby release access can be made closer to the pulse width at the time of address access as it approaches the shortest variation range.

As a result, also in the invention of claim 2, the same as the invention of claim 1 except that the delay time becomes the longest in the variation range according to the variation of the use environment or the manufacturing process conditions. Since the timing signal generation circuit can shorten the pulse width of the pulse signal generated at the time of standby release access so that it approaches the pulse width at the time of address access, it takes more time than necessary for the data read operation at the time of standby release access. It is possible to prevent the access time from being lengthened by wasting the computer.

According to a third aspect of the present invention, the delay circuit according to the second aspect is provided with a delay MOS transistor, and the correction circuit is provided with a detection MOS transistor.
The case where the driving capability of the OS transistor is changed in a substantially similar manner according to changes in the use environment and manufacturing process conditions so as to cancel each other out is shown. That is, as the driving capability of the delay MOS transistor increases due to changes in the environment and conditions, the driving capability of the detection MOS transistor also increases, so that the correction circuit suppresses the driving capability of the delay MOS transistor. By applying a voltage, the shortening of the delay time of the delay circuit can be canceled as much as possible to suppress the change of the delay time. In addition, this correction circuit outputs only in accordance with the driving capability of such a detection MOS transistor when the access signal is in the state where the standby state is released, and when the access signal indicates the standby state. Is always output so that the delay MOS transistor can exhibit almost the maximum driving capability.

In this case, the delay time control circuit uses the detection M
The access signal applied to the gate of the OS transistor is delayed for a certain period. Then, at the time of address access, since the access signal has already been released from the standby state, the correction circuit operates normally, but at the time of standby release access, the access signal sent to the correction circuit still indicates the standby state. Since the state remains as it is, this correction circuit controls the delay time so as to be almost the shortest time of the control range.

The delay time control circuit need only delay the timing at which the access signal changes to the state for releasing the standby state, and does not need to delay the timing for returning to the state instructing the standby state. .

As a result, also in the case of the invention of claim 3, as in the invention of claim 2, the pulse width of the pulse signal generated by the timing signal generating circuit at the time of the standby release access is made closer to the pulse width at the time of the address access. Therefore, it is possible to prevent the access time from being lengthened by wasting more time than necessary for the data read operation during standby release access.

[0041]

EXAMPLES Examples of the present invention will be described below.

1 to 8 show a first embodiment of the present invention, FIG. 1 is a block diagram showing the configuration of a semiconductor memory device, and FIG. 2 is a circuit diagram showing the configuration of a CE delay circuit. 3 is a block diagram showing the connection relationship between the CE delay circuit and the timing signal generating circuit, FIG. 4 is a time chart showing the operation of the CE delay circuit and the timing signal generating circuit, and FIG. 5 is an operation at the time of CE access in the semiconductor memory device. A time chart, FIG. 6 is a time chart showing the relationship when the delay time of the delay circuit in the timing signal generating circuit changes.
FIG. 7 is a block diagram of a timing signal generation circuit having a correction circuit used in this embodiment, and FIG. 8 is a circuit diagram showing a configuration of a delay circuit and a correction circuit in the timing signal generation circuit used in this embodiment. It should be noted that constituent members having the same functions as those of the conventional example shown in FIGS. 9 and 12 are denoted by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 1, the semiconductor memory device of this embodiment enters a standby state when the external chip enable signal CEp is inactive, and releases the standby state when this chip enable signal CEp becomes active. I will show you about things. However, the access signal for instructing and canceling the standby state is not limited to such a chip enable signal CEp, and may be another signal or a combination of a plurality of other signals.

The structure of this semiconductor memory device is almost the same as that of the conventional example shown in FIG. 9, but the internal structure of the timing signal generating circuit 4 is different, and the CE delay circuit 5 is also provided.
Has been added. The circuits other than these have exactly the same configuration as the conventional example of FIG.

Here, in the delay circuit 4b of the timing signal generating circuit 4 in the conventional example shown in FIG. 11, the delay time greatly changes in accordance with changes in the use environment and manufacturing process conditions, and the maximum delay time is about three times. There may be a time lag.
When the delay time greatly fluctuates in this way, the read data signal Mi stabilizes the pulse width tW2 of the pulse signal φ2 output from the timing signal generating circuit 4 even when the fluctuation time is the shortest. Therefore, the average time of this pulse width tW2, which occupies more than half of the access time, becomes longer than necessary, and the speedup of the semiconductor memory device is hindered. . Therefore, in the timing signal generating circuit 4 shown in FIG. 11, the correction circuits 4g and 4 shown in FIG.
By adding h, the fluctuation of the delay time of the delay circuit 4b is reduced to 1.5.
Conventionally, proposals have been made to reduce the amount by a factor of two.

As shown in FIG. 8, the structure of delay circuit 4b in timing signal generating circuit 4 is substantially the same as that shown in FIG. However, the delay MOS in the modified inverter circuits 4c and 4e in the first and third stages
The output of the correction circuit 4g is connected to the gate of the transistor PR, and the modified inverter circuits 4d, 4 of the second and fourth stages are connected.
The output of the correction circuit 4h is connected to the gate of the delay MOS transistor NR in f. Correction circuit 4g
Is the source of the detection MOS transistor PC is the power supply VCC
And a drain connected to the ground power supply GND via a resistor R1. An output signal PO from this drain is sent to the delay circuit 4b. The gate of the detection MOS transistor PC has a chip enable signal C obtained by inverting the chip enable signal CEi.
The Ei bar is input. The correction circuit 4h is a circuit in which the source of the detection MOS transistor NC is connected to the ground power supply GND and the drain is connected to the power supply VCC through the resistor R2. The output signal NO from the drain is the delay circuit 4b. Sent to. And
The chip enable signal CEi is input to the gate of the detection MOS transistor NC. These detection MOS transistors PC and NC are set so that their driving ability is lowered to some extent, like the delay MOS transistors PR and NR.

In the timing signal generation circuit 4, when the chip enable signal CEi is at low level, the detection MOS transistors PC and NC of the correction circuits 4g and 4h are both inactive, and the output signals PO and NO are output. The potentials of the ground power supply GND and the power supply VCC are respectively obtained. However, when the chip enable signal CEi becomes high level, both the detection MOS transistors PC and NC become active, the potential of the output signal PO tries to approach the power supply VCC, and the potential of the output signal NO tries to approach the ground power supply GND. To do.
The actual potentials of these output signals PO and NO are
Driving capability of detection MOS transistors PC and NC and resistance R
Determined by the values of 1 and R2. That is, the higher the drive capability of the detection MOS transistor PC, the higher the potential of the output signal PO of the correction circuit 4g, and the higher the drive capability of the detection MOS transistor NC, the lower the potential of the output signal NO of the correction circuit 4h. The drive capabilities of the detection MOS transistors PC and NC are the same as the drive capabilities of the delay MOS transistors PR and NR of the modified inverter circuits 4c to 4f in the delay circuit 4b in accordance with changes in the use environment and manufacturing process conditions. The same changes.

Therefore, when the driving capability of the delay MOS transistor PR is going to increase due to changes in environment and conditions, the potential of the output signal PO of the correction circuit 4g applied to the gate rises, This improvement in driving ability is suppressed. Similarly, when the driving capability of the delay MOS transistor NR is about to increase, the potential of the output signal NO of the correction circuit 4h applied to the gate decreases, and the improvement of the driving capability is suppressed. As a result, the delay circuit 4b
Even when there is a change in the usage environment or manufacturing process conditions, the change in delay time can be suppressed to about 1.5 times as described above. The semiconductor memory device according to the present embodiment is shown by adding the correction circuits 4g and 4h to the timing signal generation circuit 4.

As shown in FIG. 1, the CE delay circuit 5 includes:
The internal chip enable signal CEi output from the CE input buffer circuit 1 is input. Then, a delayed chip enable signal CE obtained by delaying the rising timing of the chip enable signal CEi
id and the delayed chip enable signal CE obtained by inverting this id
Output id bar and.

That is, the CE delay circuit 5 is composed of a circuit in which five modified inverter circuits 5a to 5e are connected in series as shown in FIG. The first, third, and fifth modified inverter circuits 5a, 5c, and 5e have the same configuration as the second and fourth modified inverter circuits 4d and 4f in the delay circuit 4b shown in FIG. The second-stage and fourth-stage modified inverter circuits 5b and 5d have the same configuration as the first-stage and third-stage modified inverter circuits 4c and 4e in the same delay circuit 4b. Therefore, in the case of this CE delay circuit 5, unlike the delay circuit 4b, only the rising timing of the input pulse signal is greatly delayed. The chip enable signal CEi is input to the modified inverter circuit 5a at the first stage. The modified inverter circuit 5d of the fourth stage outputs the delayed chip enable signal CEid, and the modified inverter circuit 5e of the fifth stage outputs the delayed chip enable signal CEid bar.

The delayed chip enable signals CEid and CEid bar output from the CE delay circuit 5 are sent to the timing signal generation circuit 4 as shown in FIG. Further, in the timing signal generation circuit 4, as shown in FIG. 3, the delayed chip enable signal CEid bar output from the CE delay circuit 5 is detected by the detection MOS in the correction circuit 4g.
The delayed chip enable signal CEid is applied to the gate of the transistor PC and the gate of the detection MOS transistor NC in the correction circuit 4h.

The operations of the timing signal generating circuit 4 and the CE delay circuit 5 shown in FIG. 3 will be described with reference to the time chart of FIG. When the chip enable signal CEi output from the CE input buffer circuit 1 changes to a high level, the pulse signal φ1 output from the signal change detection circuit 3
Becomes a high level, and accordingly, the pulse signal φ2 output from the timing signal generating circuit 4 also becomes a high level with a wider pulse width, and falls after a lapse of time t7. When the chip enable signal CEi changes to the high level, the delay time t8 of the CE delay circuit 5 increases.
The delayed chip enable signal CEid rises and the delayed chip enable signal CEid bar falls after.
At this time, the delay time t8 of the CE delay circuit 5 is set to be longer than the time t7 from the rise of the chip enable signal CEi to the fall of the pulse signal φ2. When the delayed chip enable signal CEid bar changes to the low level in this way, the output signal PO of the correction circuit 4g, which has been the potential of the ground power supply GND until then, is the correction potential corresponding to the driving capability of the detection MOS transistor PC at that time. Ascend to VPF. Further, when the delayed chip enable signal CEid changes to the high level, the output signal NO of the correction circuit 4h which has been the potential of the power supply VCC until then.
Falls to the correction potential VNF according to the driving capability of the detection MOS transistor NC at that time.

The CE access operation when the semiconductor memory device having the above configuration is in the standby state will be described with reference to the time chart of FIG.

When the external chip enable signal CEp goes high, the chip enable signal CEi output from the CE input buffer circuit 1 goes high with a delay of time t1, and the address signal Ai1 output from the address input buffer circuit 2 is reached. , Ai2 changes with a delay of time tA. When the address signals Ai1 and Ai2 change, the X decoder circuit 6 and the Y decoder circuit 7 perform the selection Xi and Yi with a delay of time t6, and then the read data signal Mi is read from the memory cells of the memory cell array 8. , The sense amplifier circuit 9 starts the sensing operation, and becomes the definite data signal SAi after time t3, and after the time t4, the output buffer circuit 10 outputs the data signal DO.
Output as UT.

The chip enable signal CEi changes to the high level, and after the time tA, the address signals Ai1 and
When Ai2 also changes, the pulse signal φ from the signal change detection circuit 3 becomes high level by the pulse width tW1 of the time obtained by adding the time tA and the delay time t5 of the pulse width delay circuit 3b.
1 is output. The operation up to this point is similar to that of the conventional example shown in FIG.

However, the delay chip enable signals CEid and CEid output from the CE delay circuit 5 remain at the low level and the high level, respectively.
The output signals PO and NO of g and 4h are ground power GN, respectively.
It becomes the potential of D and the power source Vcc. Then, the delay MOS transistors PR and NR in the delay circuit 4b shown in FIG.
Exhibits the maximum driving ability in accordance with the variation of the use environment and manufacturing process conditions at that time, and the delay time of the delay circuit 4b is shortened. Therefore, the pulse signal φ2 output from the timing signal generation circuit 4 rises after a delay of time t2 from the rise of the pulse signal φ1, but the timing of its fall is earlier and the pulse width tW2 is sufficiently shorter than before. Will be things.

The address access operation when the semiconductor memory device has already been released from the standby state is the same as that shown in FIG. However, in this case, since the delayed chip enable signals CEid and CEid output from the CE delay circuit 5 are already in the active state of high level and low level, respectively, the correction circuit 4g in the timing signal generation circuit 4 is , 4h output signals PO and NO are changed to correction potentials VPF and VNF, respectively. Then, the delay MOS transistors PR and NR in the delay circuit 4b shown in FIG. 8 have the correction potential VPF and the correction potential VSS so that the driving ability becomes high in accordance with the fluctuation of the use environment and the manufacturing process condition at that time. This drive capability is suppressed by VNF, and the change in delay time is reduced. Therefore, the variation range of the pulse width tW2 of the pulse signal φ2 output from the timing signal generation circuit 4 is also 1.5.
It fits in about twice. Even if the pulse width tW2 when the variation range is the shortest is set to be the minimum time for which data can be stably read, the waste of access time at the average pulse width tW2 is reduced. Therefore, the speed of the semiconductor memory device can be increased.

The delay time of the delay circuit 4b is shown in FIG.
As shown in, when the shortest time of this variation range is reached according to the variation of the use environment or the manufacturing process condition, the output signals PO and NO of the correction circuits 4g and 4h are changed to change the time t11 to the time t12. Control range (hatching part)
It is assumed that the control becomes possible within the control range, and when it becomes the longest time of the fluctuation range, the control becomes possible within the control range (hatched portion) from time t13 to time t14. When the delay time is the shortest time within the fluctuation range, the correction circuits 4g and 4h control it so as to be the longest time within the control range, so the delay time during address access is time t12. However, in this case, the delay time during CE access is the shortest time t11 within the control range because the output signals PO and NO are at the potentials of the ground power supply GND and the power supply VCC, respectively. However, the pulse signal φ during this CE access
Since the pulse width tW2 of 2 is longer than the time of address access by the time tA shown in FIG. 5, the time obtained by adding the time t11 and the time tA should be set to be about the same as the time t12. Address access and CE
The pulse width tW2 of the pulse signal φ2 during access can be made substantially the same. On the other hand, the delay time in the conventional CE access becomes the same time t12 as in the address access, and the pulse width tW2 of the pulse signal φ2 is extended by the time tA.

When the delay time becomes the longest time within the fluctuation range, the correction circuits 4g and 4h control it so as to become the shortest time within the control range, so that the delay time at the time of address access is It becomes time t13. As a result, the change in delay time is changed from time t12 to time t13.
It can be stored in about 1.5 times. However, in this case, the delay time during CE access is also the same time t13.
Therefore, the pulse width tW2 of the pulse signal φ2 is extended by the time tA as in the conventional case. Therefore, the present embodiment has an effect of reducing the delay time at the CE access only when the delay time is shorter than the longest time within the fluctuation range.

When the delay time of the delay circuit 4b in the timing signal generating circuit 4 is controlled to be shortened at the CE access as described above, the pulse output from the timing signal generating circuit 4 at the CE access and the address access. The pulse width tW2 of the signal φ2 can be made approximately the same length. Therefore, if the pulse width tW2 is set to be the minimum time for which data can be stably read, the access time for CE access can be set to that for address access without impairing the read operation of the read data signal Mi. It is possible to speed up the semiconductor memory device by shortening it to the same extent.

In the above embodiment, the CE delay circuit 5 is used to correct the correction circuits 4g and 4h of the timing signal generation circuit 4.
Although the delay time of the delay circuit 4b is shortened by controlling the delay time, it is possible to directly control the delay circuit 4b at the time of CE access by the delay time control circuit to shorten the delay time.

[0062]

As described above, according to the present invention, the pulse width of the pulse signal generated when the timing signal generating circuit releases the standby state and performs access is shortened to the same level as the pulse width at the time of address access. Therefore, in this case, it is possible to prevent the access time from being lengthened by taking more time than necessary for the data read operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 shows a first embodiment of the present invention, which comprises CE
It is a circuit diagram which shows the structure of a delay circuit.

FIG. 3 shows a first embodiment of the present invention, and CE
FIG. 3 is a block diagram showing a connection relationship between a delay circuit and a timing signal generation circuit.

FIG. 4 shows a first embodiment of the present invention, which comprises CE
6 is a time chart showing the operation of the delay circuit and the timing signal generation circuit.

FIG. 5 shows a first embodiment of the present invention and is a time chart showing an operation at the time of CE access in the semiconductor memory device.

FIG. 6 is a time chart showing the first embodiment of the present invention and showing the relationship when the delay time of the delay circuit in the timing signal generating circuit varies.

FIG. 7 shows a first embodiment of the present invention and is a block diagram of a timing signal generation circuit having a correction circuit used in the present embodiment.

FIG. 8 shows a first embodiment of the present invention and is a circuit diagram showing a configuration of a delay circuit and a correction circuit in the timing signal generation circuit used in the present embodiment.

FIG. 9 is a block diagram showing a conventional example, showing a configuration of a semiconductor memory device.

FIG. 10 is a block diagram showing a configuration of a signal change detection circuit, showing a conventional example.

FIG. 11 is a block diagram showing a configuration of a timing signal generation circuit, showing a conventional example.

FIG. 12 shows a conventional example and is a block diagram showing a configuration of a delay circuit of a timing signal generating circuit.

FIG. 13 shows a conventional example and is a time chart showing an operation at the time of CE access in the semiconductor memory device.

FIG. 14 is a time chart showing an operation at the time of address access in the semiconductor memory device, showing a conventional example.

[Explanation of symbols]

 3 signal change detection circuit 4 timing signal generation circuit 4b delay circuit 4g correction circuit 4h correction circuit 5 CE delay circuit

Claims (3)

[Claims] 1. A semiconductor memory device having a function of stopping a part of an internal circuit or shifting to a power saving operation when the access signal is in a standby state, wherein the access signal is in a standby state. And a signal change detection circuit that generates a pulse signal that is active for a predetermined period when the address signal changes and a change in the pulse signal generated by the signal change detection circuit from active to inactive A timing signal generating circuit for generating a pulse signal having a wider pulse width in an active period by delaying the timing with a delay circuit, and reading data according to the pulse width of the pulse signal generated by the timing signal generating circuit In the semiconductor memory device controlling the operation, the access signal is If the changes in the state of releasing the standby state, the semiconductor memory device by controlling the delay circuit in the timing signal generating circuit, a delay time control circuit to shorten the delay time of the delay circuit by a predetermined period of time is provided. 2. A semiconductor memory in which the timing signal generating circuit is provided with a correction circuit for controlling the delay time of the delay circuit in a direction of suppressing a change in the delay time according to a change in use environment, manufacturing process condition, and the like. In the device, the delay time control circuit controls the correction circuit to change the delay time of the delay circuit for a certain period of time from the shortest time of the control range when the access signal changes to a state of releasing the standby state. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is controlled so that 3. A modification in which the delay circuit in the timing signal generating circuit has a delay MOS transistor interposed between the CMOS inverter circuit and the power supply, and the delay time is extended as the driving capability of the delay MOS transistor is lowered. The correction circuit drives the output voltage of the output circuit of the detection MOS transistor, to which the access signal is applied to the gate, to the gate of the delay MOS transistor of the modified inverter circuit. The voltage is applied as a voltage, and when the drive signal indicates a standby state, the drive voltage becomes a voltage for driving the delay MOS transistor in the vicinity of the maximum capacity. When the state is released, the detection MOS transistor In a semiconductor memory device according to the drive capability of a transistor, the higher the drive capability, the more the voltage for suppressing the drive capability of the delay MOS transistor is set. 3. The semiconductor memory device according to claim 2, wherein the timing of changing to the state of releasing the standby state is delayed for a certain period and applied to the gate of the detection MOS transistor.