JPH07294873A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display device capable of preventing the malfunction of liquid crystal driving logic circuits while using conventional ready-made liquid crystal drivers. CONSTITUTION:In the power source circuits of the liquid crystal display device, 6 potentials V0 to V5 for driving liquid crystal are supplied to drivers 17, 18 of CMOSs with power source wirings 14a to f. Impedance forming elements consisting of chip impedors 15a to f and resistors R6 to R11 are inserted in all of power source wirings 14a to f. Thus, generations of ringing voltages in power source wirings can be suppressed. Further, in an FFC having wirings of control signals such as a timing clock and wirings for supplying voltages from external power sources to an LCD module, a high voltage power source wiring and a current recovering wiring are separated physically from other timing clock wirings and these two power source wirings are allotted to plural wirings in the FCC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type liquid crystal display device, and more particularly to the structure of a power supply circuit for supplying a predetermined voltage to liquid crystal drive electrodes.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, the liquid crystal is driven by a pair of drive electrodes provided so as to sandwich the liquid crystal. Then, a plurality of levels of voltage for driving the liquid crystal are supplied to the drive electrodes via a switch element composed of a CMOS circuit or the like.

The structure of the power supply circuit of the liquid crystal display device will be described below by taking a simple matrix type liquid crystal display device as an example.

In the simple matrix type liquid crystal display device, by supplying a predetermined voltage to the common electrodes provided with the liquid crystal sandwiched between them and the segment electrodes, the liquid crystal located between these electrodes is driven.

FIG. 4 shows a part of the power supply circuit formed in the module 10 of the simple matrix type liquid crystal display device.

In the figure, the high-voltage power supply VEE supplied from the external high-voltage power supply to the module 10 through the wiring is a negative power supply which is lower than the ground voltage VSS by 20 to 30 V and is a power supply VCC.
Is a power supply of 3 to 5 V supplied for the logic circuit. This device is a negative power supply type that uses a power supply VCC and a high-voltage power supply VEE to generate a liquid crystal drive voltage for driving the liquid crystal 45. In addition to this, there is also a positive power supply type that creates a liquid crystal drive voltage by using a high voltage positive power supply 30 to 40 V higher than the ground voltage VSS and the ground voltage VSS.
The basic configuration of the power supply circuit is the same as that shown in FIG.

Due to recent demands for small size, light weight and high density mounting, the high voltage power supply wiring for supplying the liquid crystal drive power supply to the liquid crystal drive electrodes (common electrodes, segment electrodes) is paired with this high voltage power supply wiring. Wiring cable (FFC: printed on a flexible substrate as shown in FIG. 7 together with the current recovery wiring and other timing clock wiring that form
Flexible Flat Cable) is connected to the control system and external power supply by an interface cable called.

In the liquid crystal display device of FIG. 4, by dividing the two voltages of the high voltage power source VEE and the power source VCC supplied from the external power source by the voltage dividing resistors R1 to R5, the predetermined 6 voltages V0 to V0 are set as the liquid crystal driving voltage. Creating V5. In addition,
In the positive power supply type, 6 voltages are generated from the high voltage positive power supplies VEE and VSS.

Of these 6 voltages V0 to V5, V
0, V1, V4 and V5 are power supply wirings 44a and 44, respectively.
It is supplied to the common driver 17 by b, 44e, and 44f. Further, V0, V2, V3 and V5 are supplied to the segment driver 18 by power supply wirings 44a, 44c, 44d and 44f, respectively.

On the other hand, the final output stages of the common driver 17 and the segment driver 18 are CMs as shown in FIG.
It is composed of an OS switching circuit. And
This CMOS switching circuit is composed of switching elements (FETs: field effect transistors) Q85 to 88 which are four output stages. This output stage Q8
5 to 88 supply only one voltage from the four voltages 81 to 84 supplied by the power supply wirings 44a to 44f to the common electrode and the segment electrode. Therefore, the liquid crystal in the portion sandwiched between the two electrodes is driven according to the potential difference between the two electrodes.

[0011]

The voltages 81 to 84 output from the output stages Q85 to 88 of the CMOS are flag codes for alternating current (alternating current) for preventing direct current from being applied to display contents and liquid crystals. Signal). When this voltage is switched, that is, when three gates of the four output stages Q85 to 88 are set to the non-selected state by the logic circuit and one gate is set to the selected state, CM
The phenomenon of charging the floating capacitance between the gate and drain of the OS output stages Q85 to 88 occurs.

However, although the gate current per FET is small, the CMOS output stage Q8 of FIG.
Since 5 to 88 are provided for each of the common electrode line and the segment electrode line that form the simple matrix of the liquid crystal display device, the total gate charging current per device is 1 even in the VGA (480 pixels × 640 pixels) standard. This is 1120 × 4 times the charging current of the gate.

The charging of the gate / drain capacitance is a transient phenomenon of about several tens of nanoseconds. Therefore, a charging large current having a high frequency component is supplied in the wiring of the power supply system, and this current is supplied from an external power supply. Flows to the FFC 70.

However, since the conductor portion 71 forming the wiring portion of the FFC 70 and the wiring in both the common electrode side and the segment electrode side have a finite parasitic inductance component 72, a transient with a high frequency component is generated. A ringing current 61 as shown in FIG. 6 is generated for the current.

Further, a ringing voltage 62 corresponding to this change in current is generated. This ringing voltage 62 is equal to
The inter-conductor capacitance in the FFC 70 has a period of about nanoseconds.
3 and the inter-wiring capacities in both the common electrode side and segment electrode side substrates couple to the logic circuit system wiring, that is, the power supply wiring of the logic circuit system and the timing clock wiring to which a predetermined signal is supplied. Then, due to this coupling, ringing noise 63 shown in FIG. 6 is generated, which causes malfunction of the logic circuit.

Therefore, in the conventional liquid crystal display device, the ringing noise 63 becomes large when the wiring length in the substrate becomes long or when the cable length of the FFC 70 becomes long, the display operation becomes unstable, and the display quality is deteriorated. There was a problem of causing a decrease.

As a means for solving this problem, for example, a structure as disclosed in Japanese Patent Laid-Open No. 1-215117 is known.

This will be described with reference to FIG. This configuration has an output circuit (C
MOS). Then, a first-stage inverter 93 to which a signal in this device is input, a plurality of final-stage inverters 91 that receive an output signal of the first-stage inverter 93,
And 92. Multiple final stage inverters 91, 9
2 is connected in parallel, and further, on the gate side of one of the final stage inverters 91, 92,
A resistor R94 is inserted.

By thus providing the resistor R94 in one of the inverters 92, two sets of output stage inverters 9 are provided.
The charging currents for the gates of 1,92 are shown in FIG.
As shown in FIG. 11, it is possible to temporally disperse the gate currents for the paired CMOSs, which are simultaneously overlapped. Therefore, the noise due to the gate charging current can be reduced without significantly lengthening the propagation time of the output voltage of the inverter 92.

When this configuration is applied to the driver of the liquid crystal display device, it is possible to prevent the unstable display operation and the deterioration of the display quality due to the noise described above. However, the above-mentioned inverter 93 and the resistor R94 must be built inside the integrated circuit for driving the liquid crystal display device. Therefore, there is a drawback that a ready-made liquid crystal driver cannot be used.

Further, in Japanese Patent Application Laid-Open No. 4-121786, in a power supply circuit of a simple matrix type liquid crystal display device, the influence of noise generated at the time of alternating current (switching of output stage CMOS) on the entire system, that is, noise A configuration that minimizes the instability of the display operation and the deterioration of the display quality due to the above is shown.

This structure will be described with reference to FIG.

The common side driver 121 and the segment side driver 122 are independently configured. It is shown that a noise cutoff circuit including a diode clipper 123 is provided in the voltage supply circuit between the common power source of the common side driver 121 and the segment side driver 122 and each driver.

With such a configuration, noise can be reduced, and instability of display operation and deterioration of display quality can be minimized. However, since fundamentally suppressing the gate charge current in the output stage of the CMOS is not considered,
Coupling occurs in the logic circuit bus and the like in the FFC, the common electrode side, and the segment electrode side. Therefore, even with this configuration, it is not possible to prevent ringing noise due to coupling and prevent malfunction of the logic circuit.

The present invention has been made in order to solve the above problems, and prevents the display operation from becoming unstable and the display quality from deteriorating due to the malfunction of the logic circuit while using the conventional ready-made liquid crystal driver. The purpose is to

[0026]

In a liquid crystal display device according to the present invention, an impedance forming element is provided in each of a plurality of power supply wirings for supplying a plurality of levels of voltage for driving a liquid crystal to an electrode via a switch element. Inserted. The impedance forming element is composed of at least one of a chip impeder and a resistance element.

In a plurality of wirings for supplying a predetermined signal and a predetermined voltage from an external power source to the liquid crystal display device, among these wirings, a high voltage power supply wiring for driving the liquid crystal and a high voltage power supply wiring are paired. And the current recovery wiring that forms the wiring are physically separated from other wiring.

Further, the printed circuit board has a plurality of wirings for supplying a predetermined signal and a predetermined voltage from an external power source to the liquid crystal display device. Among them, the high-voltage power supply wiring for driving the liquid crystal and the current recovery wiring paired with the high-voltage power supply wiring are allocated to a plurality of wirings of the substrate.

Further, the wiring is characterized by being printed on a flexible substrate.

[0030]

According to the invention described in claim 1, the impedance forming element having a large impedance with respect to the current change (ringing current) 61 of the high frequency component shown in FIG. It was inserted into all of the plurality of power supply lines that supply the electrodes.

This makes it possible to reduce the response speed of the power supply wiring to high frequencies and limit the instantaneous large charging current flowing to the gate-drain capacitance of the switch element. Therefore, it is possible to suppress the generation of the ringing voltage 62 in the power supply wiring, which causes a malfunction of the logic circuit,
That is, it is possible to prevent the display operation from becoming unstable and the display quality from being degraded.

According to the second aspect of the present invention, in the plurality of wirings for supplying a predetermined signal and a predetermined voltage from an external power supply to the liquid crystal display device, for example, wirings printed on a flexible substrate, the power supply is used. We paid attention to the fact that coupling of voltage fluctuations (ringing voltage) to other wiring is likely to occur.

Then, among these wirings, the high-voltage power supply wiring for driving the liquid crystal and the current recovery wiring paired with the high-voltage power supply wiring are physically separated from other wirings.

A charging current having a high frequency component for charging the gate-drain capacitance of the liquid crystal driver output stage is connected to the high voltage power supply line for driving the liquid crystal and the current recovery line paired with the high voltage power supply line. (Ringing current) flows. Therefore, by physically separating the two wirings from the wirings such as the timing clock, the coupling can be surely reduced, and the malfunction of the logic circuit, that is, the instability of the display operation and the deterioration of the display quality can be prevented. It will be possible.

According to a fourth aspect of the present invention, further, in the wiring formed by printing on the substrate, a high-voltage power supply wiring in which the ringing current having the above-mentioned high frequency component flows and a current recovery wiring paired with the high-voltage power supply wiring are provided. Was assigned to a plurality of wirings printed on the board.

As a result, the ringing current flowing per wire can be reduced, and the ringing voltage generated by the parasitic inductance component of the wiring on the substrate can be reduced. Therefore, it is possible to prevent malfunction of the logic circuit, that is, instability of display operation and deterioration of display quality.

The above-described structure can achieve the object by itself, but by applying at least two or more of the above-mentioned structures in combination, the malfunction of the logic circuit, that is, the display operation can be more surely achieved. It is possible to prevent instability and deterioration of display quality.

[0038]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a part of a power supply circuit of a liquid crystal display device according to an embodiment of the present invention. In FIG. 1 and the following figures, the same parts as those already described are designated by the same reference numerals and the description thereof will be omitted.

In the figure, high-voltage power supply VEE and power supply VCC
Through the high-voltage power supply wiring 11 and the current recovery wiring (power supply VCC wiring) 12 paired with the high-voltage power supply wiring 11
It is supplied to the CD module 10.

Then, between the high-voltage power supply VEE wiring 11 and the current recovery wiring 12, two voltages of the high-voltage power supply VEE and the power supply VCC are divided and predetermined 6 voltages V0 to V5 for driving the liquid crystal 45 are provided. The voltage dividing resistors R1 to R5 for making are connected in series.

Among the 6 voltages V0 to V5 formed by the voltage dividing resistors R1 to R5, V0, V1, V4 and V5
Are supplied to the common driver 17 by power supply wirings 14a, 14b, 14e and 14f, respectively, and V0, V2, V
3 and V5 are power supply wirings 14a, 14c, 14d,
It is supplied to the segment driver 18 by 14f.

The power supply wirings 14a to 14f are provided with chip impedances 15a to 15f which are impedance forming elements.
And resistor elements R6 to R11 are inserted. Further, the high-voltage power supply wiring 12 for supplying the power supply for driving the liquid crystal to the liquid crystal drive electrode is, along with the current recovery wiring 12 and other timing clock wiring forming a pair with the high-voltage power supply wiring 11, the FFC as shown in FIG. Interface cable 70
Is connected to the control system and external power supply.

The wiring allocation (pin assignment) in the interface cable 70 is as shown in FIG. That is, the high-voltage power supply VEE wiring 53 and this high-voltage power supply V
The power supply VCC wiring (current recovery wiring) 51 that forms a pair with EE,
Assigned to the central part of the cable 70
A ground voltage VSS wiring 52 is assigned between the two wirings.

With the above-mentioned structure, in this embodiment, the liquid crystal driver itself is not changed, and the response speed of the power supply wiring to the high frequency current is lowered, and the CMOS
It is possible to limit the momentary large charging current flowing to the gate / drain capacitance of the switching element (output stage). Therefore, it is possible to suppress the generation of ringing voltage in the power supply wiring,
It is possible to prevent the malfunction of the logic circuit caused by this, that is, the instability of the display operation and the deterioration of the display quality.

The performance of the liquid crystal display device of this embodiment having such a structure will be concretely shown below in comparison with the structure of the conventional device.

As a conventional liquid crystal display device, a simple matrix type liquid crystal display device including the power supply circuit shown in FIG. 4 has been used.

A wiring cable for supplying a control signal and an external power supply voltage output from a display control device (computer or the like) to this device has a pin assignment as shown in FIG. (TW-VF type manufactured by Fujikura Electric Co., Ltd., 1.25 mm pitch, 15 poles) was used. Furthermore, power supply VCC = 3.3V, high voltage power supply VEE = 2
It was driven at 0.8 V and a frame rate of 80 Hz.

As a result of driving, the high-voltage power supply VEE wiring 53 and the power supply VCC wiring 51 are connected to the gate-drain capacitances of the liquid crystal driver output stages 17 and 18 of FIG. 4 having high frequency components as shown in FIG. The charging current 61 flowed. Then, due to the existence of the parasitic inductance component of the wiring, a ringing voltage 62 is generated between the start point and the end point of the high voltage power source VEE wiring and the power source VCC wiring.

Further, in FIG. 5, the high voltage power supply VEE wiring 53
On the ground voltage VSS wiring 52 sandwiched between the power supply VCC wiring 51 and the power supply VCC wiring 51, ringing noise 63 due to coupling with the power supply wirings 51 and 53 was generated.

On the other hand, the FLM (vertical synchronization pulse) wiring 54 located physically far from these wirings 51, 52 and 53 is not affected by the coupling. Therefore, when the potential difference between the FLM wiring 54 for operating the logic circuit and the ground voltage VSS wiring 52 is observed, a ringing voltage 64 having a phase opposite to the ringing voltage 63 generated in the VSS wiring 52 is generated.

Therefore, the ringing voltage 64 generated on the FLM wiring 54 has a maximum wave height of 2.8 V and a maximum width of 5.
It reaches 0 ns and the high level input voltage Vcc required for the liquid crystal driver composed of CMOS etc. is 0.8 (2.64).
The pulse width exceeds V and the high-level pulse width of 40 ns, a malfunction of the logic circuit occurs, and vertical synchronization cannot be achieved, and normal display cannot be performed.

On the other hand, in the liquid crystal display device of Example 1, the power supply circuit shown in FIG. 1 is used, and as the wiring cable, an F-shaped cable having a pin assignment shown in FIG.
FC (TW-VF type, made by Fujikura Electric, 1.25 mm pitch,
15 poles) was used.

Vcc = 3.3V, VEE = 20.8
It was driven at V and a frame rate of 80 Hz. The chip impeders 15a to 15f shown in FIG.
2Y102B was used, and the resistance values of the resistance elements R6 to R11 were 3Ω or 10Ω.

Further, the following four types of impedance forming elements were used to fabricate liquid crystal display devices and carry out experiments.
(1) Only the chip impellers 15a to 15f are mounted. (2) Mounted only with the resistance elements R6 to R11 (3Ω). (3) The chip impedances 15a to 15f and the resistance elements R6 to R11 (3Ω) are both mounted.
(4) Chip impeders 15a to 15f and resistance element R6
-Mounted with both R11 (10Ω).

The driving results are shown in FIG.
That is, in each of the four types of liquid crystal display devices (1) to (4), the charging current (IEE, ICC) 31 of the gate-drain capacitance flowing through the VEE wiring 53 and the VCC wiring 51 has a high frequency component. By inserting the impedance forming element exhibiting a large impedance with respect to the change, the charging current 61 was clearly reduced as compared with the charging current 61 in FIG.

Further, the ringing voltage 32 measured at the start point and the end point of the VEE and Vcc wirings also decreases.

Further, along with this, the ringing noise 33 of the VSS wiring 52 generated due to the coupling between the conductors of the FFC is also reduced. Therefore, the potential difference between the FLM (vertical synchronization pulse) wiring 54 and the VSS wiring 52 is observed. The ringing voltage 34 at that time was also extremely small.

The maximum value of the ringing voltage 34 generated in the FLM wiring 54 is 0.25 V under the condition (1) (only the chip impeder) and the condition (resistance (3
Ω)} was 0.28 V, under the condition (3) {Chip Impeder and resistance (3 Ω)} it was 0.21 V, and under the condition (4) {Chip Impeder and resistance (10 Ω)} it was 0.16 V. As described above, under any of the conditions, since the low level input voltage Vcc of the liquid crystal driver is below 0.2 (0.66) V, the state where the malfunction of the logic circuit can be reliably prevented is maintained, It became possible to display normally.

(Embodiment 2) Next, a configuration different from that of Embodiment 1 will be described.

In this embodiment, the liquid crystal display device shown in FIG.
A simple matrix type liquid crystal display device having the power supply circuit shown in was used.

A wiring cable for supplying a predetermined control signal and a voltage from an external power source to the liquid crystal display device shown in FIG. 4 is a pin-assigned FFC as shown in FIG.

That is, on the FFC, the high voltage power source VEE wiring 21 for driving the liquid crystal and the current recovery wiring (power source VCC wiring) 22 paired with the high voltage power source VEE wiring 21 are connected to each other with no connection conductor N.
It was physically separated from the wiring 23 for control signals such as other timing clocks by C24. When the liquid crystal display device is of a positive power source drive type, VEE wiring and VSS wiring are
Physically separate from the timing clock wiring on the FC.

The high-voltage power supply VEE wiring 21 and the current recovery wiring 22 are connected to the plurality of wirings 21a, 21b and 2 of the FFC.
2a and 22b are assigned respectively.

The FFC has a total length of 250 mm.
(TW-VF type made by Fujikura Electric, 1.25 mm pitch, 18
Pole).

Vcc = 3.3V, VEE = 20.8
It was driven at V and a frame rate of 80 Hz.

As a result of the driving, as shown in FIG. 3, the gate-drain capacitance charging current 31 flowing in the VEE wiring 21 and the VCC wiring 22 is divided into a plurality of wirings 21a, 21b and 22a in the VEE wiring 21 and the VCC wiring 22, respectively. , 22b.

Therefore, the ringing voltage 32 measured at the start point and the end point of the VEE wiring 21 and the VCC wiring 22 was also reduced.

Further, on the FFC, VEE wiring 21 and VCC
The wiring 22 and the timing clock line 23 are physically separated from each other. As a result, FF is connected to the VSS wiring 25.
The ringing noise 33 generated by the coupling between the conductors of C was also reduced, and the ringing voltage 34 when the potential difference between the FLM wiring 26 and the VSS wiring 25 was observed was also very small.

The ringing voltage 34 generated in the FLM wiring 26 has a maximum peak height of 0.30 V, which is lower than 0.2 (0.66) V of the low level input voltage Vcc of the liquid crystal driver. Therefore, the prevention of malfunction of the logic circuit can be maintained and the normal display can be performed.

In this embodiment, the high voltage power supply VEE wiring 21 and the current recovery wiring 22 are provided on the FFC.
The wiring 23 is physically separated from the other wirings 23, and each wiring is allocated to a plurality of wirings (conductors). However, it is possible to reduce the ringing voltage even if only one of the configurations is used without necessarily adopting both the separation of wiring and the allocation to a plurality of wires.

(Third Embodiment) An example in which the first and second embodiments are further improved will be described below.

In this embodiment, a simple matrix type liquid crystal display device having the power supply circuit shown in FIG. 1 was used as the liquid crystal display device.

The liquid crystal display device and the display control device were connected by the pin assignment FFC shown in FIG.
The FFC is an FFC with a total length of 250 mm (TW-manufactured by Fujikura Electric Cable)
VF type, 1.25 mm pitch, 18 poles), Vcc =
3.3V, VEE = 20.8V, frame rate 80H
Driven with z.

As the impedance forming element of FIG.
Chip Impeders 15a-15f (MMZ20 made by TDK
12Y102B) and the resistance elements R6 to R11 (3Ω) were inserted into the power supply wirings 14a to 14f.

According to the configuration of this embodiment, the effects of the first and second embodiments are synergistically obtained.

That is, the ringing voltage obtained by the configuration of the first embodiment is (1) 0.25 V and (2) 0.28.
V, (3) 0.21V, and (4) 0.16V. In addition, the ringing voltage of Example 2 is 0.30V.

On the other hand, in the driving result of this embodiment, the ringing voltage 34 generated in the FLM wiring 26 is
Has a maximum wave height of 0.12V, which is extremely small as compared with the other examples, and is completely lower than the low level input voltage 0.2VCC (0.66V) of the liquid crystal driver. Therefore, the malfunction of the logic circuit can be surely prevented, and the instability of the display operation and the deterioration of the display quality can be prevented.

In the first and third embodiments,
A chip impeder and a resistance element having a resistance value of 3Ω and 10Ω are used as the impedance forming element, but the present invention is not limited to this. Further, the resistance value of the resistance element is not limited to 3Ω and 10Ω, and is effective in the range of 1Ω to 15Ω, for example.

Furthermore, in the second and third embodiments,
The number of high-voltage power supply wirings in the FFC and the number of power supply recovery wirings paired with the high-voltage power supply wirings is not limited to two, and may be any number within the allowable range on pin assignment. Moreover, if the high-voltage power supply wiring, the power recovery wiring, and the other wiring are physically separated, the number of unconnected wires that separate the other wiring is not limited to one, and the allowable range in pin assignment You can use multiple of the above.

[0081]

As described above, according to the first aspect of the invention, the impedance forming element exhibiting a large impedance with respect to linking noise is provided with a plurality of steps of potentials for driving the liquid crystal through the switch element. And was inserted into all of the plurality of power supply lines respectively supplied to the electrodes.

As a result, the response speed of the power supply system wiring to high frequencies can be reduced, and the instantaneous large charging current flowing to the gate-drain capacitance of the switch element can be limited. Therefore, it is possible to suppress the generation of the ringing voltage in the power supply wiring, and it is possible to prevent the malfunction of the logic circuit caused by this, that is, the instability of the display operation and the deterioration of the display quality.

According to a second aspect of the present invention, in a plurality of wirings for supplying a predetermined signal and a predetermined voltage from an external power supply to the liquid crystal display device, a high voltage power supply wiring for driving the liquid crystal and a high voltage power supply. The wiring and the current collecting wiring forming a pair are physically separated from the other wiring.

A linking current for charging the gate-drain capacitance of the output stage of the liquid crystal driver flows through the liquid crystal driving high-voltage power supply wiring and the current recovery wiring paired with the high-voltage power supply wiring. Therefore, by physically separating the two wirings from the wirings such as the timing clock, the coupling can be surely reduced, and the malfunction of the logic circuit, that is, the instability of the display operation and the deterioration of the display quality can be prevented. It will be possible.

Further, the invention according to claim 4 is, in a wiring cable printed on a substrate, a high-voltage power source wiring for driving a liquid crystal and a high-voltage power source wiring for flowing a linking current having the above-mentioned high frequency component. The pair of current collecting wirings were allocated to the plurality of wirings printed on the substrate.

As a result, it is possible to reduce the linking current flowing per wire and reduce the ringing voltage generated by the inductance component of the wiring on the substrate. Therefore, it is possible to prevent malfunction of the logic circuit, that is, instability of display operation and deterioration of display quality.

Although the above-described configurations can achieve the object by themselves, by applying at least two of the above configurations in combination, the malfunction of the logic circuit, that is, the failure of the display operation can be more reliably achieved. It is possible to prevent stability and deterioration of display quality.

[Brief description of drawings]

FIG. 1 is a diagram showing a power supply circuit of a liquid crystal display device according to first and third embodiments of the present invention.

FIG. 2 is a diagram showing pin assignments of FFCs according to Embodiments 2 and 3 of the present invention.

FIG. 3 is a diagram showing a noise generation state according to the first embodiment, the second embodiment, and the third embodiment of the present invention.

FIG. 4 is a diagram showing a power supply circuit of Example 1 of the present invention and a conventional liquid crystal display device.

FIG. 5 is a diagram showing a wiring cable of the liquid crystal display device.

FIG. 6 is a diagram showing a conventional noise generation state.

FIG. 7 is a diagram showing parasitic inductance and parasitic capacitance in the FFC.

FIG. 8 is a diagram showing a circuit configuration of a common driver 17 and a segment driver 18.

FIG. 9 is a diagram showing a circuit configuration of a CMOS mounted on the output side of a conventional semiconductor circuit device.

FIG. 10 is a diagram for explaining gate current output characteristics of the semiconductor circuit device of FIG. 9.

11 is a diagram showing improved gate current output characteristics of the semiconductor circuit device of FIG.

FIG. 12 is a diagram showing a configuration of a power supply circuit of a conventional simple matrix type liquid crystal display device.

[Explanation of symbols]

14a-f power supply wiring, 15a-f chip impeder, R6-R11 resistance element, 17 common driver,
18 segment driver, 21 high voltage power supply VEE wiring,
22 current recovery wiring, 23 timing clock wiring,
24 unconnected conductor NC, 25 VSS wiring, 26 FLM
When observing the gate / drain capacitance charging current flowing in the wiring, 31 VEE wiring and VCC wiring, 32 VEE, ringing voltage measured at the start and end points of VCC wiring, 33 ringing noise, and the potential difference between 34 FLM wiring and VSS wiring. Ringing voltage.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takuhi Sakai 325 Kamimachiya, Kamakura City, Kanagawa Mitsubishi Electric Corporation System Works

Claims (6)

[Claims] 1. A liquid crystal display device for driving a liquid crystal to perform a predetermined display by electrodes provided with a liquid crystal sandwiched therebetween. A liquid crystal display device comprising a plurality of power supply wirings to be supplied, wherein an impedance forming element is inserted in each of the power supply wirings. 2. A liquid crystal display device for driving a liquid crystal to perform a predetermined display by electrodes provided with the liquid crystal interposed therebetween, wherein a predetermined signal and a predetermined voltage from an external power supply are supplied to the liquid crystal display device. A liquid crystal display having a plurality of wirings, wherein, of the wirings, a high-voltage power supply wiring for driving a liquid crystal and a current recovery wiring paired with the high-voltage power supply wiring are physically separated from other wirings. apparatus. 3. The liquid crystal display device according to claim 1, further comprising a plurality of wirings for supplying a predetermined signal and a predetermined voltage from an external power source to the liquid crystal display apparatus, wherein the wiring is for driving a liquid crystal. 2. The liquid crystal display device, wherein the high-voltage power supply wiring and the current recovery wiring forming a pair with the high-voltage power supply wiring are physically separated from other wirings. 4. The liquid crystal display device according to claim 1, 2, or 3, wherein a plurality of wirings printed on a substrate are provided on the liquid crystal display device. A plurality of wirings for supplying a signal and a predetermined voltage from an external power supply, and among the wirings, a high-voltage power supply wiring for driving a liquid crystal, and a current recovery wiring paired with the high-voltage power supply wiring, A liquid crystal display device characterized by being assigned to a plurality of wires. 5. The liquid crystal display device according to claim 1, wherein the impedance forming element is at least one of a chip impedance and a resistance element. 6. The liquid crystal display device according to claim 2, 3, or 4, wherein the wiring is printed on a flexible substrate.