JPH07294870A - Thin film transistor circuit and liquid crystal display device using the above circuit - Google Patents

Abstract

PURPOSE:To reduce the size and to improve the preciseness and the display quality of a liquid crystal display device. CONSTITUTION:In a thin film transistor circuit and the liquid crystal display device using the above circuit, a minute pitch is realized by efficiently laying out switching circuits SW1, SW2, SW3... of a data line driving circuit. Moreover, gate wirings which drive the circuits above are commonly used and the driving timing is made coincident. Furthermore, by making the shape of all leader line wiring same, the pattern dependability is eliminated and thin film transistor circuits having a wiring constitution with equal resistive values are provided. Thus, the driving circuits of a liquid crystal display device is provided, in which the size of the device is reduced and the preciseness and the display quality are improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor circuit and a liquid crystal display device using the thin film transistor. In particular, it relates to a wiring structure and materials around a switch circuit of a drive circuit of a liquid crystal display device on an insulating substrate.

[0002]

2. Description of the Related Art In a liquid crystal display device which displays an image by utilizing the electro-optical characteristics of liquid crystal, a thin film element such as a TFT (thin film transistor) is formed on a transparent substrate as a switching element of each pixel, and a voltage applied to the liquid crystal. It has succeeded in obtaining an excellent display quality by controlling. Furthermore,
In place of the LSI, a driving circuit built-in technology in which a driving circuit for a liquid crystal display body is integrally formed with TFTs around a pixel matrix on a substrate has also been widely used. With this drive circuit built-in technology, the liquid crystal display device can be made compact and at the same time cost can be reduced.

In general, an active matrix type liquid crystal display device has a transparent substrate 1 as shown in a block diagram in FIG. 1 (here, the number of video signal lines is three).
1. The pixel matrix 22 and the scanning line drive circuit 2 on the front surface side of 1.
1 and the data line drive circuit 12 are formed. The scanning line drive circuit 21 has a scanning line drive timing control unit and a buffer circuit, and the scanning line Y is output by the buffer circuit.
1, Y2, Y3 ... Are driven. When the scanning line is in the selected state, the pixel TFT 4 connected thereto has a low resistance and the video signal can be written in the liquid crystal capacitor 2 and the storage capacitor 3. The data line drive circuit 12 includes a data line drive timing control section including a shift register, switch circuits SW1, SW2, SW3 ... Composed of TFTs, and video signal lines V1, V2, V3. From the timing control unit side, the switch circuits SW1, SW2, SW3
The bit signal output from the data line drive timing control unit is indicated by ... in the switch circuit drive gate lines G1 and G.
2, G3 ... Can be input. Therefore, the bit signals are the switch circuit driving signal lines G1, G2,
Each switch circuit SW1, SW2, S via G3 ...
When input to W3 ..., each switch circuit SW1, S
W2, SW3 ... Switch from the high resistance state to the low resistance state. By this switching, the video signal lines V1 and V
The video signals supplied to V2 and V3 are data lines X1 and X
2, Pixels P1, P2, P3 ...
At, the video signal changes the alignment state of the liquid crystal of the liquid crystal cell 2 to display the screen.

In recent years, in a liquid crystal display device with a built-in drive circuit, the pixel matrix pitch has become extremely small due to miniaturization and higher definition. Along with this, the number of scanning lines and data lines tends to increase, and at the same time, the wiring pitch tends to become smaller. Therefore, in the liquid crystal display device with a built-in driver, it is necessary to reduce the pitch of the switch circuits located near the pixel portion. However, the TFT has a gate length of L
Since it cannot be on the order of submicrons like SI, there is a limit to reducing the area occupied by one circuit. In order to solve this problem, there is a technique for reducing the number of data lines itself (Japanese Patent Laid-Open No. 5-26).
5045). By sharing the data line by two pixels, the number of data lines is halved, while the number of scanning lines is increased, and the wiring pitch on the data line side, which has a severe pitch, is set to 2
It is a method of expanding twice.

Next, an example of a TFT manufacturing process will be described (see FIG. 3). First, the semiconductor layer 1 of polysilicon or the like, which becomes the channel region, the source, and the drain region later, is formed. Then, the semiconductor layer is oxidized by thermal oxidation or the like to form a gate insulating film 8, and a gate line and gate electrodes G1P and G1N are formed on the gate insulating film 8 with silicide or refractory metal. Then, using this gate electrode as a mask, n ⁺ and p ⁺ ions are implanted to form source and drain regions, thereby forming a self-aligned TFT. After forming the interlayer insulating film 9 on this, the source,
A contact hole 5 is opened to electrically connect the drain portion to the wiring, and low resistance metal wirings 6 and 7 such as aluminum are formed to complete P-type and N-type TFTs. Thus, the gate wirings G1P and G1N and the aluminum wirings 6 and 7 are separated by the interlayer insulating film 9, and these wirings are conductively connected only through the contact holes. In this TFT process, the source is formed by ion implantation,
After forming the drain, high temperature activation is performed. Therefore, the gate wiring must be made of a material that can withstand this high temperature, and low resistance metal wiring cannot be used. Therefore, materials such as polysilicon and silicide are usually used. As a result, the gate wiring usually has a higher resistance than the metal wiring.

FIG. 2 exemplifies a part of the layout on the substrate around the video signal lines of the data line driving circuit (here, a case where a CMOS analog switch is used as a switch circuit is shown). Due to the arrangement of the data line driving circuit 12 and the pixel matrix 22, the video signal lines V1, V2, V3 and the lead wirings S1, S2, S3, ... Inevitably intersect. Therefore, as shown in the drawing, the lead wires S1, S2, S3, ... Are wired in different layers via the video signal line and the insulating film on the substrate of the actual liquid crystal display device, and the necessary image is provided through the contact hole 5. Only the signal line is conductively connected.

FIG. 3 is a sectional view of the switch circuit (CMOS analog switch) of FIG. The video signal from the video signal line is input to the source side 7 of the P-channel and N-channel transistors formed on the insulating substrate via the lead wiring. When a signal from the data line driving timing control section is input to the switch circuit driving gate electrodes G1P and G1N, at least one of the channel regions of the P-channel transistor and the N-channel transistor has a low resistance, and the contact hole 5 is used. A video signal is written in the data line via the drain side wiring 6 connected to the drain.

Here, the correspondence between the wiring around the video signal line and the TFT process will be described. Video signal line V1
Since V3 has a large load capacity, a low resistance wiring is required, and a metal wiring such as aluminum is usually used. This is made in the same process as the metal wirings 6 and 7 in the TFT manufacturing process. On the other hand, since the lead wirings S1 to S3 that intersect the video signal line have to be formed in a layer different from the metal wiring, they are arranged below the video signal line through the interlayer insulating film 9 and the gate wiring of the TFT manufacturing process. G1P, G1
The same material as N is used. The resistance value of the gate wiring is higher than that of the metal wiring, and the lead wiring portion has a higher resistance than the video signal line. In particular, when the process temperature is high and the metal wiring cannot be used and a material such as silicide is used, the sheet resistance of the wiring may be higher than that of the aluminum wiring by one digit or more. For example, when aluminum is used for the wiring with a film thickness of 5000Å, the sheet resistance of this wiring is about 0.05Ω, whereas when using polysilicon for the same wiring, the sheet resistance of this wiring is about 15Ω. Become. As a result, the writing of the video signal to the data line is largely influenced by the resistance of the lead wiring. Since the lead-out wirings are connected to different video signal lines, the resistance value varies among the wirings. Therefore, the writing of the video signal to the data line is varied, resulting in deterioration of display quality.

In order to prevent the deterioration of the display quality, the conventional methods shown in FIGS. 4 and 5 have been adopted. In the method of FIG. 4, the variation of the resistance value between the wirings is eliminated by increasing the wiring width of the lead wirings S1, S2, S3 ... In proportion to the wiring length. Further, in the method of FIG. 5 (Japanese Patent Laid-Open No. 5-307165), the variation of the resistance value is eliminated by changing the shape of the lead wiring according to the wiring length.

[0010]

In the conventional method of reducing the data wiring, the load of the data line becomes large. Therefore, when the number of pixels is large and the signal writing time to the data line is short, the load of the data line driving circuit is increased. Connect Since the TFT has poorer crystallinity and higher on-resistance than a single crystal MOSFET formed on a silicon substrate, an increase in the load of the switch circuit, especially in a liquid crystal display device with a built-in drive circuit, leads to deterioration of display quality. Therefore, it is necessary to efficiently layout the switch circuits without reducing the number of data lines.

Further, the conventional technique is characterized in that the wiring resistance values are made uniform by making the shapes of the lead wires different from each other. For this reason, in the conventional method, the magnitude of the resistance of the lead wiring has pattern dependence. That is, even if a pattern is formed on the mask so that the resistance values of the lead-out wirings are the same, the finished pattern of the pattern on the actual substrate varies in shape, and as a result, the resistance value of the lead-out wirings is different for each wiring shape. Will be different. Therefore, the produced liquid crystal display device still has a variation in display quality. There is a problem in that it is difficult to design a pattern on a mask in consideration of this pattern dependency, and even if it can be done, this method cannot deal with it when the process conditions change.

Further, in the active matrix liquid crystal display device, the number of video signal lines tends to increase as the number of pixels increases due to color display and miniaturization and high definition. This is because the number of video signal lines is increased and the substantial writing frequency is lowered. Therefore, the number of intersections between the lead wiring and the video signal line is increased, and at the same time, the length of the lead wiring is also increased. The longer the length of the lead-out wiring, the greater the difference between the shapes of the lead-out wirings in the conventional method, and the stronger the pattern dependence. In other words, the conventional method has a problem that the reliability decreases as the number of pixels increases and the number of video signal lines increases.

As described above, the problem of the prior art is that a thin film transistor capable of coping with a fine pitch is required, and at the same time, uniformity of writing of a video signal is maintained.

[0014]

In FIG. 1, a substrate 11 is provided.
There is the data line driving circuit 12 formed between the upper pixel matrix 22 and the outer peripheral edge of the substrate, and the side direction (horizontal direction in the drawing) of the outer peripheral edge is the X direction, and the pixel matrix 22 is formed from the outer peripheral edge. The direction (vertical direction in the figure) is the Y direction. The present invention makes it possible to deal with a fine pitch in the layout in the X direction by arranging the circuits using the thin film transistors in the Y direction so as to be offset from each other, and by optimizing the layout of the switch circuit and the video signal line It is characterized in that variation between wirings is suppressed. In addition, by aligning the shapes of the lead wires, there is no process dependence, the resistance value is constant, and a layout that corresponds to a fine pitch is possible, while at the same time eliminating variations in display characteristics and improving display performance. It is characterized by being

[0015]

【Example】

(Embodiment 1) FIG. 6 shows an embodiment of the present invention in the case where a switch circuit constituted by using thin film transistors is applied to a drive circuit of a liquid crystal display device. Here, a part of the wiring structure around the switch circuit and the video signal line is illustrated. The three video signal lines V1, V2, and V3 are connected to the respective data lines X1 via the lead wirings S1 to S3 and the switch circuits SW1 to SW3.
~ 3 connected. Each switch circuit switches between high resistance and low resistance according to the timing when the bit signal output from the drive timing control unit is applied to the switch circuit driving gate line G123.

In a switch circuit such as an analog switch, a video signal must be written in a data line in a short time,
For this purpose, the resistance must be sufficiently low in the selected state.
However, since the TFT has poorer crystallinity than the single crystal MOSFET, when a switch circuit such as an analog switch is formed using the TFT, it is necessary to increase the channel width in order to obtain a sufficiently low on resistance. In fact, single crystal MO
The channel width must be increased by one digit or more as compared with the case of SFET. Also, the channel length is single crystal MOS.
Since it cannot be made small like an FET, there is a limit to making the pitch in the X direction small, and as a result, the switch circuit occupies a considerably large area in the drive circuit. Therefore, in the drive circuit of the liquid crystal display device, how to efficiently arrange the switch circuit in a small space is a key to downsizing and high definition. When color display is performed using a color filter, since video signals of R, G, and B colors are input from the outside, the number of video signal lines is generally 3n (n is a positive integer). Become. The on / off timings of the switch circuits for writing these signals to the respective data lines must be aligned when writing signals of at least three colors.

In the thin film transistor circuit of the present invention shown in FIG. 6, adjacent switch circuits SW1 to SW3 are arranged in the Y direction (vertical direction in the drawing) at a distance of at least the channel width (W) of the TFTs forming the switch circuit ( (D> W in FIG. 6)
It is characterized by As a result, if the switch circuits are arranged so as to be displaced from each other in the X direction (horizontal direction in the figure) as shown in the figure, the pitch in the X direction per switch circuit can be made small and it becomes possible to cope with a fine pixel pitch. Therefore, it is easy to make the liquid crystal display device compact and highly precise.

In the case of a single crystal MOSFET, if the wiring on the silicon substrate is long, a capacitance is generated between the wiring and the silicon substrate by that much, so it is the iron rule to shorten the wiring length anyway. Since the switch circuit composed of thin film transistors requires a considerably long channel width as described above, it becomes large in the Y direction, and when the arrangement shown in FIG. 6 is taken, the wiring lengths of the lead wirings S1 to S3 become considerably long. In the case of a wiring on a silicon substrate, the problem of parasitic capacitance is large, but in a wiring in a thin film transistor on an insulating substrate, since the capacitance between the wiring and the substrate does not occur at all, an increase in wiring length is hardly a problem. Therefore, the arrangement of the switch circuit of the present invention is particularly effective when the circuit is formed using thin film transistors.

FIG. 7 shows a thin film transistor circuit of the present invention. The thin film transistor circuit of the invention is characterized in that a plurality of switch circuits share a switch circuit driving gate line. The three switch circuits SW1 to SW3 are driven by signals input to the switch circuit driving gate lines G1 to G3. These switch circuit driving gate lines G1 to G1
G3 is conductively connected to one switch circuit driving gate line G123, and only G123 has a layout in which it crosses the video signal line. In the arrangement of the present invention shown in FIG. 7, since the three switch circuits share the switch circuit driving gate lines, the switch circuit driving gates that cross the video signal lines to drive these three switch circuits are provided. The number of lines is one, so that the number of intersections of the switch circuit driving gate lines and the video signal lines is three. On the other hand, in the conventional wiring shown in FIG. 4 and FIG. 5, three switch circuit driving gate lines G1 to G3 are wired to drive the three switch circuits SW1 to SW3. Gate line and video signal line V1
There are nine intersections with ~ V3. By thus sharing the gate line with a plurality of switch circuits, it is possible to reduce the number of intersections of the switch circuit driving gate line and the video signal line, and accordingly, the yield due to a short-circuit defect between wirings can be reduced. You can prevent the decline. At the same time, the inter-wiring capacitance between the video signal line and the switch circuit driving gate line is reduced, so that the load capacitance of the video signal line is reduced and the load of the external circuit for writing the video signal on the video signal line can be reduced. .

Further, as shown in FIG. 6, the switch circuits SW1 to SW1
By arranging SW6 in the Y direction with a channel width of W or more, the switch circuit driving gate lines G123 and G45 can be arranged.
6 can also be shared. As shown in FIG. 6, the switch circuits SW1 to SW6 arranged apart from each other in the Y direction.
Between the switch circuit driving gate lines G123 and G456
Space for Y direction is provided. Letting D be a length obtained by adding the layout space of the switch circuit driving gate lines to the Y direction layout width of the switch circuit, at least the respective switch circuits have a pitch D.
If the switch circuits are arranged apart from each other only in the Y direction, the switch circuit driving gate lines can be arranged between the switch circuits that are displaced in the Y direction as illustrated. This enables sharing of the switch circuit driving gate line. With this layout, not only the space occupied by the gate wiring can be saved and a fine pitch can be accommodated, but also the switch circuits sharing the switch circuit driving gate line can be driven at exactly the same timing. If the switch circuits, which must have the same drive timing, are arranged in the Y direction at a distance larger than the channel width and share these gate lines, these switch circuits are always driven at the same timing. As described above, by arranging the switch circuits in the Y direction by at least the channel width and sharing the switch circuit driving gate line,
In addition to being able to respond to miniaturization, the drive timing of the switch circuit can be aligned, and further, the reduction of the switch circuit drive gate line intersecting with the video signal line can improve the yield and reduce the load on the external circuit. Is particularly effective when applied to a switch circuit.

In the thin film transistor circuit of the present invention, when the pitch of the switch circuits in the Y direction is D, the wiring width of the video signal lines is WV, and the inter-wiring distance of the video signal lines is SV, D = W
It is characterized by being V + SV. Here, as shown in FIG. 6, D is the pattern pitch in the Y direction of the adjacent switch circuits, WV is the wiring width in the Y direction of the video signal lines, and SV.
Is determined by the distance between the video signal lines in the Y direction. By setting the sizes of the video signal line and the switch circuit so as to satisfy these conditions, the distance between the switch circuit and the video signal line can be easily aligned.
As a result, the lead wires connecting the switch circuit and the video signal line can all have the same wiring length, so that the variation in the resistance value of the lead wires can be suppressed, and the writing characteristics of the video signal to the data line can be reduced. improves. At the same time, since the lead wires have the same wiring length, the resistance value of the lead wires is simply determined by the width of the lead wires. Therefore, the wiring resistance can be easily calculated at the design stage, and the efficiency of the design can be improved.

FIG. 8 shows a schematic diagram of the thin film transistor circuit of the present invention relating to the connection between the video signal line and the switch circuit.
In the thin film transistor of the present invention, the number of video signal lines is m × n.
A video (m and n are positive integers) and when the m switch circuits are arranged in the Y direction at a distance greater than or equal to their channel widths, the m switch circuits are connected via the lead wiring. The signal lines are characterized in that there is an interval of 1 in n in the m × n video signal lines. By combining the connection of the switch circuit and the video signal line as described above, it is possible to minimize the variation in length between the lead wires connecting the video signal line and the switch circuit. For example, in FIG. 8, m =
3 and n = 2. Three (= m) switch circuits SW1, SW2, and SW3 are arranged in the Y direction with a channel width or more apart from each other, and these switch circuits are connected via lead wires S1, S2, and S3. Are V1, V2, and V3, respectively, and these video signal lines have an interval of two (= n) lines. If SW3 is connected to V3 and SW2 next to it is V6
In addition, if the adjacent SW1 is connected to V2, the other lead wires S4, S5, and S6 will necessarily be S1 and S.
2, it becomes shorter than the lead wire of S3. However, by connecting the video signal line and the switch circuit according to the connection method of the present invention, it is possible to minimize the variation in the wiring length of the extraction wiring. Further, by appropriately setting the space occupied by the switch circuit and the video signal line, it is possible to make the distance between the video signal line and the switch circuit uniform.

Further, as shown in FIG. 8, by adjusting the wiring lengths LS of the lead wires and at the same time making the wire width the same for all the lead wires, the shape of all the lead wires can be made the same. Here, as shown in FIG. 8, the wiring length of the lead wiring is the video signal line,
Distance L between contact holes for conductive connection with the switch circuit
Define by S. In FIG. 8, all of the lead wires S1 to S6 have the same wire length LS and the same wire width, and are made to have a constant resistance value.

In a liquid crystal display device, when a series of paths of a video signal line, a lead wire, a switch circuit, and a data line is viewed as a whole, this is a low-pass band consisting of a resistor connected in series and a capacitor connected in parallel. Forming a circuit.
Therefore, how much the video signal can be written in the data line is determined by the time constant which is the product of the resistance value and the capacitance value. Therefore, if this time constant differs for each data line, non-uniform writing will be performed. In order to prevent this, it is necessary to make the resistance values of the lead wires particularly uniform in the series of paths.
Since the wiring of the liquid crystal display device has no load capacitance generated between the wiring and the substrate, the variation of the wiring resistance has a greater influence on the writing of the video signal than the wiring length. By aligning the shapes (length and width) of the lead wires as described above, the shape of the path of the video signal written from the video signal line to the lead wire and the data line through the analog switch is all the same, and the display quality due to variations in write characteristics Can be prevented. At the same time, since the shape is the same in all video signal paths, there is no pattern dependence and the pattern on the substrate always has the same finished shape. Even if the thin film transistor formation process changes, the finished shape is always the same. Therefore, it is possible to obtain a thin film transistor circuit having stable writing characteristics that is not influenced by the process.

FIG. 9 shows an embodiment in which a metal having a high melting point is used as the lead wiring. As described above, by using a refractory metal such as tantalum, tungsten, or chromium as compared with the case where a wiring such as a silicide is used as the lead wiring, a high temperature process can be used and at the same time, the resistance values of the lead wirings S1 to S6 can be increased. It can be reduced by one digit or more. Therefore, it is possible to increase the distance SV between the video signal lines as shown in FIG. 9 without worrying about the deterioration of the writing characteristics of the video signal to the data line due to the resistance of the lead wiring. As a result, the inter-wiring capacitance between the video signal lines is reduced, and the capacitance itself of the video signal lines can be reduced. In long wiring on an insulating substrate such as a video signal line, there is no capacitance between the wiring and the substrate, but the capacitance of adjacent wiring is effective. In particular, this becomes remarkable as the wiring length is longer such as the video signal line. By increasing the distance between the wirings as shown in the figure, the capacitance between the wirings can be reduced and the writing of the video signal from the outside to the video signal line can be improved. By thus using the high melting point material for the lead-out wiring, it is possible to reduce the time constant of the video signal line and improve the writing characteristics of the high frequency video signal, and it is possible to obtain a thin film transistor circuit having good frequency characteristics. .

(Embodiment 2) The liquid crystal display device of the present invention is shown in FIG.
The wiring structure around the switch circuit shown in the block diagram has the layout shown in FIG. When performing color display using a normal color filter, video signals corresponding to red (R), green (G), and blue (B) are input from the data line driving circuit side. Therefore, considering the same pixel size as in the case of monochrome display, the same pixel is 3 in the X direction.
The pixel is divided and the R, G, and B color filters are associated with the respective pixels. That is, the number of pixels in the X direction is tripled, and the pixel pitch is ⅓. Therefore, particularly in the case of color display, how to make the thin film transistor circuit in the X direction in the data line driving circuit correspond to a fine pitch determines the miniaturization and high definition. By arranging the switch circuits in the Y direction so as to be separated from each other by the channel width or more as in the layout of the switch circuits shown in FIG. 6, the pitch in the X direction occupied by each switch circuit is reduced, and the writing ability to the data line is maintained. However, it becomes possible to cope with a fine pitch in the X direction. Accordingly, it is possible to support color display without changing the size of the liquid crystal display device.

Further, the liquid crystal display device of the present invention is characterized by having the wiring structure of FIG. 6 as the wiring structure around the switch circuit shown in the block diagram of FIG. The case where the number of video signal lines is 6 is shown here. The three switch circuits are arranged in a space-saving manner in the Y direction, and these three switch circuits share the switch circuit driving gate line. At the same time, video signals corresponding to the R, G, and B3 primary colors are externally input to the video signal lines V1, V2, and V3 to which these three switch circuits are connected via the lead wiring. The three switch circuits that share the switch circuit driving gate line are in the low resistance state at the same time when a signal is input to the switch circuit driving gate line, so that the R, G, and B video signals are exactly the same. The data line can be written at the timing. As a result, it is possible to reduce the color unevenness due to the deviation of the write timings of the R, G, and B signals, and to obtain a liquid crystal display device having good display characteristics.

Further, the liquid crystal display device of the present invention has a wiring structure around the switch circuit shown in the block diagram of FIG.
It is characterized by having the layout shown in. In the case of color display, a plurality of video signal lines are inevitably required, and it is required that there is no variation in writing each signal. By using the layout of FIG. 8, the shape of the lead-out wiring can be made almost the same for all the data lines, so that it is possible to eliminate the variation in the writing characteristics for each data line, and as a result, it is possible to eliminate the unevenness of the luminance for each data line. it can.

The liquid crystal display device of the present invention is characterized in that the wiring structure around the switch circuit shown in the block diagram of FIG. 1 uses a lead wiring material of refractory metal and has a layout shown in FIG. When the inter-wiring capacitance of the video signal line increases, the load of the external circuit for writing the video signal on the video signal line increases. This is because the output resistance of the external circuit has to be lowered to reduce the time constant, and the current consumption of the external circuit increases. In the liquid crystal display device of the present invention, since the high-melting-point metal wiring is used for the lead-out wiring, the length of the lead-out wiring need not be taken into consideration,
As a result, a sufficient distance can be secured between the video signal lines. Therefore, the load on the external circuit can be reduced.

[0030]

As described above, in the thin film transistor circuit of the present invention, since the adjacent switch circuits are separated from each other by more than the channel width of the switch circuits in the Y direction, the switch circuits can be arranged in the X direction. The pitch in the X direction occupied by each piece can be reduced. Therefore, fine pitch can be achieved. Further, since a plurality of switch circuits share the switch circuit driving gate line, the number of switch circuit driving gate lines intersecting with the video signal line can be reduced, which allows the video signal line and the switch circuit driving gate line to be connected. Defects due to short circuits at the intersections of can be reduced, leading to improved yield and cost reduction. Further, the adjacent switch circuits are arranged in the Y direction separated by the channel width and the space for arranging the switch circuit driving gate lines, and the switch circuit driving gate lines are shared, so that a finer pitch can be achieved. At the same time, the drive timings of the switch circuits can be perfectly matched.
At the same time, the number of switch circuit driving gate lines crossing the video signal line is reduced, so that the yield is improved and the load of an external circuit for writing the video signal on the video signal line can be reduced.
When the wiring width of the video signal line is WV, the distance between the wirings is SV, and the pattern pitch in the Y direction of the switch circuit is D, D
= WV + SV, the distance between the video signal line and the switch circuit can be easily made equal, so that the variation in the wiring length of the lead-out wiring can be suppressed, and the writing characteristic of the video signal to the data line is improved, and at the same time in the design stage. Efficiency can also be improved. Furthermore, since the combination when connecting the video signal line and the switch circuit is optimized, it is possible to minimize the variation in the distance of the lead wiring. In addition, by appropriately setting the size of the switch circuit and the space of the video signal line, it is possible to make the distance between the switch circuit and the video signal line all the same. Also,
Since the lead wire length and the lead wire width are almost the same for all lead wires, it is possible to keep the lead wire resistance constant within the circuit even if the wire shape changes due to manufacturing process variations or process changes. It is possible to prevent variations in output signals. On the other hand, since the material of the lead-out wiring is a high melting point metal, the resistance value of the lead-out wiring can be made very small. As a result, the distance between the video signal lines can be widened, and as a result, the wiring capacitance between the video signal lines can be reduced and the writing characteristics of the video signal can be improved.

Since the liquid crystal display device of the present invention comprises a driving circuit using thin film transistors that can handle a fine pitch, it can be made compact and high definition. In particular, since the switch circuit can be miniaturized, it is possible to colorize with the same size of the liquid crystal display device. Since the three switch circuits that write the R, G, and B video signals to the data lines share the switch circuit driving gate line, the write timings of these three primary colors are completely the same, and there is uneven color. It is possible to obtain good display characteristics. Further, since the thin film transistor circuit in which the shape of the lead-out wiring is not influenced by the manufacturing process is used, it is possible to obtain good display quality in which there is no unevenness in brightness for each data line. Furthermore, since the refractory metal is used for the lead-out wiring and the inter-wiring capacitance of the video signal line is reduced, the load on the external circuit for inputting the video signal to the liquid crystal display device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device.

FIG. 2 is a diagram showing a layout of a video signal line peripheral portion of the data line driving circuit of FIG. 1 on a substrate.

3 is a cross-sectional view of the switch circuit of FIG.

FIG. 4 is a diagram showing a layout of a video signal line peripheral portion of a conventional data line driving circuit on a substrate.

FIG. 5 is a diagram showing a layout on a substrate of a peripheral portion of a video signal line of a conventional data line driving circuit.

FIG. 6 is a diagram showing a layout of a video signal line peripheral portion of a data line driving circuit using a thin film transistor of the present invention on a substrate.

FIG. 7 is a diagram showing a layout on a substrate of a peripheral portion of a video signal line of a data line driving circuit using a thin film transistor of the present invention.

FIG. 8 is a diagram showing a layout on a substrate of a peripheral portion of a video signal line of a data line driving circuit using a thin film transistor of the present invention.

FIG. 9 is a diagram showing a layout on a substrate of a video signal line peripheral portion of a data line driving circuit using a thin film transistor of the present invention.

[Explanation of symbols]

11 ... Transparent substrate 12 ... Data line drive circuit 21 ... Scan line drive circuit 22 ... Pixel matrix V1, V2, V3, V4, V5, V6 ... Video signal line SW1, SW2, SW3 , SW4, SW5, SW6 ...
Switch circuit S1, S2, S3, S4, S5, S6 ... Lead wiring P1, P2, P3 ... Pixel matrix X1, X2, X3, X4, X5, X6 ... Data lines Y1, Y2, Y3 ... Scanning lines G1, G2, G3, G4, G5, G6, G123, G4
56 ... Switch circuit driving gate line 1 ... Semiconductor layer (including P region and N region) 2 ... Liquid crystal cell 3 ... Storage capacitor 4 ... Pixel transistor 5 ... Contact hole 6・ ・ ・ Drain side wiring of switch circuit 7 ・ ・ ・ Source side wiring of switch circuit 8 ・ ・ ・ Gate insulating film 9 ・ ・ ・ Interlayer insulating film G1P, G2P, G3P ・ ・ ・ P channel driving gate line of switch circuit G1N, G2N, G3N ... Gate line for driving N channel of switch circuit D ... Pattern pitch in Y direction between adjacent switch circuits W ... Channel width of switch circuit WV ... Wiring of video signal line Width SV: Distance between wires of video signal lines LS: Wire length of lead wires

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/786

Claims (44)

[Claims] 1. In a thin film transistor circuit formed between a pixel matrix region on the same substrate and an outer peripheral edge of the substrate, a data line driving circuit has a side direction (X) of the outer peripheral edge.
Direction)) and video signal lines parallel to each other from the outer peripheral side of the data line drive circuit toward the pixel matrix formation region side direction (Y direction), and an interlayer insulating film for each of these video signal lines. Are electrically connected to each other, and are connected between the video signal lines toward the pixel matrix forming region side, and each of these extraction lines and each data line corresponding to each of the extraction lines, and drive timing control is performed. A switch circuit whose operation is switched to a conductive connection state and a non-conductive connection state between the lead wiring and the data line according to a drive timing signal output from the drive circuit, and from the drive timing control section to the switch circuit section. The drive timing signal is formed and intersects the video signal line through an interlayer insulating film, and the drive timing signal is transmitted to the switch circuit. And a switching circuit for driving the gate lines to be input to, those adjacent the switching circuit,
A thin film transistor circuit, which is separated in the Y direction by a channel width of the switch circuit or more. 2. In a thin film transistor circuit formed between a pixel matrix region on the same substrate and an outer peripheral edge of the substrate, a data line driving circuit has a peripheral direction (X) of the outer peripheral edge.
Direction)) and video signal lines parallel to each other from the outer peripheral side of the data line drive circuit toward the pixel matrix formation region side direction (Y direction), and an interlayer insulating film for each of these video signal lines. Are electrically connected to each other, and are connected between the video signal lines toward the pixel matrix forming region side, and each of these extraction lines and each data line corresponding to each of the extraction lines, and drive timing control is performed. A switch circuit whose operation is switched to a conductive connection state and a non-conductive connection state between the lead wiring and the data line according to a drive timing signal output from the drive circuit, and from the drive timing control section to the switch circuit section. The drive timing signal is formed and intersects the video signal line through an interlayer insulating film, and the drive timing signal is transmitted to the switch circuit. A thin film transistor circuit, characterized in a switch circuit driving gate lines for inputting, a plurality of the switching circuits share the switching circuit for driving a gate line. 3. In a thin film transistor circuit formed between a pixel matrix region on the same substrate and an outer peripheral edge of the substrate, a data line driving circuit has a peripheral direction (X) of the outer peripheral edge.
Direction)) and video signal lines parallel to each other from the outer peripheral side of the data line drive circuit toward the pixel matrix formation region side direction (Y direction), and an interlayer insulating film for each of these video signal lines. Are electrically connected to each other, and are connected between the video signal lines toward the pixel matrix forming region side, and each of these extraction lines and each data line corresponding to each of the extraction lines, and drive timing control is performed. A switch circuit whose operation is switched to a conductive connection state and a non-conductive connection state between the lead wiring and the data line according to a drive timing signal output from the drive circuit, and from the drive timing control section to the switch circuit section. The drive timing signal is formed and intersects the video signal line through an interlayer insulating film, and the drive timing signal is transmitted to the switch circuit. And a switch circuit driving gate line for inputting to the switch circuit, and by arranging the adjacent switch circuits (m is a positive integer) in the Y direction at a distance greater than or equal to the channel width thereof, a fixed layout pattern is formed. A thin film transistor circuit is characterized in that the m switch circuits share a switch circuit driving gate line. 4. When adjacent ones of the switch circuits are arranged with a pitch D in the Y direction, the width of the video signal lines is WV, and the distance between the video signal lines is SV, D = WV + SV 2. The method according to claim 1, wherein
The thin film transistor circuit described. 5. When adjacent ones of the switch circuits are arranged with a pitch D in the Y direction, the width of the video signal lines is WV, and the distance between the video signal lines is SV, D = WV + SV 3. The method according to claim 2, wherein
The thin film transistor circuit described. 6. When adjacent ones of the switch circuits are arranged at intervals of a pitch D in the Y direction, the width of the video signal lines is WV, and the distance between the video signal lines is SV, D = WV + SV 4. The method according to claim 3, wherein
The thin film transistor circuit described. 7. The number of the video signal lines is m × n (m,
n is a positive integer), and the adjacent switch circuits m
When a certain layout pattern is formed by arranging the pieces in the Y direction so as to be separated from each other by the channel width or more, the video signal lines connected to the m switch circuits through the lead wiring are the Y direction. 2. The thin film transistor circuit according to claim 1, wherein there is an interval of 1 in n in m × n video signal lines arranged in parallel. 8. The number of the video signal lines is m × n (m,
n is a positive integer), and the adjacent switch circuits m
When a certain layout pattern is formed by arranging the pieces in the Y direction so as to be separated from each other by the channel width or more, the video signal lines connected to the m switch circuits through the lead wiring are the Y direction. 3. The thin film transistor circuit according to claim 2, wherein there is an interval of 1 in n in m × n video signal lines arranged in parallel. 9. The number of the video signal lines is m × n (m,
n is a positive integer), and the adjacent switch circuits m
When a certain layout pattern is formed by arranging the pieces in the Y direction so as to be separated from each other by the channel width or more, the video signal lines connected to the m switch circuits through the lead wiring are the Y direction. 4. The thin film transistor circuit according to claim 3, wherein there is an interval of 1 in n in m × n video signal lines arranged in parallel. 10. When the wiring length of the lead-out wiring is defined by the distance between each of the video signal line and the switch circuit and the contact hole where the lead-out wiring is conductively connected, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 2. The thin film transistor circuit according to claim 1, wherein the thin film transistor circuits have the same value. 11. When the wiring length of the lead-out wiring is defined by the distance between each of the video signal line and the switch circuit and the contact hole through which the lead-out wiring is conductively connected, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 3. The thin film transistor circuit according to claim 2, wherein the thin film transistor circuits have the same value. 12. When the wiring length of the lead-out wiring is defined by the distance between each of the video signal line and the switch circuit and the contact hole for conductively connecting the lead-out wiring, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 4. The thin film transistor circuit according to claim 3, wherein the thin film transistor circuits have the same value. 13. When the wiring length of the lead-out wiring is defined as the distance between the video signal line and the switch circuit and the contact hole for conductive connection of the lead-out wiring, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 5. The thin film transistor circuit according to claim 4, wherein the thin film transistor circuits have the same value. 14. When the wiring length of the lead-out wiring is defined by the distance between the video signal line and the switch circuit and the contact hole where the lead-out wiring is conductively connected, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 6. The thin film transistor circuit according to claim 5, wherein the thin film transistor circuits have the same value. 15. When the wiring length of the lead-out wiring is defined by the distance between each of the video signal line and the switch circuit and the contact hole through which the lead-out wiring is conductively connected, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 7. The thin film transistor circuit according to claim 6, wherein the thin film transistor circuits are equal. 16. When the wiring length of the lead-out wiring is defined by the distance between the video signal line and the switch circuit and the contact hole for conductively connecting the lead-out wiring, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 8. The thin film transistor circuit according to claim 7, wherein the thin film transistor circuits have the same value. 17. When the wiring length of the lead-out wiring is defined by the distance between the video signal line and the switch circuit and the contact hole through which the lead-out wiring is conductively connected, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 9. The thin film transistor circuit according to claim 8, wherein the thin film transistor circuits have the same value. 18. When the wiring length of the lead-out wiring is defined by the distance between each of the video signal line and the switch circuit and the contact hole through which the lead-out wiring is conductively connected, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 10. The thin film transistor circuit according to claim 9, wherein the thin film transistor circuits have the same value. 19. The thin film transistor circuit according to claim 1, wherein a wiring material of the lead wiring is a refractory metal. 20. The thin film transistor circuit according to claim 2, wherein the wiring material of the lead wiring is a refractory metal. 21. The thin film transistor circuit according to claim 3, wherein the wiring material of the lead wiring is a refractory metal. 22. The thin film transistor circuit according to claim 4, wherein the wiring material of the lead wiring is a refractory metal. 23. The thin film transistor circuit according to claim 5, wherein the wiring material of the lead wiring is a refractory metal. 24. The thin film transistor circuit according to claim 6, wherein a wiring material of the lead wiring is a refractory metal. 25. The thin film transistor circuit according to claim 7, wherein the wiring material of the lead wiring is a refractory metal. 26. The thin film transistor circuit according to claim 8, wherein the wiring material of the lead wiring is a refractory metal. 27. The thin film transistor circuit according to claim 9, wherein the wiring material of the lead wiring is a refractory metal. 28. The thin film transistor circuit according to claim 10, wherein a wiring material of the lead wiring is a refractory metal. 29. The thin film transistor circuit according to claim 11, wherein a wiring material of the lead wiring is a refractory metal. 30. The thin film transistor circuit according to claim 12, wherein the wiring material of the lead wiring is a refractory metal. 31. The thin film transistor circuit according to claim 13, wherein the wiring material of the lead wiring is a refractory metal. 32. The thin film transistor circuit according to claim 14, wherein the wiring material of the lead wiring is a refractory metal. 33. The thin film transistor circuit according to claim 15, wherein a wiring material of the lead wiring is a refractory metal. 34. The thin film transistor circuit according to claim 16, wherein a wiring material of the lead wiring is a refractory metal. 35. The thin film transistor circuit according to claim 17, wherein the wiring material of the lead wiring is a refractory metal. 36. The thin film transistor circuit according to claim 18, wherein the wiring material of the lead wiring is a refractory metal. 37. In a liquid crystal display device having a thin film transistor circuit formed between a pixel matrix region on the same substrate and an outer peripheral edge of the substrate, a data line driving circuit is provided in a side direction (X direction) of the outer peripheral edge. Image signal lines that are formed in parallel with each other from the outer peripheral edge side of the data line drive circuit toward the pixel matrix formation region side direction (Y direction), and conductive connection is made for each of these image signal lines through an interlayer insulating film. Then, it is inserted between the lead-out wiring extending from the video signal line toward the pixel matrix forming region side, each lead-out wiring and each data line corresponding to each of the lead-out wirings, and output from the drive timing control unit. The operation is switched between a conductive connection state and a non-conductive connection state of the lead wire and the data line according to the generated drive timing signal. A switch circuit and a switch circuit formed from the drive timing control unit toward the switch circuit unit and intersecting the video signal line through an interlayer insulating film and inputting the drive timing signal to the switch circuit unit. A liquid crystal display device having a driving gate line, wherein adjacent ones of the switch circuits are separated from each other by at least a channel width of the switch circuits in the Y direction. 38. When the number of the video signal lines is 3 × n (n is a positive integer), three switch circuits are arranged apart from each other by at least their channel width in the Y direction, and these three switch circuits are provided. 38. The liquid crystal display device according to claim 37, wherein the switch circuits of the above share a switch circuit driving gate line. 39. When the wiring length of the lead-out wiring is defined by the distance between each of the video signal line and the switch circuit and the contact hole through which the lead-out wiring is conductively connected, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 38. The liquid crystal display device according to claim 37, wherein the liquid crystal display device has the same value. 40. When the wiring length of the lead-out wiring is defined by the distance between each of the video signal line and the switch circuit and the contact hole for conductively connecting the lead-out wiring, the lead-out wiring has a wiring length and a wiring width of all the lead-out wirings. 39. The liquid crystal display device according to claim 38, wherein the liquid crystal display devices have the same value. 41. The liquid crystal display device according to claim 37, wherein a wiring material of the lead wiring is a refractory metal. 42. The liquid crystal display device according to claim 38, wherein the wiring material of the lead wiring is a refractory metal. 43. The liquid crystal display device according to claim 39, wherein a wiring material of the lead wiring is a refractory metal. 44. The liquid crystal display device according to claim 40, wherein the wiring material of the lead wiring is a refractory metal.