JPH0729384A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase a storage capacity without accompanying the increase of the number of memory cells or the expansion of the size of a semiconductor chip. CONSTITUTION:A data reading out/encoding circuit 13 capable of reading out the information corresponding to plural bits from one memory cell by discriminating the depth of the level writing into one memory cell MS, and a data comparison circuit 14 are provided in the device. By validating the write-in of the multiple bits information to one memory cell, the storage capacity is increased without accompanying the increase of the number of memory cells or the expansion of the size of semiconductor chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for enlarging a memory capacity in the semiconductor memory device, for example, a technique effectively applied to a flash memory.

[0002]

2. Description of the Related Art DRAMs (Dynamic Random Access Memory), SRAMs are used as semiconductor memory devices.
(Static random access memory), mask ROM (read only memory), PROM (programmable read only memory) and the like can be mentioned. DRAM can be electrically programmed, erased, and
It is a readable volatile memory and requires a memory holding operation. The SRAM is a volatile memory that can be electrically written, erased, and read at any time, and does not require a memory holding operation. The mask ROM is a memory in which a program (data writing) is performed in the manufacturing process (photomask), and is a nonvolatile read-only memory. A PROM is a read-only non-volatile memory that is electrically writable by the user and is UV or electrically erasable.

Further, Japanese Patent Application Laid-Open No. 2-289997 discloses a batch erase type EEPROM (electrically eraseable.
And programmable read only memory). This batch erase type EEPROM
Can be understood to have the same meaning as the flash memory in this specification. The flash memory can rewrite information by electrically erasing / writing,
Like M, the memory cell can be configured by one transistor, and has a function of electrically erasing all of the memory cells or a block of memory cells at once. Therefore, the flash memory can rewrite the stored information in the state where it is mounted in the system, and the batch erasing function can shorten the rewriting time, and further contributes to the reduction of the chip occupying area. To do.

In each of the above memories, each memory cell has a binary value (1 bit) of "0" and "1".
Designed to store information, for example, 1
Eight memory cells are required to store byte (8-bit) information.

[0005]

As described above, in the prior art, in order to increase the storage capacity, the number of memory cells is reduced by reducing the size of the memory cell itself or increasing the size of the semiconductor chip. Need to increase. As a result of a study by the present inventor on that, it is necessary to develop a new fine processing technology in order to significantly reduce the size of the memory cell, and to increase the semiconductor chip area means that the system to which it is applied is increased. It was found that not only hindering downsizing, but also lowering of yield may lead to cost increase.

An object of the present invention is to increase the number of memory cells,
An object of the present invention is to provide a technique for increasing the storage capacity without increasing the size of the semiconductor chip.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the semiconductor memory device is provided with a data read system capable of reading information corresponding to a plurality of bits from one memory cell by discriminating the depth of the write level to one memory cell.

[0010]

According to the above-mentioned means, the data read system operates so as to read a plurality of bits of information from one memory cell by discriminating the depth of the write level to one memory cell, This makes writing of multi-bit information into one memory cell effective, and increases the storage capacity without increasing the number of memory cells or expanding the size of the semiconductor chip.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a flash memory which is an embodiment of the present invention.

Although not particularly limited, the flash memory shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit.

In FIG. 1, 10 is a plurality of memory cells M.
S is a memory cell array in which S is arranged in a matrix, and this memory cell array 10 is capable of rewriting information by electrical erasing / writing, and one memory cell is formed by one transistor like an EPROM. Composed. Further, it has a function of electrically erasing a plurality of memory cells MS collectively. In the memory cells MS arranged in a matrix in the X and Y directions, the control gates (selection gates of the memory cells) of the storage transistors arranged in the same row are respectively associated with the corresponding word line W.
The drain regions (memory cell input / output nodes) of the storage transistors connected to 0 to W3 and arranged in the same column are
It is connected to the corresponding data lines D11 to D14. The source regions of the memory transistors forming the memory cell are coupled to the corresponding source lines S11 to S14. The plurality of data lines D11 to D14 and the source lines S11 to D14 correspond to the corresponding column selection switches 16 to.
Via 23, they are coupled to the common data line D and the common source line S, respectively. Column selection switch 16-2
The operation of No. 3 is controlled by column control signals D0 to D3 from the address decoder 11 which will be described later. That is, one of the column control signals D0 to D3 is selectively set to the high level, so that one set of the data line and the source line among the data lines D11 to D14 and the source lines S11 to S14 is selectively made common. It is adapted to be connected to the data line D and the common source line S.

Reference numeral 11 is an input address signal A0-A3.
The address decoder 11 is a row decoder for selecting the word lines W0 to W3, and column selection switches 16 to 23.
It includes a column decoder for switch control. As will be described later, the address signals A0 and A1 are handled as row addresses and are decoded to generate a word line selection signal. Also, address signals A2 and A
3 is treated as a column address, and by decoding it, the selection signals (D0 to D3) of the column selection switches 16 to 23 are generated.

Reference numeral 12 is a data write / erase circuit. This data write / erase circuit 12 has a common data line D,
Via the common source line S, the plurality of memory cells MS
Writing data to and erasing written data. A write / erase execution instruction signal WES and a write / erase selection signal W / E * are input to the data write / erase circuit 12. Write / erase selection signal W / E
When * is at high level, programming is selected, and when programming / erase selection signal W / E * is at low level, erasing is selected. Writing and erasing are enabled by applying a predetermined voltage to the memory cell, and the application timing of such voltage is controlled by the write / erase execution command signal WES.

Reference numeral 13 is a data reading / encoding circuit,
The data reading / encoding circuit 13 has a function of taking output data of the memory cell through the common data line D and the common source line S and encoding the output data into 2-bit data. Normally, the data stored in one memory cell is
Although it is 1-bit information of 0 "" 1 ", in the present embodiment, the memory cell MS increases the storage capacity without increasing the number of memory cells or expanding the size of the semiconductor chip, and therefore, one memory Information corresponding to 2 bits is written in the cell, and the data reading / encoding circuit 13
By accurately discriminating such information based on a plurality of logic threshold values and encoding it, writing of 2-bit equivalent information to one memory cell is effective. The read data encoded by the data read / encode circuit 13 is DR (R0, R1).

Reference numeral 14 denotes a data comparison circuit. This data comparison circuit 14 checks 2-bit data W0 to be written in the memory cell array 10 in order to check whether the data has been written correctly in the data writing to the memory cell array 10. , W1 and the 2-bit read data R0, R1 are compared. Here, the read data R0 and R1 are the data written to the memory cell immediately before the read, and if written correctly, the write data W0 and W1.
And the read data R0 and R1 match. The comparison result of the data comparison circuit 14 is the comparison signals W = R, W> R,
W <R, which is synchronized with the assert timing of the compare signal CMP from the control circuit 15,
It is adapted to be transmitted to the control circuit 15.

The control circuit 15 includes the data comparison circuit 14 described above.
The operations of the address decoder 11, the data write / erase circuit 12, and the data read / encode circuit 13 are controlled based on the comparison result of 1. From the outside of the memory of this embodiment,
Write command signal WRS * (* indicates low active or signal inversion), clock CLK, read command signal RDS
* Is input, and the operation of each part is controlled based on such various control signals.

FIG. 2 shows the structure of the memory cell MS.

The stack type flash memory cell has a two-layer structure of a floating gate and a control gate, and is a one-transistor type cell which is almost the same as an EPROM. Writing is performed by applying a high voltage to the control gate and drain and injecting hot electrons generated in the vicinity of the drain junction into the floating gate, as in the EPROM. For erasing, as shown in FIG. 3, a high voltage (Vpp = 12V) is applied to the source, the control gate is grounded to 0V (usually equivalent to the low-level side power supply Vss), and tunneling causes It is realized by extracting electrons in the floating gate to the source. When electrons are extracted from the floating gate, the threshold Vth seen from the control gate becomes low. Such a structure makes it possible to hold different logical states, which can be used to write multi-bit information.

FIG. 4 shows a structural example of the address decoder 11.

As shown in FIG. 4, the address decoder 11 for decoding the fetched address signal includes
A row address decoder 11A for decoding A0 and A1 of the address signals A0 to A3 and A2 and A3
Column address decoder 11B for decoding

The row address decoder 11A is constructed as follows.

Inverters 31 and 3 for obtaining complementary levels by inverting addresses A0 and A1, respectively.
2 is provided, and two-input AND circuits 33, 34, 35, 36 for obtaining those AND logics are provided. The outputs of the AND circuits 33 to 36 are coupled to the word lines via the n-channel MOS transistors 41 to 44, respectively. n-channel MOS transistor 41
˜44 are turned on when the read command signal RDS is asserted to the high level. Since the high-level power supply Vdd is supplied to the AND circuits 33 to 36, the high level at the time of driving the word line at the time of reading is equal to the power supply voltage Vdd.

An n-channel type MOS transistor 45 whose operation is controlled by the write depth signal WDP,
An n-channel type MOS transistor 46 whose operation is controlled by the write / erase selection signal W / E * is provided, and the write depth signal WDP and the write / erase selection signal W / E are provided.
When * is high level, the high voltage Vpp is taken in. Write / erase execution instruction signal WES,
AND circuits 37 to 40 for obtaining AND logic with the logic outputs of the AND circuits 33 to 36 are provided, and n channel type MOS is provided by the logic outputs of the AND circuits 37 to 40.
The operations of the transistors 49 to 52 are controlled. That is, in the state where the write / erase execution command signal WES is asserted to the high level, one of the AND circuits 37 to 40 is set to the high level output according to the AND logic according to the address, and the n channel corresponding thereto is output. The high voltage Vpp is supplied to the word line by turning on the MOS transistors 49 to 52. Further, an n-channel type MOS transistor 48 coupled to the low level power supply Vss and a write / erase selection signal W /
An inverter 47 is provided for inverting E * and transmitting it to the gate electrode of the n-channel MOS transistor 48, and the n-channel MOS transistors 46 and 48 are complementary to each other in response to the write / erase selection signal W / E *. It is designed to be activated.

Further, the column address decoder 11B
Is composed of inverters 53 and 54 for obtaining complementary levels by inverting addresses A2 and A3, and 2-input AND circuits 55 to 58 for obtaining AND logics thereof. The logical output is column selection switches 16 to 2 as column selection signals.
3 is transmitted.

FIG. 5 shows a configuration example of the data reading / encoding circuit 13.

As shown in FIG. 5, the data reading / encoding circuit 13 includes a sense amplifier 13A for reading data and an encoding circuit 1 for encoding its output.
3B and.

Although not particularly limited, the sense amplifier 13A has a circuit configuration of a current sensing system, and includes p-channel type MOS transistors 61 and 62 and an n-channel type MOS.
Transistors 63, 64, 65, 66 are combined. The p-channel type MOS transistors 61 and 62 are coupled to the high-level side power source Vdd, and n-channel type M
The OS transistors 63, 64, 66 are the low level power supply V
bound to ss. Read command signal RDS is applied to the gate electrodes of the p-channel type MOS transistors 61, 63 and 66.
* Is supplied, and when the read command signal RDS * is asserted to a low level, the p-channel type MOS transistor 61 is turned on and the n-channel type MOS transistors 63 and 66 are turned off. Thus, the sensed state of the memory cell data is set. That is, the current flowing through the n-channel MOS transistors 64 and 65 is determined according to the read level from the memory cell, and the voltage level of the output node D of the sense amplifier 13A is determined. The voltage level of the output node D is transmitted to the encoding circuit 13B at the subsequent stage for encoding. Then, the read command signal RDS *
Is negated to a high level, the p-channel MOS transistor 61 is turned off, and the n-channel MOS transistors 63 and 66 are turned on, so that the n-channel MOS transistor 65 is turned off. The sense amplifier is set to the non-sense state.

The encoding circuit 13B is constructed as follows.

Three inverters 67, 68, 69 having logical thresholds different from each other are provided, and a 2-input NOR circuit 70, an exclusive OR circuit 71, and a 2-input NOR circuit 72 are arranged in the subsequent stage. When the logical threshold values of the inverters 67 to 69 are represented by Vth1, Vth2 and Vth3,
The output logic of inverters 69 to 67 is inverted according to the voltage level of output node D of sense amplifier 13A. For example, the voltage level of the output node D of the sense amplifier 13A and the logical threshold values Vth1 and Vth of the inverters 69 to 67 are
When th2 and Vth3 are set to have a relationship as shown in FIG. 6, 2-bit information can be obtained from one memory cell. That is, when the voltage level of the output node D is lower than the logic threshold value Vth1 of the inverter 67, it is set to 0. When the voltage level of the output node D exceeds the logic threshold value Vth1 and is less than or equal to the logic threshold value Vth2, it is set to 1, and the voltage level of the output node D exceeds the logic threshold value Vth2 and the logic level. When it is less than or equal to the threshold value Vth3, it is set to 2, and when the voltage level of the output node D exceeds the logical threshold value Vth3, it is set to 3.

FIG. 7 shows a truth table of the encoding circuit 13B.

As shown in FIG. 7, nodes A, B, C
Read data R0 having a 2-bit configuration according to the logical state of
R1 is determined. According to this truth table, the stored data of one memory cell and the outputs A of the inverters 67 to 69,
The relationship between B and C and the encoded outputs R0 and R1 is clarified.

FIG. 8 shows a configuration example of the data comparison circuit 14.

The data comparison circuit 14 compares the write data DW (W0, W1) with the read data DR (R0, R1) as 2-bit data, although not particularly limited thereto. As the comparison result, when DW = DR, the comparison signal W = R is asserted to the high level, and when DW> DR, the comparison signal W> R is asserted to the high level, and the DW
When <DR, the comparison signal W <R is asserted to the high level. In order to realize such a logic, the read data D
Inverters 81 and 82 for inverting R to form a complementary level signal and inverters 83 and 84 for inverting the write data DW to form a complementary level signal are provided. Exclusive-OR circuits 85 and 86 for comparison, 3-input NOR circuit 89, 2-input AND circuit 88, 3-input NOR circuit 9
A 0-, 4-input NOR circuit 91, a 2-input NOR circuit 87, a 3-input OR circuit 92, and a 2-input NOR circuit 93 are provided. Then, the compare signal CM from the control circuit 15
Clocked inverters 94, 9 controlled by P
5, 96 are provided. An inverter 97 is provided in order to generate complementary level control signals for operating the clocked inverters 94, 95 and 96. By holding the comparison signal in the clocked inverters 94 to 96 in synchronization with the timing when the compare signal CMP is asserted to the high level, the comparison signal can be transmitted to the subsequent circuit, that is, the control circuit 15. It
FIG. 9 shows a truth table of the data comparison circuit 14.

FIG. 10 shows a configuration example of the data write / erase circuit 12.

An n-channel type MOS transistor 101 connected to the common data line D and an n-channel type MOS transistor 102 connected to the common data line S are provided. An n-channel MOS transistor 105 is coupled to the n-channel MOS transistor 101, and an n-channel MOS transistor 102 is connected to an n-channel MOS transistor 102.
Channel type MOS transistors 103 and 104 are coupled. The high voltage Vpp is applied to the n-channel MOS transistor 103, the low-level power supply Vss is coupled to the n-channel MOS transistor 104, and the high-level power supply Vdd is coupled to the n-channel MOS transistor 105. Further, a write / erase selection signal W
An inverter 106 for inverting / E * is provided,
The inverted output of the inverter 106 is an n-channel MO
It is adapted to be transmitted to the gate electrode of the S transistor 103. In such a configuration, when the write / erase selection signal W / E * is at the high level and the write / erase execution command signal WES is at the high level, the n-channel type MOS transistors 102 and 104 are turned on. Causes the common data line S to have the low-level power supply Vss.
It is a level. At this time, the n-channel MOS transistors 101 and 105 are turned on, so that the high-level power supply Vdd for writing data to the memory cell is applied to the common data line D. On the other hand, when the write / erase selection signal W / E * is at the low level and the write / erase execution command signal WES is at the high level, the n-channel MOS transistor 104 is turned off and the n-channel MOS transistor 104 is turned off. The high voltage Vpp for erasing the memory cell data is applied to the common data line S by turning on the MOS transistor 103.

FIG. 13 shows a configuration example of the control circuit 15.

As shown in FIG. 3, an inverter 117 for inverting the comparison signal W> R and an inverter 118 for inverting its output are provided, and the output of this inverter 118 is a write / erase selection signal. W / E *. A two-input OR circuit 120 for obtaining an OR logic between the comparison signals W> R and W <R is provided.
An AND circuit 121 for obtaining an AND logic of the logic output of 20 and the clock CLK is provided.
21 and an AND circuit 119 for obtaining the AND logic of the comparison signal W> R are provided, and the logical output of the AND circuit 119 is a write depth for controlling the depth of data write to the memory cell MS. The signal is WDP. Also,
The AND logic between the inverted signal of the read command signal RDS * and the clock CLK is obtained by the AND circuit 122, which is used as the compare signal CMP for regulating the comparison output timing in the data comparison circuit 14. Furthermore, the OR logic of the write command signal WRS and the comparison signal W = R is obtained by the OR circuit 123, and this is used as the write end signal WED for indicating the end of writing to the outside of the memory.

Next, the operation of the embodiment circuit having the above configuration will be described.

FIG. 14 shows the timing for reading data.

An external read command signal RDS * is asserted to a low level, and the input address signal is decoded by the address decoder 11, whereby one of the word lines W0 to W3 is selected at a selected level. Driven to. When one of the column selection signals D0 to D3 is driven to the selection level, the pair of data lines corresponding to the address is selectively coupled to the common data lines D and S. As a result, the storage data (memory cell data) of one memory cell MS is transmitted to the data reading / encoding circuit 13. When the memory cell data is input to the sense amplifier 13A in the data read / encoding circuit 13, a voltage level corresponding to the memory cell data appears at the node D, which is the 2-bit data DR (R0, R1 in the subsequent encoding circuit 13B. ) Is encoded. The encoded 2-bit data can be externally output via a buffer (not shown). In the present embodiment, as shown in FIG. 14, one cycle of reading is performed in two cycles of the clock CLK.

FIG. 15 shows the timing for writing / erasing data. One data write / erase operation is completed in three cycles (T1, T2, T3).

In this embodiment, since 2-bit information can be written to one memory cell, data is read from the memory cell related to the write even in the write cycle, and the read data and the write data are written. The write state is optimized by comparing the above.

The write command signal WRS * and the read command signal RDS * are asserted to the low level, and the read data DR from the data read / encoding circuit 13 and the write data DW are compared. In this data comparison,
When the write data DW is larger than the read data DR, the comparison signal W> R is asserted to the high level, thereby setting the write / erase selection signal W / E * to the high level and executing the write / erase. At the timing when the command signal WES is asserted to the high level, the data write / erase circuit 12 causes the high-level power supply Vd for writing.
d is applied to the memory cell MS in the selected state. FIG. 11 shows an equivalent circuit at the time of writing this data. As shown in the figure, at the time of writing data, the control circuit 1
5, write depth signal WDP, write command signal W
When RS is asserted to the high level, the n-channel type MOS transistors 107 and 108 are turned on, and the high voltage Vpp is applied to the gate electrode of the memory cell MS. In addition, the n-channel type MOS transistor 10
By turning on 9, 110, the drain line D is coupled to the high level side power source Vdd, and the source line S is coupled to the low level side power source Vss. In this state, writing to the memory cell MS is enabled.

In the comparison of the data comparison circuit 14, when the write data DW is smaller than the read data DR, it means that the write is overwritten in level, and therefore the comparison signal W <R is asserted to the high level. As a result, the write / erase selection signal W / E * is set to the low level and the high voltage Vpp is applied to the source line S at the timing when the write / erase execution command signal WES is asserted to the high level.
Is applied to erase the memory cell data. FIG. 12 shows an equivalent circuit at the time of erasing this data. By asserting ERS to a low level, the n-channel type MOS transistor 115,
When the high voltage Vpp is applied to the source of the memory cell MS and the control gate is set to the low level power supply Vss level, the memory cell data can be erased.

In the data reading / encoding circuit 13,
When it is determined that the write data DW and the read data DR are equal, the comparison signal W = R is asserted to the high level. Then, the control circuit 15 indicates the completion of writing to the external device by asserting the write end signal WED at a high level. In this cycle,
Since the write / erase execution instruction signal WES is not asserted to the high level, neither writing nor erasing is performed.

According to the above embodiment, the following operational effects can be obtained.

Since information corresponding to 2 bits can be read from one memory cell MS, "0" is obtained as compared with the prior art in which 1 bit information of "0" or "1" is stored per memory cell. Since it is possible to read 2-bit information that can indicate the values of "1", "2", and "3", it is possible to increase the storage capacity without increasing the number of memory cells and the size expansion of the semiconductor chip. . In other words,
Since information equivalent to 2 bits can be read from one memory cell, the number of memory cells can be reduced to 1 /
It can be reduced to 2, and the chip size can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

FIG. 16 shows another example of the structure of the read / encode circuit 13.

As described above, in the flash memory cell MS, the threshold value Vth seen from the control gate differs depending on the amount of electrons in the floating gate. Also,
Even if the word line voltage is the same, the current value at the time of reading differs depending on the threshold value Vth of the memory cell MS. By using this, for example, as shown in FIG. 16, if the capacitor C of the data line D1 is charged by driving the word line W1 for a predetermined time, the difference in the threshold Vth is It appears as a difference in cell current and further as a difference in potential generated in the capacitor C. Therefore, if this potential is encoded by the encoding circuit 13B in the subsequent stage, it is possible to obtain information of 2 bits or more from one memory cell MS, as in the case of the above-mentioned embodiment. The same effect as in the case of can be obtained. The coding circuit in this case may have the same configuration as the coding circuit indicated by the same reference numeral in FIG.

FIG. 17 shows another configuration example of the read / encode circuit 13.

The inverting input terminal and the output terminal of the operational amplifier 125 are coupled by the negative feedback resistor 126, and the operational amplifier 1
The memory cell MS is coupled to the inverting input terminal of 25. Further, an operational amplifier 128 is coupled to the operational amplifier 125 via an input resistor 127. This operational amplifier 12
The inverting input terminal and the output terminal of 8 are connected by a negative feedback resistor 129. Further operational amplifiers 125 and 128
The non-inverting input terminal of is connected to the low level power supply Vss. As described above, the threshold Vth of the memory cell MS
Therefore, the current value at the time of reading is different, and by utilizing it, the multi-valued data is written to the memory cell MS. Then, the output current from the memory cell MS is converted into a voltage by the operational amplifier 125, amplified by the operational amplifier 128 in the subsequent stage, and then encoded by the encoding circuit 13B. The coding circuit 13B may have the same structure as the coding circuit indicated by the same reference numeral in FIG. Even with such a configuration, as in the case of the above-described embodiment, since information of 2 bits or more can be obtained from one memory cell MS, the same effect as that of the above-described embodiment can be obtained.

FIG. 18 shows another configuration example of the read / encode circuit 13.

Since the memory cell MS can be considered as a variable resistor having its threshold value Vth as a parameter, if a resistor 131 is provided in series with this memory cell MS, the resistance division leads to a node D. Since the voltage changes according to the output current of the memory cell MS, by encoding it by the encoding circuit 13B in the subsequent stage, as in the case of the above-described embodiment, information of 2 bits or more from one memory cell MS can be obtained. Therefore, it is possible to obtain the same effect as that of the above embodiment. Encoding circuit 13B in this case
Also, the same configuration as the encoding circuit shown by the same reference numeral in FIG. 5 can be applied.

Further, in the above embodiment, the information corresponding to 2 bits is written in one memory cell, but the information storage density can be further increased by writing the information corresponding to 3 bits or more.

Although the flash memory has been described in the above embodiments, the present invention can be applied to other semiconductor memory devices such as DRAMs.

As shown in FIG. 19, the memory cell M1 of the DRAM is composed of one MOS transistor M1 and a capacitor capacitance C1 connected in series to the MOS transistor M1, depending on whether or not electric charge is stored in the capacitor C1. Data storage is enabled. For data reading, as shown in FIG. 20, the data line D1 and the word line W1 are selected to specify the memory cell M1 as the data reading target.
The parasitic capacitance C2 of the data line D1 and the capacitance C1 of the memory cell
It is possible to obtain the potential of the data line D1 which changes according to the charge share current Ics. Such DRAM
The output level of the memory cell is different from that of the flash memory type cell depending on the depth of the write level. Therefore, the memory cell of FIG. The same effect as that of the embodiment can be obtained.

In the above description, the case where the invention made by the present inventor is mainly applied to a flash memory or a DRAM which is a field of application which is the background of the invention has been described, but the present invention is not limited thereto and a photomask is used. ROM that allows data to be written by
Alternatively, the present invention can be applied to various semiconductor memory devices such as a PROM electrically writable by a user, and further various semiconductor memory devices incorporated in a data processing device such as a single-chip microcomputer.

The present invention can be applied on the condition that it includes a memory cell that can be in at least three or more states.

[0062]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the data read system determines the depth of the write level to one memory cell, it is possible to read information corresponding to a plurality of bits from one memory cell. Since writing multi-bit information to a cell is effective, without increasing the number of memory cells or expanding the size of a semiconductor chip,
The storage capacity of the entire semiconductor memory device can be increased.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a flash memory that is an embodiment of the present invention.

FIG. 2 is a basic configuration explanatory diagram of a memory cell included in the flash memory.

FIG. 3 is an operation explanatory diagram of a memory cell included in the flash memory.

FIG. 4 is a circuit diagram of a configuration example of an address decoder included in the flash memory.

FIG. 5 is a configuration circuit diagram of a read / encoding circuit included in the flash memory.

FIG. 6 is an output voltage characteristic diagram of a sense amplifier included in the read / encode circuit.

FIG. 7 is an explanatory diagram of a truth table of a read / encode circuit included in the flash memory.

FIG. 8 is a configuration circuit diagram of a data comparison circuit included in the flash memory.

FIG. 9 is an explanatory diagram of input / output truth values of the data comparison circuit.

FIG. 10 is a configuration circuit diagram of a data write / erase circuit included in the flash memory.

FIG. 11 is an equivalent circuit at the time of writing data in the flash memory.

FIG. 12 is an equivalent circuit diagram when erasing data in the flash memory.

FIG. 13 is a configuration circuit diagram of a control circuit included in the flash memory.

FIG. 14 is a timing diagram when reading from the flash memory.

FIG. 15 is a timing diagram at the time of writing / erasing the flash memory.

FIG. 16 is another configuration block diagram of a read / encode circuit in the flash memory.

FIG. 17 is a block diagram of another configuration of the read / encode circuit in the flash memory.

FIG. 18 is a block diagram of another configuration of the read / encode circuit in the flash memory.

FIG. 19 is a configuration block diagram of a main part in a DRAM according to another embodiment of the present invention.

FIG. 20 is an explanatory diagram of a read operation of the DRAM.

[Explanation of symbols]

 10 memory cell array 11 address decoder 12 data write / erase circuit 13 data read / encode circuit 14 data comparison circuit 15 control circuit MS memory cell

Claims (3)

[Claims] 1. A semiconductor memory device including a plurality of memory cells for storing information, wherein information corresponding to a plurality of bits is read from one memory cell by determining the depth of a write level to one memory cell. A semiconductor memory device including a data read system that enables the above. 2. Comparing means for determining whether or not the data to be written in one memory cell has been correctly written in the memory, and controlling data writing in the memory cell based on the result of the determination. The semiconductor memory device according to claim 1, further comprising a write system. 3. The data reading system includes an encoding circuit for encoding memory cell data, and the comparing means compares the output value of the encoding means with the write data. 3. The semiconductor memory device according to claim 1 or 2, further comprising: