JPH0728877A - Register transfer level design supporting device - Google Patents

Abstract

PURPOSE:To provide a register transfer level design supporting device which an estimate with high accuracy an area of a circuit and an operating speed by adding a layout, and can design an outline of the layout simultaneously with the estimation, in a register transfer level of a circuit design by which a data path part and a control part of the circuit are designed as each independent block on the layout. CONSTITUTION:By plural pieces of library estimating means 10, a library is given, and by layout design system describing means 20a-20c, plural pieces of layout design systems being different from each other are given. Each of data path part performance estimating means 30a-30c estimates an area of a data path part of a circuit and an operating speed by using the library and the layout design system. A floor plant optimizing means 80 optimizes a block shape for considering both of the area of the whole circuit and the operating speed by comparing and studying plural pieces of block realizing methods being different from each other and a result of its estimation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register transfer level design support device for supporting circuit design at a register transfer level.

[0002]

2. Description of the Related Art In recent years, description using a hardware description language and graphics has come to be performed at the register transfer level of circuit design. What is commonly performed regarding these synthesizing methods is to clearly separate the data flow into a data path portion that handles data operations and a control portion that handles the processing order of the operations, and perform optimization. .

Since the data path unit is realized by a relatively regular repeating circuit, it is easy to predict and optimize the delay time between registers. On the other hand, the control part has strong randomness and is difficult to predict and optimize.
To implement a system including the data path unit and the control unit in the VLSI mask layout, there are the following two types of circuit design methods.

A circuit designing method in which the data path unit and the control unit are collectively realized in one block. A circuit designing method in which the data path unit and the control unit are treated as separate blocks in the layout. When the circuit size (the number of gates) of the data path part is not more than about 10 times as large as that of the control part, the circuit designing method is effective in terms of area minimization. In other cases, it is effective to use the circuit design method and apply a dedicated layout method to the data path section.

When the circuit designing method (1) is used, most of the area on the chip is occupied by the data path portion. Therefore, in estimating the chip area, the estimation of the data path portion is more important than the estimation of the control portion. However, it is necessary to realize both the control unit and the data path unit so as to satisfy the conditions in terms of timing.
Hereinafter, a conventional circuit design method and a conventional design support method at the register transfer level when the data path part and the control part of the circuit are designed as independent blocks in terms of layout will be described.

FIG. 8 is a flow chart showing the conventional circuit design method. As shown in FIG.
From the register transfer level design of 51, step S54
After the logic level design of step S57, the layout design of step S57 is performed, and the conceptual model of the circuit is sequentially converted from a highly abstract model to a concrete model.

First, in the register transfer level design in step S51, an arithmetic unit (hardware) is defined corresponding to each operation, and design data is transferred by the data transfer between registers and the sequence control section between them. Composed. Data transfer between the registers is collectively treated as a data path block. On the other hand, the control part is represented by a Finite State Machine. next,
In the logic level design of step S54, each block is expanded to a logic gate according to the detailed specifications defined by the register transfer level. A cell library is used to select an appropriate one from among them and to construct them by combining them. Then, in the layout design of step S57, the layout of each block, the wiring between the blocks, etc. are determined, and the mask pattern of the LSI is designed.

Further, as shown in FIG. 8, step S51
After designing the register transfer level, the chip size and system operating speed are estimated in step S52 based on the register transfer level circuit diagram, and the estimated value is compared with the required specifications in step S53 to verify the design result. If the estimated value does not meet the required specifications, the process proceeds to the logic level design in step S54. If the estimated value does not meet the required specifications, the process returns to step S51 to perform redesign at the register transfer level. . Similarly, step S5
After the logic level design of 4, the chip size, the system operating speed, etc. are estimated based on the logic level circuit diagram in step S55, and the estimated value is compared with the required specifications in step S56 to verify the design result. When the estimated value satisfies the required specification, the process proceeds to the layout design in step S57, while when the estimated value does not satisfy the required specification, the process returns to step S54 to redesign at the logic level.

As described above, in the upstream of the circuit design, that is, at the register transfer level, as shown in step S52 of FIG. 8, the area of the circuit, the operating speed, and the like are estimated, as a design support at the register transfer level. Very important.

As a concrete example of the conventional design support method at the register transfer level, as will be described below, the estimation is performed without considering the layout, or the area and the operation speed are calculated by using the layout model of the standard cell. What estimates is proposed.

Gajski's estimate of the data path area is based on the IEE International Conference on Computer Aided Design (1991), pages 34-37 (IEEE Internati
onal Conference on Computer-Aided Design (1991) p
As described in p.34-37), the layout model of the data path has a bit slice structure, and the area of the data path is obtained using the following equation (1).

Number of bits × (area of bit slice + wiring area) (1) The “area of bit slice” in equation (1) is the product of the average transistor pitch of the cells in the library and the number of transistors of the bit slice. Is the height of the bit slice, and the width of the bit slice is fixed with respect to the library to obtain the product of the height and the width of the bit slice. The "wiring area", which is the area of the wiring region between bit slices, is obtained as a function of the number of wiring tracks, the wiring pitch, and the wiring channel length. The wiring channel length is the length of the bit slice, and the number of wiring tracks is estimated by arranging all components in the bit slice one-dimensionally with min-cut and wiring with the left-edge method.

Gajski's estimate of datapath speed is from the IEE European Design Automation Conference (1992), pages 60-6.
Page 5 (IEEE Europe Design Automation Conference (19
92) pp.60-65), the data path delay is defined as the maximum value of the delay of all operations, and the delay of each operation is the propagation delay of each component such as the source register, ALU, and multiplexer. And the propagation delay of the wiring between the components and the setup time of the destination register. Here, the wiring length between the components is 1/2 of the height of the data path block.

For estimating the data path area and speed of Parker, the 35th to 41st pages of the 24th ACM / IEE Design Automation Conference (1987) (24th ACM / IEEE
As described in Design Automation Conference (1987) pp.35-41), the area of the data path is calculated as the sum of the area of all operations, the area of all registers, and all multiplexers. Further, the clock cycle of the data path is obtained as the sum of the maximum value of the delay of all operations, the setup time of the register, the propagation delay of the register and the propagation delay of the passing multiplexer. This method is a rough estimation method that is effective at a higher level than the register transfer level without considering layout such as layout and wiring.

[0015]

However, in the above-described conventional design support method at the register transfer level of the circuit design method, only a limited layout is taken into consideration when estimating the circuit area and operating speed, and Since the manufacturing technology is not taken into consideration, it is not possible to deal with the prediction of the layout area or the trade-off using the custom layout or module composition, and the accuracy of the estimation result is not good.

Further, looking at the entire conventional circuit design method, since the area of the circuit and the operating speed are estimated independently of the circuit synthesis, the assumptions made at the time of estimation are as follows: It will not be reset at the end of the estimation, and the assumption will not be embodied as it is and reflected in the circuit synthesis. For this reason, there is a large difference between the circuit assumed at the time of estimation and the actual circuit at the time of design completion, and as a result, the estimation accuracy at the register transfer level deteriorates.

The present invention has been made in view of the above, and in the register transfer level of the circuit design in which the data path portion and the control portion of the circuit are designed as blocks independent of each other in layout, the area and operating speed of the circuit are reduced. An object of the present invention is to provide a register transfer level design support device capable of improving estimation accuracy.

[0018]

In order to achieve the above object, the present invention provides a plurality of layout design methods which are different from each other at a register transfer level as a block realization method of a data path part of a circuit, and each layout design method. A layout is roughly designed by estimating the area and operation speed of the data path section based on the method, and optimizing the block shape based on the plurality of layout design methods.

Specifically, the means for solving the problems according to the invention of claim 1 is a register transfer level design which supports a circuit design for designing a data path part and a control part of a circuit as independent blocks in layout at a register transfer level. Targeting an assisting device, a plurality of library estimating means for generating a basic circuit group including a plurality of basic circuits each realizing the same calculation between registers with different areas and operating speeds, and different layout designs Selecting a combination of a plurality of layout design method description means for supplying a method, each of the plurality of basic circuit group libraries and one of the plurality of layout design methods as a data path block implementation method, The surface of the data path part based on the selected data path block realization method. And a plurality of data path part performance estimating means for estimating the operation speed, a plurality of control part performance estimating means for estimating the area and the operation speed of the control part based on different control block realizing methods, and the circuit. A plurality of data path block implementation methods and a plurality of control block implementation methods are selected based on the constraint of the overall operation speed, and a plurality of selected data path block implementation methods and a plurality of control block implementations are selected. A floorplan optimizing means for optimizing the block shapes of the data path section and the control path section based on the method.

According to a second aspect of the present invention, in addition to the configuration of the first aspect of the invention, a plurality of units are provided corresponding to each of the plurality of library estimating units, and the estimation results of the corresponding library estimating units are displayed. Library estimation result display means and a plurality of data path part performance estimation results, each of which is provided corresponding to each of the plurality of data path part performance estimation means and displays the estimation result of the corresponding data path part performance estimation means Display means, a plurality of control part performance estimation result display means each provided corresponding to each of the plurality of control part performance estimation means and displaying an estimation result of the corresponding control part performance estimation means, and the floor Floor plan optimization result display means provided corresponding to the plan optimization means and displaying the optimization result, and A plurality of library estimating interrupt means provided corresponding to each of the library estimating means and receiving a user interrupt of the corresponding library estimating means, and each corresponding to each of the plurality of data path part performance estimating means. A plurality of data path part performance estimation interrupting means provided to receive user interrupts of corresponding data path part performance estimating means, and a corresponding control part provided corresponding to each of the plurality of control part performance estimating means A plurality of control unit performance estimation interrupting means for accepting a user interrupt of the performance estimating means, and a floorplan optimizing interrupting means provided corresponding to the floorplan optimizing means for accepting a user interrupt are provided. If the By selecting and activating means related to the changed setting condition from among several library estimation means, a plurality of data path performance estimation means, a plurality of control performance estimation means and a floor plan optimization means, A configuration for eliminating a contradiction of setting conditions among the plurality of library estimating means, the plurality of data path performance estimating means, the plurality of control performance estimating means, and the floor plan optimizing means is added.

According to a third aspect of the present invention, in addition to the configuration of the first aspect of the invention, a delay time required for transfer between registers and its control,
Display means for displaying data in which a transfer method between registers and a control method of the processing order is expressed in a language or a figure, an operating speed of the entire circuit, a request for changing the operating speed of the entire circuit, and a request for changing the delay time. Interrupting means for accepting as a user interrupt, and the user interrupt activates the plurality of library estimating means, the plurality of data path performance estimating means, the plurality of control performance estimating means, and the floor plan optimizing means. By doing so, a configuration for performing optimization considering both the area of the circuit and the operating speed is added.

According to a fourth aspect of the present invention, in the configuration of the first aspect of the invention, each of the plurality of library estimating means sets the area and operating speed of the corresponding function as the width W and the length L of the transistor. An abstract gate circuit structure template that shows the connection relationship of the abstract gate circuit in a bit expandable manner using the ratio, that is, W / L as a parameter, and information that depends on the manufacturing technology for the abstract gate circuit of the abstract gate circuit structure template. The configuration to be estimated by using is added.

According to a fifth aspect of the present invention, in the configuration of the first aspect of the invention, each of the plurality of data path section performance estimating means includes a switch means whose on / off state corresponds to a setting of a layout condition of a layout design method. And a means for estimating the area and operation speed of the data path portion based on the layout condition when the layout condition is set, and each of the plurality of layout design method description means corresponds to the corresponding data path. The configuration is such that the layout condition of the layout design method is set depending on the on / off state of the switch means of the section performance estimating means.

According to a sixth aspect of the present invention, in the configuration of the first aspect of the invention, each of the plurality of data path unit performance estimating means includes a switch means whose on / off state corresponds to a setting of a layout condition of a layout design method. And a means for estimating the area and operation speed of the data path section based on the layout condition when the layout condition is set, and further, when the functional cells are arranged in one row, the one-dimensional dimension of the functional cell Configuration having at least one of means for optimizing arrangement, means for optimizing an implementation method when wiring is implemented by a bus or multiplexer, and means for estimating data transfer speed and block area Is added.

According to a seventh aspect of the present invention, in the configuration of the first aspect, each of the plurality of data path unit performance estimating means has one or more cells arranged in each cell row. The sum of the widths of the cells included in each cell row and the feed-through wiring is the width of the cell row, the maximum width of all the cell rows is the block width W, and the sum of the cell heights is the block width. The height is H, the maximum value of the delay time required for data transfer between registers is the operation speed S of the block, and the function of the width W, the height H, and the operation speed S in the block is sequentially repeated by changing the arrangement of cell rows. A configuration for optimizing the linear arrangement of cell rows is added by minimizing the evaluation function defined by.

An eighth aspect of the present invention is the configuration of the first aspect of the invention, wherein the floor plan optimizing means is
Obtain the constraint on the operation speed of the block based on the constraint on the operation speed of the entire circuit, list the combinations of block realization methods and block shapes that satisfy the constraint on the operation speed of the block, and As described above, a configuration for selecting a combination of the block realization method and the block shape for each block is added.

[0027]

According to the structure of the present invention, a plurality of library estimation means provide a library, and a plurality of layout design method description means provide a plurality of different layout design methods. Each data path part performance estimation means,
A combination of a library and a layout design method is selected as a block realization method of a data path part of a circuit, and an outline of a layout in a data path block is designed by using the block realization method. Then, the area and operation speed of the data path unit are estimated based on the designed layout. Here, in estimating the area and operating speed, various layout design methods such as a standard cell method, a gate array method, a module synthesis method, and a handcraft method can be taken into consideration, so that the accuracy of the estimation result can be improved. it can.

Further, the floorplan optimizing means selects a plurality of data path block realizing methods and control block realizing methods based on the constraint of the operation speed of the entire circuit, and obtains these block realizing methods and their estimation results. By comparing and studying, the block shapes of the data path part and the control part of the circuit can be optimized, and the design can be performed under accurate timing conditions in consideration of the layout. Here, even if the process or cell library is given later,
It is possible to proceed with the design by using the driving capability of the transistor, the wiring width, etc. as parameters, and at the time when the process is given, those parameters can be fixed and at the same time, the rough design of the chip can be completed.

Further, according to the configuration of the invention of claim 2, it is possible for the user to interrupt the estimation of the area of the block and the operation speed, and each interrupt means accepts the user's designation for circuit synthesis and presupposes the designation information. The estimation accuracy can be improved by performing the estimation.

With the configuration of the third aspect of the invention, the general layout can be optimized in the background without the user having to be aware of the layout at all.

According to the configuration of the fourth aspect of the present invention, even when the cell library is not provided, the information about the cell size and the operation speed is provided, and the area and the operation speed of the block and the chip are estimated by using the information. be able to.

According to the configuration of the seventh aspect of the invention, the layout of the data path portion of the circuit can be optimized in consideration of both the area of the block and the operation speed.

According to the structure of the eighth aspect of the present invention, since the operation speed of the block is taken into consideration when the shape of the block is optimized, the optimum shape is obtained in terms of both the area of the block and the operation speed. To be

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the configuration of a register transfer level design support device according to an embodiment of the present invention will be described with reference to the drawings. The register transfer level design support device supports a circuit design for designing a data path part and a control part of a circuit as independent blocks in layout at a register transfer level.

FIG. 1 shows the register transfer level design support apparatus. In FIG. 1, the register transfer level design support apparatus includes a plurality of library estimation means 10 provided corresponding to the data path portion of the circuit. The layout design method description means 20a to 20c and the data path part performance estimation means 30a to 30c are provided. One library estimating means 10 defines one basic circuit group consisting of a plurality of basic circuits that realize the same arithmetic operation between registers with different areas and operating speeds, and a plurality of library estimating means 10 allow a plurality of basic circuit groups to be formed. A library consisting of basic circuits is defined. The layout design method description means 20a to 20c describe different layout design methods in the data path part performance estimation means 30a to 30c, respectively. The data path section performance estimating means 30a to 30c are intended to support the design of the data path section of the circuit, and are characterized in that they are individually provided for a plurality of layout design methods.

Data path unit performance estimating means 30a to 30c
Display screens 40a to 40c with interrupt inputs, respectively, and data path performance estimating means 30a to 30c.
Receives interactive designations regarding the design of the data path unit from the display screens with interrupt input 40a to 40c, respectively. For example, the designation of the layout of the function, the designation of whether the wiring is realized by the bus or the multiplexer, and the designation of whether to insert the latch before or after the function are accepted. Further, the display screens 40a to 40c with interrupt input have a function of displaying the estimated values of the area and the operation speed calculated by the data path unit performance estimating means 30a to 30c, respectively.

Further, the register transfer level design support device is provided with an estimation selecting means 60, and any of the data path unit performance estimating means 30a to 30c is an estimation selecting means 60.
The predicted shape and timing information of the data path block are transferred from the data path part performance estimating means selected and selected to the floor plan optimizing means 80.

The floor plan optimizing means 80 is the arranging means 8
1, a wiring means 82, and a shape optimizing means 83, and a display screen 90 with interrupt input is provided corresponding to the floorplan optimizing means 80. The arranging means 81 is
The arrangement of the blocks is controlled, and the blocks are arranged based on the arrangement instruction or the automatic optimization instruction given from the display screen 90 with interrupt input. The wiring means 82 performs wiring between blocks and arrangement of pins. The shape optimization means 83
For the purpose of optimization in consideration of both the timing and the area, the estimation selection means 60 is used to select the block and optimize the block shape.

The estimation selecting means 60 is controlled by a signal from the floor plan optimizing means 80, and the selection of the data path part performance estimating means 30a to 30c can be freely switched. Furthermore, the register transfer level design support device is
A plurality of library estimation means 110, layout design method description means 120a to 120c, and control section performance estimation means 50 provided corresponding to the control section of the circuit.
a to 50c, and the control unit estimating means 5
0a to 50c each have a display screen 14 with an interrupt input.
0a to 140c are provided. The register transfer level design support device also includes dedicated function performance estimating means 70a to 70c provided corresponding to dedicated functions such as miscellaneous circuits, ROM, and RAM.

Control section performance estimating means 50a-50
c and dedicated function performance estimating means 70a to 70c
Is connected to the estimation selecting means 60, and is selected by the estimation selecting means 60 like the data path part performance specifying means 30a to 30c.

Next, a circuit design method using the register transfer level design support device configured as described above will be described.

FIG. 2 is a flow chart showing the circuit design method. The register transfer level design support device is used in steps S2, S3, S4 and S5 of FIG.

As shown in FIG. 2, first, in the register transfer level design in step S1, an arithmetic unit is defined corresponding to each operation, and the design data is used for data transfer between registers and sequence control between them. And part. Data transfer between the registers is collectively treated as a data path block. On the other hand, the control part is represented by a finite state machine.

Next, steps S2, S3, S4 and S5.
Then, the circuit design at the register transfer level using the register transfer level design support device is supported.

Corresponding to the design of the data path portion of the circuit, in step S2, a library is given to the data path portion performance estimating means 30a by, for example, a plurality of library estimating means 10, and the data is supplied from the layout design method describing means 20a. A layout design method is given to the path part performance estimating means 30a. Then, the data path unit performance estimating means 30
A uses the library and layout design method as a block implementation method of the data path unit to roughly design the layout in the data path block. Next, in step S3, the data path unit performance estimation means 30a estimates the area and operation speed of the data path unit based on the layout designed in step S2. Similarly, in response to the design of the control unit of the circuit, for example, the control unit performance estimation unit 50a estimates the area and operation speed of the control unit, and in response to the dedicated function, for example, the dedicated function performance estimation unit 70a is the dedicated function. Estimate area and motion speed of the part.

In step S4, the floor plan optimizing means 80 receives the expected shape of the block, the timing information and the like from the data path performance estimating means 30a, the control performance estimating means 50a and the dedicated function performance estimating means 70a, and the block The layout of the entire circuit is roughly designed by arranging the wiring, wiring between the blocks and pins.

Data path unit performance estimating means 30a-30
c, the control unit performance estimating means 50a-50c and the dedicated function performance estimating means 70a-70c respectively provide a plurality of block realization methods and their estimation results. Therefore, the floor plan optimizing unit 80 selects any one of the data path unit performance estimating units 30a to 30c, any one of the control unit performance estimating units 50a to 50c, and the dedicated function performance estimating units 70a to 70.
By changing the selection of any of 0c through the estimation selecting means 60 and repeating steps S2, S3 and S4, a plurality of block realization methods and their estimation results can be compared and examined. As a result, the floorplan optimizing unit 80 optimizes the block shape in consideration of both the clock and the area, which are the operating speeds of the entire circuit. Then, in step S5, it is determined whether or not such circuit optimization is completed, and when the optimization is completed, that is, the schematic design of the entire circuit is completed, the process proceeds to step S6.

Each block is expanded to a logic gate by the logic level design in step S6, the rough layout design at the register transfer level is improved in step S7, and the mask pattern of the LSI is determined in step S8 to complete the layout design. .

As described above, in the register transfer level design support apparatus according to this embodiment, the plurality of library estimating means 10 are the data path part performance estimating means 30a to 30.
The library is given to b, and the layout design method description means 2
0a to 20c are data path part performance estimating means 30 respectively.
Different layout design methods are given to a to 30b, and the data path unit performance estimating means 30a to 30b design the outline of the layout in the data path block using the library and the layout design method as the block realizing method. Then, similarly, the data path unit performance estimating means 30a to 30b.
Estimates the area and operation speed of the data path unit based on the designed layout. Here, in estimating the area and operating speed, various layout design methods such as a standard cell method, a gate array method, a module synthesis method, and a handcraft method can be taken into consideration, so that the accuracy of the estimation result can be improved. it can.

Further, the floorplan optimizing means selects a plurality of data path block realizing methods and control block realizing methods based on the constraint of the operation speed of the entire circuit, and obtains these block realizing methods and their estimation results. By making comparisons and examinations, the block shapes of the data path section and the control section of the circuit can be optimized, so that the overall layout of the circuit can be roughly designed.

In addition, the floor plan optimizing means 80 compares and examines a plurality of different block realization methods and their estimation results to achieve optimization in consideration of both the area of the entire circuit and the operating speed. Therefore, the design can be performed under the accurate timing condition taking the layout into consideration. Here, even if the process or cell library is given later,
It is possible to proceed with the design by using the driving capability of the transistor, the wiring width, etc. as parameters, and at the time when the process is given, those parameters can be fixed and at the same time, the rough design of the chip can be completed.

The register transfer level design support apparatus according to the present embodiment has an innovative structure as compared with the conventional one, and is very effective in terms of system design optimization and user friendliness.

Next, details of each means of the register transfer level design support apparatus according to the present embodiment will be described.

(User Interrupt Mechanism) The user interrupt mechanism of the register transfer level design support apparatus according to this embodiment will be described below.

Each means of the register transfer level design support device is constructed by an event activation type. That is, each means has a queue (queue) of events, and when there is an activation command from another means, the latest event request is stored in the last column of the queue. Further, each means also has a function of issuing an event request to activate other means as needed. Further, each means has data classified and has a list of means to be activated when each data is changed. The user interrupt is also processed as one of the event requests.

By using this event processing method, a plurality of library estimating means 10, 110, data path part performance estimating means 30a to 30c, control part performance estimating means 50a to 50c, and floor plan optimizing means 80. It is possible to independently accept user interrupts from the corresponding display screens with interrupt inputs.

When the setting condition is changed by the user interrupt, the related means is selected and activated,
It is also possible to realize a mechanism that eliminates the contradiction of setting conditions among the data held by each means.

According to the present embodiment, the user can proceed with the design while paying attention to the layout within the chip, so that it is possible to obtain better results in terms of area and operating speed than in the conventional case. However, some users have no knowledge or experience about layout, and it is meaningless to allow such a user to display the layout on the screen or modify the layout through the screen.

For users who have little knowledge and experience about such layouts, data representing the transfer method between registers and the control method of the processing order in a language or figure are mainly used.
We are only interested in timing information on that and data on overall system performance. Therefore, a function of accepting a request to change the system clock speed, a request to change the delay time, and the like, and optimizing layout information that greatly affects the delay time such as a floor plan in the background according to the change request are provided.

In order to realize this function, the delay time information for each data path is displayed to the user, the delay time improvement request from the user is accepted, and the library estimation means 10, 110, based on the generation of the request, Data path part performance estimating means 30a to 30c, control part performance estimating means 50a
.About.50c and the floor plan optimizing means 80 are further provided with a function of generating a delay time improvement request event.

(Library Estimating Means) The library estimating means of the register transfer level design support apparatus according to this embodiment will be described below.

The library estimating means 10 is intended to provide the data path part performance estimating means 30a to 30c with information on the cell area and operating speed. Similarly, the library estimation means 110 is the control unit performance estimation means 5.
The purpose is to give information on the cell area and operating speed to 0a to 50c.

A plurality of library estimating means 10, 110
Even if the cell library is not prepared, it is possible to estimate the information about the cell area and the operating speed. Therefore, not only at the register transfer level but also at the high level and the logic level, the area of the chip or block, the operating speed, It is an effective means for estimating the timing and the like.

The library estimating means 10 will be described below with reference to the drawings, but the library estimating means 110 is also the same.

FIG. 3 shows the library estimating means 10. In FIG. 3, the library estimating means 10 comprises a plurality of abstract gate circuit structure templates 11, a technology defining means 12, and an area / operating speed estimating means 13. And template selection means 14.

Abstract gate circuit structure template 11
Is a bit expandable description of the connection of logic gates at an abstract level that does not depend on the manufacturing technology. For example, 10-input AND operation is represented by one abstract gate. In the case of actually manufacturing this, it is necessary to make multi-stages by a combination of two-input AND operations.

The template selecting means 14 is provided with an interrupt input display screen 15 as a means for displaying and modifying the abstract gate circuit structure template 11, so that the user can newly add another function for the same function as required. It is also possible to register an abstract gate circuit.

The technology definition means 12 takes the manufacturing conditions into consideration and converts the abstract gate circuit into a practically usable form, the calculation formula of the delay time determined by the manufacturing technology, and the layout of the gate. It holds information such as the proportion occupied by wiring. Specifically, the transistor circuit in the gate, the number of transistors and the number of stages, the delay calculation formula depending on the W / L of the transistor, the in-cell wiring portion ratio, the design rule, etc. are registered. Here, the W / L of the transistor is a parameter indicating the drive capability of the transistor, and the larger this value, the faster the signal can be propagated. L means the length of the transistor, W means the width of the transistor,
Normally, L is set to the minimum width of the design rule, so W
Only changes. Therefore, in order to speed up the signal propagation, it is necessary to increase W, that is, increase the size (area) of the transistor.

The area / operation speed estimating means 13 receives a plurality of abstract gate circuit structure templates 11 from the template selecting means 14, and the technology defining means 12 calculates the delay time determined by the manufacturing technology and lays out the gates. In such a case, the information such as the proportion occupied by the wiring portion is received, and the relationship between the area and the operating speed is obtained for a plurality of cell realization methods.

The starting procedure of the library estimating means 10 configured as above will be described.

The following signals are input to activate the library estimating means 10.

Function Name / Number of Bits First, the template selection means 14 selects a plurality of abstract gate circuit structure templates 11 of cells corresponding to the function indicated by the function name. For example, for the adder function, an abstract gate circuit such as a carry look ahead adder or a ripple carry adder (a gate circuit that is independent of manufacturing technology and capable of expanding bits) is selected.

Next, referring to the technology definition means 12,
Replace the abstract gate circuit with an actual transistor circuit (or a representation of the number of transistors and the number of stages). In the case of a multi-input gate, the inside of the gate is multi-staged in order to cover many fan-ins depending on the number of bits.

Next, the technology defining means 12 calculates the area of the gate and the operating speed by the number of transistors and the number of stages, the delay calculation formula and W / L. As a result, the area of the gate and the operating speed are expressed using W / L as a parameter.

Next, the area of the gate and the operating speed obtained by the technology defining means 12 are used for the cells corresponding to each abstract gate circuit of the abstract gate circuit structure template 11 selected by the template selecting means 14. Estimate the area and motion speed of the. Here, the operating speed of the cell is
It is the delay value of the critical path (the path with the longest delay time) on the gate circuit. The cell area is a value obtained by multiplying the sum of gate areas by α. However, α is a value that depends on the number of usable wiring layers, and is represented by α = (1 + wiring portion ratio).

FIG. 4 shows an area / operating speed trade-off curve of an output example when the adder is considered as a function. As an adder configuration, the abstract gate circuit structure template 11 of carry look ahead adder and ripple carry adder is registered, and there is a trade-off due to the change of W / L for each.

(Layout Design Method Description Means) The layout design method description means of the register transfer level design support apparatus according to this embodiment will be described below. Here, the layout design method description means 20a will be described, but the layout design method description means 20b, 20c, 120a to 12 will be described.
0c is also the same. .

The layout design method description means 20a is means for describing the rules relating to the layout design. The contents described are as follows.

-Wiring method-Number of wiring layers or possibility of on-cell wiring-Method of realizing wiring switching section-Cell type (custom, pin movable cell, standard cell, etc.) Example of actual data path section layout design method Is shown below.

Custom layout (manual design) Basically, in the case of manual design, the layout style is free, but the following method is generally adopted. The cell area is determined by the circuit used, but the shape (aspect ratio) and pin position can be set freely. Therefore, it is sufficient to secure the number of tracks required for wiring in the cell row direction for channels between cell rows.

Module synthesis There are various types of module synthesis, but they are classified into a channel wiring system and a pin alignment system. In the case of the channel wiring system, no effort is made to align the cell pin positions. Functions are arranged in each cell row, and each cell fetches area and speed data from a library prepared in advance. When the pin alignment method is adopted, the cell has a function of adjusting the pin position. However, unlike the custom design, the cell width is increased to adjust the pin position. The increment is equal to the sum of the pin position movement distances. If the order of arrangement of pin sets to be connected in adjacent cell rows is the same, the sum of the distance differences between adjacent pins becomes the increment of the cell width. If the order of arrangement of pin sets is reversed, wiring in the channel region is required.

Standard cell method Basically, a combination of standard cells (in some cases,
Macro cells are also combined). Although there is no particular restriction that the same function is realized in the same cell row, they are arranged in almost the same row. Wiring is performed by channel wiring.

Feed-through wiring method The feed-through wiring depends on the wiring layer that can be used.
It is divided into the case of passing between cells and the case of passing over cells.

In consideration of the above, each layout design method can be defined by the following combination of classifications.

Classification by Channel Wiring and Pin Positioning Classification by Feed-through between Cells and Feed-through on Cells Bit-slice and Function-slice The classification data path section performance estimating means 30a is provided with a condition switch and an estimation processing means for switching the estimation processing method of the area and the operating speed according to the classification conditions of, and the layout design method description means 20a describes these conditions. Position it as a means. The description of the condition is expressed by the on / off state of the condition switch.

(Data Path Part Performance Estimating Means) The data path part performance estimating means of the register transfer level design support apparatus according to this embodiment will be described below. Here, the data path part performance estimating means 30a will be described based on the drawings, but the data path part performance estimating means 30b and 30c are also the same.

FIG. 5 shows the data path part performance estimating means 30a. In FIG. 5, the data path part performance estimating means 30a includes a condition switch 31, a linear arrangement means 32, a cell selecting means 33, and a channel width estimating means 34. It has a cell row width estimating means 35, a bus / multiplexer switching means 36, a bit slice / function slice switching means 37, and a linear arrangement optimizing means 38. Further, a plurality of library estimating means 10 (or the existing cell library 10) are provided corresponding to the data path part performance estimating means 30a.
0), a layout design method description means 20a and an interrupt input display screen 40a are provided.

FIG. 6 shows an example of a layout model used for estimation, which is a custom layout when a wiring cannot pass over a cell.

In FIG. 6, 301 is a cell, 302 is a cell row, 303 is a feedthrough, 304 is a channel, 3
Reference numeral 05 denotes an external pin of the block.

The operation of each means of the data path section performance estimating means 30a will be described below.

Linear arrangement means 32: Initializes the arrangement of functions. It is also possible to perform automatic linear layout optimization with the goal of minimizing the area or maximizing the operating speed, if necessary. Details of the automatic linear placement optimization will be described later.

Cell selection means 33 From each of the plurality of library estimation means 10 (or the existing cell library 100) given as a precondition, the cell 301 of the bit unit forming each function is taken out, and the cell 301 is stored in the designated row. The function cells 301 are arranged according to the bit arrangement. Also, feedthrough 3
In consideration of the width occupied by 03 in the cell row 302, it is possible to perform automatic cell selection optimization for optimizing cell selection so as to make the cell widths as uniform as possible.

Channel Width Estimating Means 34 The width of each channel 304 is estimated when the cell rows are realized by channel wiring. The number of wiring tracks of the same channel is obtained based on the connection request given to the pin positions including the top, bottom, left and right feedthroughs 303 of each channel 304, and the width of the channel is obtained based on that.

When wiring the channel 304 between the cell rows, in order to connect the upper and lower sides of the channel 304,
Estimate each channel width and the increment of the cell row width in the case where the channel width is minimized by performing the pin alignment so as to pass straight through the top and bottom. When the custom layout method is used, that is, when the size of the cell 301 is fetched from the library estimating unit 10a, the cell shape and the pin position can be flexibly changed, so that the cell width does not increase.

When the cell is of the module synthesizing type and the cell is of the pin aligning type, the cell has a function of adjusting the pin position. However, unlike the custom design, the cell width is increased to adjust the pin position. The increment is equal to the sum of the pin position movement distances. If the order of arrangement of pin sets to be connected in adjacent cell rows is the same, the sum of the distance differences between adjacent pins becomes the increment of the cell width. If the order of arrangement of pin sets is reversed, wiring in the channel region is required. As for the channel width, the number of wiring tracks for the wiring having a horizontal wiring request with respect to the channel 304 (for example, a control line) and the horizontal wiring generated due to a failure in the pin alignment are obtained, and the width of the channel 304 is obtained based on the number. .

Cell row width estimation means 35 When feedthrough above the cell is prohibited,
The width required to pass the feedthrough wiring is added to the cell row width, and the value is taken as the cell row width.

Bus / Multiplexer Switching Means 36 The bus and multiplexer are required when one wiring resource is shared or used by switching, and each is realized by a tristate buffer for each bit or a cell of a multiplexer. Therefore, the linear arrangement means 32, the cell selection means 33, the channel width estimation means 34, and the cell row width estimation means 35 are activated by providing a cell row made up of necessary cells in the necessary parts of the bus and multiplexer.

Linear arrangement optimizing means 38 The linear arrangement optimizing means 38 is means for performing linear arrangement of the functions in the data path.

FIGS. 7A and 7B show data to be handled and an abstracted model. In FIG. 7, 401 indicates functions (F1 to F4) and 402 indicates inter-function wiring. .

The height H is given as the sum of the total cell height and the total channel height. If you swap the cell rows,
The value of W changes because the number of feedthroughs in each cell row changes. Further, since the wiring length before and after each function also changes, the operating speed S of the data path unit also changes.

The difference between the abstract model of FIG. 7A and the abstract model of FIG. 7B is that the positions of the functions F2 and F3 are interchanged. In FIG. 6A, the width W
Is 120, and the width W is 130 in FIG. Also,
The operating speed S depends on the driving ability of the transistor and the wiring length.

The data path linear arrangement method of the linear arrangement optimizing means 38 aims at minimizing the objective function given by the functions of W, H and S, and the value of the evaluation function is calculated by repeating the replacement of the cell rows. This is an optimization method. As the optimization method, a known simulated annealing method or the like can be used.

(Shape Optimizer) Hereinafter, the shape optimizer 83 of the register transfer level design support apparatus according to the present embodiment.
Will be described.

The shape optimizing means 83 is intended to determine the combination of the shapes of the minimum areas which satisfy the condition when the speed constraint is given.

The areas of blocks such as data paths and controls used in LSI design differ depending on the speed. Furthermore, for each speed (delay time),
The vertical and horizontal sizes are not uniform, and a plurality of shapes can be adopted.

At the register transfer level, it is the clock period that determines the performance of the system. When the clock cycle is determined, the minimum operation speed (maximum delay) required for each block included in the system is determined. Based on that condition, all possible vertical and horizontal sizes of each block can be enumerated.

The vertical and horizontal sizes are plotted on the XY coordinates, and arbitrary two points A (x1, y1) and B (x2, y2) are plotted.
The point B is repeatedly removed when the relation of satisfies the relations x1 <x2 and y1 <y2, whereby the set of remaining points is defined as the shape function of the block, and the conventional shape optimization without considering the speed is performed. The method is used to optimize the shape.

The conventional shape optimizing methods have been aimed only at minimizing the area or only optimizing the delay regarding the wiring length. However, in the shape optimizing means 83, the operating speed of the entire circuit is also taken into consideration, and the optimum solution can be obtained in terms of both area and operating speed.

[0109]

As described above, according to the register transfer level design support apparatus according to the invention of claims 1 to 8, the area and operating speed of the data path portion of the circuit are estimated in consideration of the layout design method. Therefore, the accuracy of the estimation result can be improved. Further, it is possible to optimize the block shape in consideration of both the area of the entire circuit and the operation speed, and it is possible to perform the design under an accurate timing condition in consideration of the layout.

Furthermore, according to the register transfer level design support apparatus of the second aspect of the present invention, the user can interrupt the estimation of the area of the block and the operation speed, and each interrupt means can be designated by the user for circuit synthesis. Is accepted and estimation is performed on the basis of the specified information, the estimation accuracy can be improved.

According to the register transfer level design support apparatus of the third aspect of the present invention, the rough layout can be optimized in the background without the user having to be aware of the layout at all.

According to the register transfer level design support apparatus of the fourth aspect of the present invention, even when the cell library is not provided, the information about the cell size and the operation speed is provided, and the information about the block and chip is used. Area and motion speed can be estimated.

According to the register transfer level design support apparatus of the seventh aspect of the present invention, the layout of the data path portion of the circuit can be optimized in consideration of both the block area and the operation speed.

According to the register transfer level design support apparatus of the eighth aspect, since the operation speed of the block is taken into consideration when the shape of the block is optimized, both the area of the block and the operation speed of the block are considered. Optimal shape is obtained in terms of points.

As described above, according to the present invention, at the register transfer level of the circuit design, the rough design of the layout can be performed simultaneously with the estimation, so that the estimation accuracy can be remarkably improved. Further, it is possible to minimize design rework such as proceeding to the detailed layout design and returning to the register transfer level design again, and it is possible to greatly reduce the time required for the circuit design process.

[Brief description of drawings]

FIG. 1 is a block diagram showing a register transfer level design support device according to an embodiment of the present invention.

FIG. 2 is a flow chart showing a circuit design method using the register transfer level design support device.

FIG. 3 is a block diagram showing a library estimating means of the register transfer level design support device.

FIG. 4 is a graph showing a trade-off curve between an area of an adder function and an operating speed.

FIG. 5 is a block diagram showing a data path unit performance estimating means of the register transfer level design support device.

FIG. 6 is a diagram showing a layout model used for estimation by the data path unit performance estimation means.

FIG. 7 is a diagram showing an abstract model of a functional linear arrangement.

FIG. 8 is a flowchart showing a conventional circuit design method.

[Explanation of symbols]

10 Library Estimating Means 11 Abstract Gate Circuit Structure Template 12 Technology Defining Means 13 Area / Operating Speed Estimating Means 14 Template Selecting Means 15 Display Screen with Interrupt Input 20a to 20c Layout Design Method Describing Means 30a to 30c Data Path Performance Estimating Means 31 Condition switch 32 Linear placement means 33 Cell selection means 34 Channel width estimation means 35 Cell row width estimation means 36 Bus / multiplexer switching means 37 Bit slice / function slice switching means 38 Linear placement optimization means 40a-40c Display screen with interrupt input 50a ˜50c Control part performance estimating means 60 Estimating selecting means 70a to 70c Special function performance estimating means 80 Floorplan optimizing means 81 Arranging means 82 Wiring means 83 Shape optimizing hand 90 interrupt input with the display screen 100 cell library 110 library estimator 120a~120c layout design method described means 140a~140c interrupt input with the display screen 301 cell 302 cell row 303 feed through 304 channel 305 external pin 401 Function 402 function between the wires

Claims (8)

[Claims] 1. A register transfer level design support device for supporting a circuit design for designing a data path part and a control part of a circuit as independent blocks in layout at a register transfer level, each of which is the same between registers. A plurality of library estimating means for generating a basic circuit group consisting of a plurality of basic circuits for realizing the above calculation in different areas and operating speeds, and a plurality of layout design method description means for respectively supplying different layout design methods. , Selecting a combination of a library consisting of a plurality of the basic circuit groups and any of a plurality of the layout design methods as a data path block realizing method, and selecting the data based on the selected data path block realizing method. Multiple data paths to estimate path area and operation speed Section performance estimating means, a plurality of control section performance estimating means for estimating the area and operating speed of the control section based on different control block realizing methods, and a plurality of control section performance estimating means based on the restriction of the operating speed of the entire circuit. The data path block realizing method and the plurality of control block realizing methods are selected, and the data path unit and the control unit are based on the selected plurality of data path block realizing methods and the plurality of control block realizing methods. And a floor plan optimizing means for optimizing the block shape of the register transfer level design support apparatus. 2. A plurality of library estimation result display means, each of which is provided corresponding to each of the plurality of library estimation means and displays the estimation result of the corresponding library estimation means, and each of the plurality of data. A plurality of data path part performance estimation result display means provided corresponding to each of the path part performance estimation means and displaying the estimation result of the corresponding data path part performance estimation means; A plurality of control section performance estimation result display means provided corresponding to each of the means and displaying the estimation result of the corresponding control section performance estimation means; and an optimization result provided corresponding to the floor plan optimization means. Floorplan optimization result display means to be displayed, and each corresponding to each of the plurality of library estimation means. A plurality of library estimation interrupting means that are provided for receiving user interrupts of the corresponding library estimating means, and data path portion performance estimating means provided corresponding to each of the plurality of data path portion performance estimating means. A plurality of data path part performance estimation interrupting means for accepting user interrupts of the means, and a plurality of data path part performance estimating interrupting means each provided for each of the plurality of control part performance estimating means and accepting user interrupts of the corresponding control part performance estimating means And a floorplan optimization interrupting means provided corresponding to the floorplan optimizing means for accepting a user interrupt, wherein the plurality of units are provided when the setting condition is changed by the user interrupt. Library estimation means, multiple A plurality of library estimating means and a plurality of library estimating means by selecting and activating means related to the changed setting condition from among the data path performance estimating means, the plurality of performance estimating means and the floorplan optimizing means. 2. The register transfer level according to claim 1, wherein the register transfer level is configured to eliminate a contradiction of setting conditions among the data path section performance estimating means, the plurality of control section performance estimating means, and the floor plan optimizing means. Design support device. 3. A display means for displaying a delay time required for transfer between registers and control thereof, data in which a control method for transfer between registers and its processing order is expressed in a language or a figure, and an operating speed of the entire circuit. An interrupt means for accepting a request for changing the operating speed of the entire circuit and a request for changing the delay time as a user interrupt, wherein the user interrupt causes the plurality of library estimating means and the plurality of data path unit performance estimating means. The plurality of control unit performance estimating means and the floorplan optimizing means are activated to perform optimization in consideration of both the area of the circuit and the operating speed. The register transfer level design support device described in 1. 4. Each of the plurality of library estimation means uses the area and operation speed of the corresponding function with the ratio of the width W and the length L of the transistor, that is, W / L as a parameter. The estimation is performed using an abstract gate circuit structure template indicating a connection relationship so as to be capable of bit expansion and information depending on a manufacturing technology for the abstract gate circuit structure template of the abstract gate circuit structure template. Register transfer level design support device. 5. Each of the plurality of data path unit performance estimation means has a switch means whose on / off state corresponds to a layout condition setting of a layout design method and a layout condition when the layout condition is set. And a means for estimating the area and the operation speed of the data path section based on the layout design method according to the ON / OFF state of the switch means of the corresponding data path section performance estimating means. 2. The register transfer level design support device according to claim 1, wherein a layout condition of a method is set. 6. Each of the plurality of data path unit performance estimation means has a switch means whose on / off state corresponds to a layout condition setting of a layout design method, and a layout condition when the layout condition is set. And a means for estimating the area and operating speed of the data path portion based on the above, and further, for arranging the functional cells in one row, a means for optimizing the one-dimensional arrangement of the functional cells and wiring are realized by a bus or a multiplexer 2. The register transfer level design according to claim 1, further comprising at least one of a means for optimizing an implementation method in the case of performing and a means for estimating a data transfer speed and a block area. Support device. 7. Each of the plurality of data path unit performance estimating means determines a width of a cell and a feedthrough wiring included in each cell row when one or a plurality of cells are arranged in each cell row. The sum total is taken as the width of the cell row, the maximum width of all the cell rows is taken as the block width W, the sum of the cell heights is taken as the block height H, and the delay time required for data transfer between registers is calculated. The maximum value is set as the operation speed S of the block, and the evaluation function defined by the functions of the width W, the height H and the operation speed S in the block is minimized by sequentially changing the arrangement of the cell rows to minimize the cell row. 2. The register transfer level design support apparatus according to claim 1, wherein the linear arrangement of is optimized. 8. The floorplan optimizing means, for each block, obtains a constraint on the operating speed of the block based on the constraint on the operating speed of the entire circuit, and realizes a block that satisfies the constraint on the operating speed of the block. A register transfer level design support device characterized by enumerating combinations of methods and block shapes and selecting a combination of a block realization method and a block shape for each block so that the area of the entire circuit is minimized.