JP3129883B2 - Register transfer level design support system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register transfer level design support device for supporting circuit design at a register transfer level.

[0002]

2. Description of the Related Art Recently, descriptions using a hardware description language or a graphic have come to be made at a register transfer level of a circuit design. What is commonly performed in these synthesizing methods is to clearly separate the flow of data into a data path portion that handles data operations and a control portion that handles the processing order of operations, and perform optimization. .

Since the data path is implemented by a relatively regular repetitive circuit, it is easy to predict and optimize the delay time between registers. On the other hand, the control section has a strong randomness and is difficult to predict and optimize.
To realize a system including the data path unit and the control unit in a VLSI mask layout, there are the following two types of circuit design methods.

A circuit design method for realizing a data path unit and a control unit in one block collectively A circuit design method in which a data path unit and a control unit are treated as separate blocks on a layout When the circuit scale of the system is about 1000 gates or less. If the circuit size (the number of gates) of the data path section is not more than about 10 times as large as that of the control section, the circuit design method is effective in minimizing the area. In other cases, it is effective to use a circuit design method and apply a dedicated layout method to the data path portion.

When the circuit design method described above is used, most of the area on the chip is occupied by the data path portion. For this reason, in the estimation of the chip area, the estimation of the data path section becomes more important than the estimation of the control section. However, it is necessary to realize such that both the control unit and the data path unit satisfy the conditions in terms of timing.
Hereinafter, a conventional circuit design method and a design support method at a register transfer level when a data path portion and a control portion of a circuit are designed as blocks independent from each other on a layout will be described.

FIG. 8 is a flow chart showing the conventional circuit design method. As shown in FIG.
From the design of the register transfer level of S51, step S54
After the logic level design, the process proceeds to the layout design in step S57, and the conceptual model of the circuit is sequentially converted from a high abstraction level to a specific level.

First, in the design of the register transfer level in step S51, a computing unit (hardware) is defined corresponding to each operation, and the design data is transferred by data transfer between the registers and an order control portion therebetween. Be composed. The data transfer between the registers is collectively treated as a data path block. On the other hand, the control part is represented by a finite state machine (Finite State Machine). next,
In the logic level design in step S54, each block is developed into a logic gate in accordance with the detailed specification defined at the register transfer level. Using a cell library, appropriate ones are selected from among them, and they are combined and configured. Then, in the layout design in step S57, the arrangement of each block, the wiring between the blocks, and the like are determined, and the mask pattern of the LSI is designed.

[0008] Further, as shown in FIG.
After the design of the register transfer level, the estimation of the chip size and the operating speed of the system is performed based on the circuit diagram of the register transfer level in step S52, and the estimated value is compared with the required specification in step S53 to verify the design result. If the estimated value satisfies the required specification, the process proceeds to the logic level design in step S54, while if the estimated value does not satisfy the required specification, the process returns to step S51 to perform redesign at the register transfer level. . Similarly, step S5
After the design at the logic level of 4, the estimation of the chip size and the operation speed of the system is performed based on the logic level circuit diagram at a step S55, and the estimated value is compared with the required specification at a step S56 to verify the design result. If the estimated value satisfies the required specification, the process proceeds to the layout design in step S57. On the other hand, if the estimated value does not satisfy the required specification, the process returns to step S54 to perform redesign at the logic level.

As described above, at the upstream of the circuit design, that is, at the register transfer level, as shown in step S52 of FIG. 8, the estimation of the circuit area and the operation speed is performed as a design support at the register transfer level. Very important.

As a specific example of the conventional design support method at the register transfer level, as described below, a method of estimating without considering layout, or an area and operation speed using a layout model of a standard cell are described. Have been proposed.

According to Gajski's estimation of the data path area, IEE International Conference on Computer Aided Design (1991), pp. 34 to 37 (IEEE Internati)
onal Conference on Computer-Aided Design (1991) p
As described in (pp. 34-37), the layout model of the data path has a bit slice structure, and the area of the data path is obtained using the following equation (1).

The number of bits × (the area of the bit slice + the wiring area) (1) The “area of the bit slice” in the equation (1) is the product of the average of the transistor pitch of the cells in the library and the number of the transistors of the bit slice. Is the height of the bit slice, and the width of the bit slice is fixed with respect to the library, thereby obtaining the product of the height and the width of the bit slice. The “wiring area”, which is the area of the wiring area between bit slices, is obtained as a function of the number of wiring tracks, wiring pitch, and wiring channel length. The wiring channel length is the length of a bit slice, and the number of wiring tracks is estimated by arranging all components in a bit slice one-dimensionally with min-cut and wiring them by a left-edge method.

According to Gajski's estimate of the data path speed, pages 60 to 6 of the IEE Europe Design Automation Conference (1992) were used.
Page 5 (IEEE Europe Design Automation Conference (19
92) As described in pp.60-65), the delay of the data path is defined as the maximum value of the delay of all operations, and the delay of each operation is defined as the propagation delay of each component such as a source register, ALU, and multiplexer. And the propagation delay of the wiring between the components and the setup time of the destination register. Here, the wiring length between the components is １ ／ of the height of the data path block.

In the estimation of Parker's data path area and speed, the 24th ACM / IEE Design Automation Conference (1987), pp. 35 to 41 (24th ACM / IEEE
As described in Design Automation Conference (1987) pp.35-41), the area of the data path is obtained as the sum of the area of all operations, the area of all registers, and all multiplexers. Further, the clock cycle of the data path is obtained as the sum of the maximum value of the delay of all operations, the setup time of the register, the propagation delay of the register, and the propagation delay of the passing multiplexer. This method is a rough estimation method that is effective at a higher level than the register transfer level without considering the layout such as arrangement and wiring.

[0015]

However, in the conventional design support method at the register transfer level of the circuit design method, only a limited layout is considered when estimating the circuit area and the operation speed. Also, since the manufacturing technology is not taken into account, it is not possible to cope with a layout area prediction or a trade-off using a custom layout, module synthesis, or the like, and the accuracy of the estimation result is poor.

Turning now to the conventional circuit design method as a whole, the estimation of the circuit area and operation speed is performed independently and independently of the circuit synthesis. It is reset at the end of the estimation, and the assumption is not embodied as it is and reflected in circuit synthesis. For this reason, there is a problem that the difference between the circuit assumed at the time of estimation and the actual circuit at the time of completion of design becomes large, and as a result, the estimation accuracy at the register transfer level deteriorates.

The present invention has been made in view of the above, and has been made in consideration of the above, and has been made in consideration of the circuit area and operation speed at a register transfer level of a circuit design in which a data path portion and a control portion of a circuit are designed as blocks independent from each other on a layout. An object of the present invention is to provide a register transfer level design support device capable of improving estimation accuracy.

[0018]

In order to achieve the above object, the present invention provides a plurality of layout design methods different from each other at a register transfer level as a block realization method of a data path portion of a circuit. The layout and the operation speed are estimated based on the scheme, and the block layout is optimized by optimizing the block shape based on the plurality of layout design schemes.

Specifically, a solution taken by the first aspect of the present invention is a register transfer level design for supporting a circuit design in which a data path portion and a control portion of a circuit are designed as independent blocks on a layout at a register transfer level. A plurality of library estimating means for generating a basic circuit group consisting of a plurality of basic circuits each for realizing the same operation between registers with different areas and operating speeds, and different layout designs for the support device; A plurality of layout design method description means for supplying a method, each of which selects a combination of a library including a plurality of the basic circuit groups and any of the plurality of the layout design methods as a data path block realizing method; A surface of the data path unit based on the selected data path block realizing method; A plurality of data path unit performance estimating means for estimating operation speed, a plurality of control unit performance estimating means for estimating the area and operation speed of the control unit based on different control block realization methods, and the circuit Selecting a plurality of the data path block realizing methods and a plurality of the control block realizing methods based on the overall operation speed constraint, and selecting the plurality of the data path block realizing methods and the plurality of control block realizing methods; Floor plan optimizing means for optimizing the block shapes of the data path unit and the control path unit based on a method.

According to a second aspect of the present invention, in the configuration of the first aspect of the present invention, there are provided a plurality of library estimating means each of which is provided corresponding to each of the plurality of library estimating means. Library estimation result display means, and a plurality of data path section performance estimation results each provided corresponding to each of the plurality of data path section performance estimation means and displaying the estimation results of the corresponding data path section performance estimation means Display means, a plurality of control section performance estimation result display means each provided corresponding to each of the plurality of control section performance estimation means and displaying the estimation result of the corresponding control section performance estimation means, and the floor Floor plan optimization result display means provided corresponding to the plan optimization means and displaying the optimization result; A plurality of library estimating interrupt means provided corresponding to each of the plurality of library estimating means and receiving a user interrupt of the corresponding library estimating means, each corresponding to each of the plurality of data path unit performance estimating means; A plurality of data path section performance estimation interrupt means provided for receiving a user interrupt of the corresponding data path section performance estimation means; and a corresponding control section provided corresponding to each of the plurality of control section performance estimation means. A plurality of control section performance estimating interrupt means for receiving a user interrupt of the performance estimating means; and a floor plan optimizing interrupt means provided corresponding to the floor plan optimizing means for receiving a user interrupt; Is changed, By selecting and activating means related to the changed setting conditions from several library estimating means, a plurality of data path section performance estimating means, a plurality of control section performance estimating means and a floor plan optimizing means, A configuration for eliminating inconsistencies in setting conditions among the plurality of library estimation units, the plurality of data path unit performance estimation units, the plurality of control unit performance estimation units, and the floor plan optimization unit is added.

According to a third aspect of the present invention, there is provided the configuration according to the first aspect of the present invention, wherein a delay time required for inter-register transfer and its control,
Display means for displaying data expressed in a language or a diagram in the method of controlling the transfer between registers and the processing order thereof, and the operation speed of the entire circuit; And a plurality of library estimating means, a plurality of data path section performance estimating means, a plurality of control section performance estimating means, and a floor plan optimizing means. By doing so, a configuration for performing optimization in consideration of both the circuit area and the operation speed is added.

According to a fourth aspect of the present invention, in the configuration of the first aspect, each of the plurality of library estimating means determines an area and an operation speed of a corresponding function by a width W and a length L of a transistor. Using the ratio, ie, W / L, as a parameter, an abstract gate circuit structure template that indicates the connection relation of the abstract gate circuit in a bit-expandable manner, and information depending on the manufacturing technology for the abstract gate circuit of the abstract gate circuit structure template This is to add a configuration to be estimated by using.

According to a fifth aspect of the present invention, in the configuration of the first aspect, each of the plurality of data path section performance estimating means includes a switch means whose on / off state corresponds to setting of a layout condition of a layout design method. Means for estimating the area and operation speed of a data path unit based on the layout conditions when the layout conditions are set, wherein each of the plurality of layout design method description means A configuration for setting the layout conditions of the layout design method according to the on / off state of the switch means of the unit performance estimating means is added.

According to a sixth aspect of the present invention, in the configuration of the first aspect, each of the plurality of data path section performance estimating means includes a switch means whose on / off state corresponds to setting of a layout condition of a layout design method. Means for estimating an area and an operation speed of a data path portion based on the layout condition when the layout condition is set, and further comprising: A configuration having at least one of a means for optimizing the arrangement, a means for optimizing a method of realizing wiring when realized by a bus or a multiplexer, and a means for estimating a data transfer speed and a block area Is added.

According to a seventh aspect of the present invention, in the configuration of the first aspect, each of the plurality of data path section performance estimating means includes one or more cells arranged in each cell row. The sum of the widths of the cells and the feedthrough wiring included in each cell row is defined as the width of the cell row, the maximum width of all the cell rows is defined as the block width W, and the sum of the cell heights is defined as the block width. The height H, the maximum value of the delay time required for data transfer between the registers is the operation speed S of the block, and the change of the arrangement of the cell rows is sequentially repeated to obtain a function of the width W, the height H, and the operation speed S in the block. Is added to optimize the linear arrangement of the cell rows by minimizing the evaluation function defined by.

According to an eighth aspect of the present invention, in the configuration of the first aspect, the floor plan optimizing means includes:
Obtain the restriction on the operation speed of the block based on the restriction on the operation speed of the entire circuit, enumerate combinations of block realization methods and block shapes that satisfy the restriction on the operation speed of the block, and determine that the area of the entire circuit is minimum. Thus, a configuration for selecting a combination of a block realizing method and a block shape for each block is added.

[0027]

According to the invention, a plurality of library estimating means provide a library, and a plurality of layout design method description means provide a plurality of different layout design methods. Each data path section performance estimation means
A combination of a library and a layout design method is selected as a block realization method for a data path portion of a circuit, and an outline of a layout in a data path block is designed using the block realization method. Then, the area and the operation speed of the data path section are estimated based on the designed layout. Here, in estimating the area and the operation speed, for example, various layout design methods such as a standard cell method, a gate array method, a module synthesis method, and handcraft can be considered, so that the accuracy of the estimation result can be improved. it can.

Further, the floor plan optimizing means selects a plurality of data path block realizing methods and control block realizing methods based on the restriction of the operation speed of the whole circuit, and selects these block realizing methods and their estimation results. By comparing and studying, the block shapes of the data path portion and the control portion of the circuit can be optimized, and the design can be performed under accurate timing conditions in consideration of the layout. Here, even if a process or cell library is given later,
The design can be advanced by using the drive capability of the transistor, the wiring width, and the like as parameters, and when the process is given, these parameters can be fixed, and at the same time, the rough design of the chip can be completed.

Further, according to the configuration of the second aspect of the present invention, it is possible for the user to interrupt the estimation of the block area and the operation speed, and each interrupt means accepts a user's designation for circuit synthesis and assumes the designation information. By performing the estimation as, it is possible to improve the estimation accuracy.

According to the configuration of the third aspect of the invention, the general layout can be optimized in the background without the user being conscious of the layout at all.

According to the configuration of the fourth aspect of the present invention, even when a cell library is not provided, information on cell size and operation speed is provided, and the area and operation speed of blocks and chips are estimated using these information. be able to.

According to the configuration of the seventh aspect of the present invention, the layout of the data path portion of the circuit can be optimized in consideration of both the block area and the operation speed.

According to the structure of the eighth aspect of the present invention, since the operation speed of the block is taken into consideration when optimizing the shape of the block, an optimum shape can be obtained in terms of both the area of the block and the operation speed. Can be

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a configuration of a register transfer level design support apparatus according to an embodiment of the present invention will be described with reference to the drawings. The register transfer level design support device supports a circuit design in which a data path portion and a control portion of a circuit are designed as independent blocks on a layout at a register transfer level.

FIG. 1 shows the register transfer level design support apparatus. In FIG. 1, the register transfer level design support apparatus includes a plurality of library estimating means 10 provided corresponding to the data path section of the circuit. Layout design method description means 20a to 20c and data path unit performance estimation means 30a to 30c are provided. One library estimating means 10 defines one basic circuit group consisting of a plurality of basic circuits for realizing the same operation between registers with different areas and operating speeds. A library including a basic circuit group is defined. The layout design method description means 20a to 20c describe different layout design methods in the data path unit performance estimation means 30a to 30c, respectively. The data path section performance estimating means 30a to 30c aim at supporting the design of the data path section of the circuit, and are characterized in that they are provided individually for a plurality of layout design methods.

Data path section performance estimating means 30a-30c
Are provided with display screens 40a-40c with interrupt inputs, respectively, and data path unit performance estimating means 30a-30c.
Accepts interactive designations regarding the design of the data path unit from the display screens 40a to 40c with interrupt inputs. For example, the specification of the arrangement of the function, the specification of whether the wiring is realized by a bus or a multiplexer, and the specification of whether or not to insert a latch before and after the function are accepted. The display screens with interrupt input 40a to 40c have a function of displaying the estimated values of the area and the operation speed calculated by the data path unit performance estimating means 30a to 30c, respectively.

Further, the register transfer level design support apparatus has an estimation selecting means 60, and any one of the data path section performance estimating means 30a to 30c is provided with the estimation selecting means 60.
The expected shape and timing information of the data path block are transferred from the selected data path unit performance estimating means to the floor plan optimizing means 80.

The floor plan optimizing means 80 includes the arranging means 8
1, a wiring means 82 and a shape optimizing means 83, and a display screen 90 with an interrupt input is provided corresponding to the floor plan optimizing means 80. The arrangement means 81
The arrangement of the blocks is controlled, and the blocks are arranged based on the arrangement command or the automatic optimization command given from the display screen 90 with the interrupt input. The wiring means 82 performs wiring between the blocks and arrangement of the pins. The shape optimizing means 83
For the purpose of optimization in consideration of both the timing and the area, block selection using the estimation selection means 60 and optimization of the block shape are performed.

The estimation selecting means 60 is controlled by a signal from the floor plan optimizing means 80, and the selection of the data path performance estimating means 30a to 30c can be freely switched. In addition, the register transfer level design support device
A plurality of library estimating means 110 provided corresponding to the control unit of the circuit, layout design method description means 120a to 120c, and control unit performance estimating means 50
a to 50c, and the control section estimating means 5
The display screens 14 with interrupt input are respectively displayed on 0a to 50c.
0a to 140c are provided. Further, the register transfer level design support device includes dedicated function performance estimating means 70a to 70c provided corresponding to dedicated functions such as a miscellaneous circuit, a ROM, and a RAM.

Control section performance estimating means 50a-50
c and dedicated function performance estimating means 70a to 70c
Are coupled to the estimation selection means 60, and are selected by the estimation selection means 60 in the same manner as the data path section performance specification means 30a to 30c.

Next, a circuit design method using the register transfer level design support device configured as described above will be described.

FIG. 2 is a flow chart showing the circuit design method. The register transfer level design support device is used in steps S2, S3, S4 and S5 of FIG.

As shown in FIG. 2, first, in the register transfer level design in step S1, an arithmetic unit is defined corresponding to each operation, and design data is transferred between registers and the order control between them. And a part. The data transfer between the registers is collectively treated as a data path block. On the other hand, the control part is represented by a finite state machine.

Next, steps S2, S3, S4 and S5
Thus, circuit design at the register transfer level using the register transfer level design support device is supported.

In response to the design of the data path section of the circuit, in step S2, for example, a library is provided to the data path section performance estimating section 30a by the plurality of library estimating sections 10, and the data is transmitted from the layout design scheme description section 20a. The layout design method is provided to the path performance estimating means 30a. Then, the data path unit performance estimating means 30
(a) performs a schematic design of a layout in a data path block using the library and the layout design method as a block realizing method of a data path unit. Next, in step S3, the data path unit performance estimating unit 30a estimates the area and operation speed of the data path unit based on the layout designed in step S2. Similarly, according to the design of the control section of the circuit, for example, the control section performance estimating means 50a estimates the area and operation speed of the control section, and, for example, the dedicated function performance estimating means 70a corresponds to the dedicated function. Estimate the area and operating speed of the part.

In step S4, the floor plan optimizing unit 80 receives the expected shape and timing information of the block from the data path unit performance estimating unit 30a, the control unit performance estimating unit 50a and the dedicated function performance estimating unit 70a, and The layout of the entire circuit is roughly designed by arranging the arrangement, wiring between blocks, and pins.

Data path section performance estimating means 30a-30
c, the control section performance estimating means 50a to 50c and the dedicated function performance estimating means 70a to 70c respectively provide a plurality of block realizing methods and their estimation results. For this reason, the floor plan optimizing unit 80 selects one of the data path unit performance estimating units 30a to 30c, one of the control unit performance estimating units 50a to 50c, and the dedicated function performance estimating units 70a to 70c.
By changing any selection of 0c through the estimation selecting means 60 and repeating steps S2, S3 and S4, it is possible to compare and examine a plurality of block realization methods and their estimation results. As a result, the floor plan optimizing unit 80 performs optimization of the block shape in consideration of both the clock and the area, which are the operating speed of the entire circuit. Then, in step S5, it is determined whether or not such circuit optimization is completed. When the optimization is completed, that is, when the schematic design of the entire circuit is completed, the process proceeds to step S6.

Each block is developed into a logic gate by the logic level design in step S6, the schematic design of the layout at the register transfer level is improved in step S7, and the LSI mask pattern is determined in step S8 to complete the layout design. .

As described above, in the register transfer level design support apparatus according to the present embodiment, the plurality of library estimating means 10 include the data path section performance estimating means 30a to 30.
b to give a library and layout design method description means 2
0a to 20c are data path unit performance estimating means 30 respectively.
Different layout design methods are given to a to 30b, and the data path unit performance estimating means 30a to 30b design the outline of the layout in the data path block using the library and the layout design method as the block realization method. Then, similarly, the data path section performance estimating means 30a to 30b
Estimates the area and operation speed of the data path section based on the designed layout. Here, in estimating the area and the operation speed, for example, various layout design methods such as a standard cell method, a gate array method, a module synthesis method, and handcraft can be considered, so that the accuracy of the estimation result can be improved. it can.

Further, the floor plan optimizing means selects a plurality of data path block realizing methods and control block realizing methods based on the restriction of the operation speed of the entire circuit, and selects these block realizing methods and their estimation results. By comparing and studying, the block shapes of the data path portion and the control portion of the circuit can be optimized, so that the schematic layout of the entire circuit can be designed.

Further, the floor plan optimizing means 80 compares and examines a plurality of different block realizing methods and their estimation results, thereby optimizing both the area of the entire circuit and the operation speed. The design can be performed under accurate timing conditions taking the layout into consideration. Here, even if a process or cell library is given later,
The design can be advanced by using the drive capability of the transistor, the wiring width, and the like as parameters, and when the process is given, these parameters can be fixed, and at the same time, the rough design of the chip can be completed.

The register transfer level design support apparatus according to the present embodiment has an innovative configuration as compared with the conventional one, and is very effective in optimizing the system design and compatibility with the user.

Next, details of each means of the register transfer level design support device according to the present embodiment will be described.

(User Interruption Mechanism) The user interruption mechanism of the register transfer level design support apparatus according to this embodiment will be described below.

Each means of the register transfer level design support device is of an event-activated type. That is, each means has a matrix (queue) of events, and when there is an activation command from another means, the latest event request is stored in the last column of the matrix. Each unit also has a function of issuing an event request to activate another unit as needed. Further, each means has data classified and has a list of means to be activated when each data is changed. A user interrupt is also processed as one of the event requests.

By using this event processing method, a plurality of library estimating means 10, 110, data path part performance estimating means 30a-30c, control part performance estimating means 50a-50c, and floor plan optimizing means 80 Enables a configuration in which a user interrupt is independently received from a corresponding display screen with an interrupt input.

Further, when the set conditions are changed by the user interrupt, the related means is selected and activated,
A mechanism for eliminating inconsistencies in setting conditions between data held by each means can also be realized.

According to the present embodiment, since the user can proceed with the design while being conscious of the layout in the chip, it is possible to obtain better results in both area and operation speed as compared with the conventional case. However, some users have no knowledge or experience regarding layout, and it is meaningless for such a user to display the layout on the screen or to modify the layout through the screen.

For a user who has little knowledge and experience of such a layout, mainly, data expressing a method of controlling transfer between registers and a processing order thereof in a language or a diagram,
I am only interested in information on timing there and data on overall system performance. Therefore, a function of receiving a request for changing the clock speed of the system, a request for changing the delay time, and the like, and optimizing in the background layout information that greatly affects the delay time such as a floor plan according to the request for change is provided.

In order to realize this function, the delay time information for each data path is displayed to the user, the user's delay time improvement request is accepted, and the library estimating means 10, 110, Data path section performance estimating means 30a-30c, control section performance estimating means 50a
To 50c and the floor plan optimizing means 80 are further provided with a function of generating a delay time improvement request event.

(Library Estimating Means) The library estimating means of the register transfer level design support apparatus according to the present embodiment will be described below.

The library estimating means 10 is intended to provide the data path section performance estimating means 30a to 30c with information on cell area and operation speed. Similarly, the library estimating unit 110 includes the control unit performance estimating unit 5.
The purpose is to give information of the cell area and the operation speed to 0a to 50c.

A plurality of library estimating means 10 and 110
Therefore, even when a cell library is not prepared, information about the cell area and the operation speed can be estimated, so that not only at the register transfer level but also at the high level and the logic level, the chip and block areas, the operation speed, This is an effective means for estimating timing and the like.

Hereinafter, the library estimating means 10 will be described with reference to the drawings, but the same applies to the library estimating means 110.

FIG. 3 shows the library estimating means 10. In FIG. 3, the library estimating means 10 comprises a plurality of abstract gate circuit structure templates 11, a technology defining means 12, and an area / operating speed estimating means 13. And a template selecting means 14.

Abstract Gate Circuit Structure Template 11
Describes the connection of logic gates at an abstract level independent of manufacturing technology in a bit-expandable form. For example, a 10-input AND operation is represented by one abstract gate. When this is actually manufactured, it is necessary to increase the number of stages by a combination of two-input AND operation.

The template selecting means 14 is provided with a display screen 15 with an interrupt input as a means for displaying and modifying the abstract gate circuit structure template 11, so that the user can add another function to the same function if necessary. It is also possible to register an abstract gate circuit.

The technology definition means 12 includes a conversion rule for replacing the abstract gate circuit with an actually usable form in consideration of the manufacturing conditions, a delay time calculation formula determined by the manufacturing technology, and a gate layout layout. It holds information such as the percentage of the wiring portion. Specifically, a transistor circuit in the gate, the number and number of transistors, a delay calculation formula depending on the W / L of the transistor, a wiring portion ratio in the cell, a design rule, and the like are registered. Here, the W / L of the transistor is a parameter indicating the drive capability of the transistor, and the larger the value, the faster the signal can be propagated. L is the length of the transistor, W is the width of the transistor,
Normally, L is set to the minimum width of the design rule, so W
Only changes. Therefore, in order to speed up signal propagation, it is necessary to increase W, that is, to increase the size (area) of the transistor.

The area / operating speed estimating means 13 receives a plurality of abstract gate circuit structure templates 11 from the template selecting means 14 and, from the technology defining means 12, calculates the delay time determined by the manufacturing technology and lays out the gates. In this case, information such as the ratio of the wiring portion occupied is received, and the relationship between the area and the operation speed is obtained for a plurality of cell realization methods.

The procedure for activating the library estimating means 10 configured as described above will be described.

The following signals are input to activate the library estimating means 10.

Function name Number of bits First, the template selection means 14 selects a plurality of abstract gate circuit structure templates 11 of cells corresponding to the function indicated by the function name. For example, for the adder function, an abstract gate circuit such as a carry look-ahead adder or a ripple carry adder (a bit-expandable manufacturing technology-independent gate circuit) is selected.

Next, referring to the technology definition means 12,
Replace the abstract gate circuit with an actual transistor circuit (or a representation of the number of transistors and the number of stages). In the case of a multi-input gate, the inside of the gate is multi-staged to cover many fan-ins depending on the number of bits.

Next, the technology definition means 12 calculates the gate area and the operating speed based on the number and number of transistors, the delay calculation formula, and W / L. Thus, the gate area and the operation speed are expressed using W / L as a parameter.

Next, for each abstract gate circuit of the abstract gate circuit structure template 11 selected by the template selecting means 14, the cell is determined by using the gate area and the operating speed obtained by the technology defining means 12. The area and the operation speed are estimated. Here, the operating speed of the cell is
A delay value of a critical path (a path having the longest delay time) on the gate circuit. The area of the cell is a value obtained by multiplying the sum of the gate areas by α. Here, α is a value depending on the number of usable wiring layers, and is represented by α = (1 + wiring portion ratio).

FIG. 4 shows an area / operating speed trade-off curve of an output example when an adder is considered as a function. As an adder configuration, an abstract gate circuit structure template 11 of a carry look ahead adder and a ripple carry adder is registered, and there is a trade-off with respect to each of them by a change in W / L.

(Layout Design Method Description Means) The layout design method description means of the register transfer level design support apparatus according to this embodiment will be described below. Here, the layout design method description means 20a will be described, but the layout design method description means 20b, 20c, 120a-12
0c is the same. .

The layout design method description means 20a is a means for describing rules related to layout design. The contents described are as follows.

Wiring method Number of wiring layers or possibility of wiring on cells Wiring switching unit realization method Cell type (custom, pin movable cell, standard cell, etc.) Example of actual data path layout design method Is shown below.

Custom Layout (Manual Design) Basically, when performing manual design, the layout style is free, but the following method is generally adopted. Although the area of the cell is determined by the circuit used, the shape (aspect ratio) and the pin position can be freely set. For this reason, the number of tracks required for wiring in the cell row direction may be ensured for the channel between cell rows.

Module Synthesis There are various types of module synthesis, and they are classified into a channel wiring system and a pin alignment system. In the case of the channel wiring method, no effort is made to adjust the pin positions of the cells. The functions are arranged in each cell row, and the cells obtain area and speed data from a library prepared in advance. When the pin alignment method is used, the cell has a function of adjusting the pin position. However, unlike the custom design, the width of the cell increases to adjust the pin position. The increment is equal to the sum of the pin position movement distances. Assuming that the order of arrangement of pin sets to be connected in adjacent cell rows is the same, the sum of the difference in distance between adjacent pins is the cell width increment. If the order of the pin set is reversed, wiring in the channel region is required.

Standard cell method Basically, a combination of standard cells (in some cases,
Macro cell). There is no particular restriction that the same function be realized in the same cell row, but they are arranged in rows that are close to each other. Wiring is performed by channel wiring.

Feed-through wiring method Feed-through wiring depends on available wiring layers.
There are two cases: passing between cells and passing over cells.

In consideration of the above, each layout design method can be defined by a combination of the following classifications.

Classification by Channel Wiring and Pin Alignment Classification by Feed-through Between Cells and Pass-through on Cells Dependence on Bit Slice and Function Slice The classification data path unit performance estimating means 30a is provided with a condition switch and an estimating processing means for switching the estimation processing method of the area and the operating speed according to the following classification conditions, and the layout design method description means 20a describes these conditions. Positioned as a means. The description of the condition is expressed by the on / off state of the condition switch.

(Data Path Unit Performance Estimating Means) The data path unit performance estimating unit of the register transfer level design support apparatus according to the present embodiment will be described below. Here, the data path section performance estimating means 30a will be described with reference to the drawings, but the data path section performance estimating means 30b and 30c are similar.

FIG. 5 shows the data path section performance estimating means 30a. In FIG. 5, the data path section performance estimating means 30a includes a condition switch 31, a linear arrangement means 32, a cell selecting means 33, and a channel width estimating means 34. And a cell row width estimating unit 35, a bus / multiplexer switching unit 36, a bit slice / function slice switching unit 37, and a linear arrangement optimizing unit 38. Further, a plurality of library estimating units 10 (or existing cell libraries 10) are provided corresponding to the data path unit performance estimating unit 30a.
0), a layout design method description means 20a and a display screen 40a with interrupt input are provided.

FIG. 6 shows an example of a layout model used for estimation, which is a layout according to a custom system when a wiring cannot pass through a cell.

In FIG. 6, reference numeral 301 denotes a cell, 302 denotes a cell row, 303 denotes a feedthrough, 304 denotes a channel,
05 indicates an external pin of the block.

The operation of each means of the data path section performance estimating means 30a will be described below.

The linear arrangement means 32 initializes the arrangement of functions. Further, if necessary, it is also possible to perform automatic linear layout optimization aiming at minimizing the area or maximizing the operation speed. Details of the automatic linear arrangement optimization will be described later.

Cell selection means 33 From the plurality of library estimating means 10 (or the existing cell library 100) given as a precondition, the cell 301 in bit units constituting each function is taken out and stored in the designated row. The function cells 301 are arranged according to the bit arrangement. Feedthrough 3
It is also possible to perform automatic cell selection optimization for optimizing cell selection so as to make the cell width as uniform as possible in consideration of the width of the cell row 302 occupying the cell row 302.

The channel width estimating means 34 estimates the width of each channel 304 when the cell row spacing is realized by channel wiring. The number of wiring tracks of the same channel is determined based on the connection request given to the pin positions including the upper, lower, left and right feedthroughs 303 of each channel 304, and the width of the channel is determined based on the number.

In wiring the channel 304 between the cell rows, in response to a connection request above and below the channel 304,
Estimate each channel width and cell row width increment when minimizing the channel width by straightening up and down by pin alignment. When the custom layout method is used, that is, when the size of the cell 301 is obtained from the library estimating unit 10a, the cell shape and the pin position can be flexibly changed, so that the cell width does not increase.

In the case of the module synthesizing method and the cell adopts the pin alignment method, the cell has a function of adjusting the pin position. However, unlike the custom design, the width of the cell increases to adjust the pin position. The increment is equal to the sum of the pin position movement distances. Assuming that the order of arrangement of pin sets to be connected in adjacent cell rows is the same, the sum of the difference in distance between adjacent pins is the cell width increment. If the order of the pin set is reversed, wiring in the channel region is required. For the channel width, the number of wiring tracks is determined by a line that has a wiring request in the horizontal direction with respect to the channel 304 (for example, a control line) and a horizontal track generated by a failure in pin alignment, and the width of the channel 304 is determined based on the number. .

Cell row width estimating means 35 When feedthrough above a cell is prohibited,
The width required to pass through the feedthrough wiring is added to the cell row width, and the value is defined as the cell row width.

Bus / multiplexer switching means 36 A bus and a multiplexer are necessary when one wiring resource is shared or switched and used, but each is realized by a tri-state buffer for each bit or a cell of a multiplexer. Therefore, the linear arrangement means 32, the cell selection means 33, the channel width estimation means 34, and the cell row width estimation means 35 are activated by providing a cell row including necessary cells in necessary parts of the bus and the multiplexer.

Linear arrangement optimizing means 38 The linear arrangement optimizing means 38 is a means for performing linear arrangement of functions in a data path.

FIGS. 7A and 7B show data to be handled and an abstracted model. In FIG. 7, reference numeral 401 denotes functions (F1 to F4), and reference numeral 402 denotes wiring between the functions. .

The height H is given as the sum of the sum of the cell heights and the sum of the channel heights. By swapping cell rows,
Since the number of feedthroughs in each cell row changes, the value of W changes. Further, since the wiring length before and after each function also changes, the operation speed S of the data path unit also changes.

The difference between the abstract model shown in FIG. 7A and the abstract model shown in FIG. 7B is that the positions of the functions F2 and F3 are interchanged. In FIG. 6A, the width W
Is 120, and the width W is 130 in FIG. Also,
The operating speed S depends on the capability of the driving transistor and the wiring length.

The data path linear layout method of the linear layout optimization means 38 aims at minimizing the objective function given by the functions of W, H and S, and repeatedly changing the cell rows to change the value of the evaluation function. How to optimize. As a method of optimization, a known simulated annealing method or the like can be used.

(Shape Optimizing Means) Hereinafter, the shape optimizing means 83 of the register transfer level design support apparatus according to this embodiment will be described.
Will be described.

The purpose of the shape optimizing means 83 is to determine a combination of shapes having a minimum area that satisfies the condition when a speed constraint is given.

Blocks such as data paths and controls used in LSI design have different areas depending on the speed. Furthermore, for each speed (delay time),
The vertical and horizontal sizes are not uniform and may take a plurality of shapes.

At the register transfer level, it is the clock cycle that determines the performance of the system. When the clock cycle is determined, the minimum operation speed (maximum delay) required for each block included in the system is determined. Based on the condition, all the possible vertical and horizontal sizes of each block can be listed.

The vertical and horizontal sizes are plotted on XY coordinates, and two arbitrary points A (x1, y1) and B (x2, y2)
When the relationship of x1 <x2 and y1 <y2 is satisfied, the removal of the point B is repeated, whereby the set of remaining points is defined as the shape function of the block, and the conventional shape optimization without considering the speed The method is used to optimize the shape.

The conventional shape optimizing method only has the object of minimizing the area or the object of optimizing only the delay related to the wiring length. However, in the shape optimizing unit 83, the operation speed of the entire circuit is also taken into consideration, and an optimum solution can be obtained in both the area and the operation speed.

[0109]

As described above, according to the register transfer level design support apparatus according to the first to eighth aspects of the present invention, the area and the operation speed of the data path portion of the circuit are estimated in consideration of the layout design method. Therefore, the accuracy of the estimation result can be improved. Further, the block shape can be optimized in consideration of both the area and the operation speed of the entire circuit, and the design can be performed under accurate timing conditions in consideration of the layout.

Further, according to the register transfer level design support apparatus of the present invention, it is possible for the user to interrupt the estimation of the block area and the operation speed, and each interrupt means can specify the user for circuit synthesis. The estimation accuracy can be improved by performing the estimation on the assumption of the designated information.

According to the register transfer level design support apparatus according to the third aspect of the present invention, the general layout can be optimized in the background without the user being conscious of the layout at all.

According to the register transfer level design support apparatus according to the fourth aspect of the present invention, even when a cell library is not provided, information on the cell size and operation speed is provided, and the block and chip information is provided using the information. The area and the operation speed can be estimated.

According to the register transfer level design support apparatus of the present invention, the layout of the data path portion of the circuit can be optimized in consideration of both the area of the block and the operation speed.

According to the register transfer level design support device of the present invention, the operation speed of the block is taken into consideration when optimizing the shape of the block. An optimal shape is obtained in terms of point.

As described above, according to the present invention, at the register transfer level of the circuit design, the layout can be roughly designed simultaneously with the estimation, so that the estimation accuracy can be greatly improved. Further, it is possible to minimize design rework such as proceeding to the detailed layout design and returning to the register transfer level design, and it is possible to greatly reduce the time required for the circuit design process.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a register transfer level design support device according to one embodiment of the present invention.

FIG. 2 is a flowchart showing a circuit design method using the register transfer level design support device.

FIG. 3 is a block diagram showing library estimating means of the register transfer level design support device.

FIG. 4 is a graph showing a trade-off curve between an adder function area and an operation speed.

FIG. 5 is a block diagram showing a data path unit performance estimating means of the register transfer level design support device.

FIG. 6 is a diagram showing a layout model used for estimation by the data path unit performance estimation means.

FIG. 7 is a diagram illustrating an abstraction model of a function linear arrangement.

FIG. 8 is a flowchart showing a conventional circuit design method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Library estimation means 11 Abstract gate circuit structure template 12 Technology definition means 13 Area / operation speed estimation means 14 Template selection means 15 Display screen with interrupt input 20a-20c Layout design method description means 30a-30c Data path section performance estimation means 31 Condition switch 32 linear arrangement means 33 cell selection means 34 channel width estimation means 35 cell row width estimation means 36 bus / multiplexer switching means 37 bit slice / function slice switching means 38 linear arrangement optimization means 40a-40c display screen with interrupt input 50a -50c Control section performance estimating means 60 Estimation selecting means 70a-70c Dedicated function performance estimating means 80 Floor plan optimizing means 81 Arranging means 82 Wiring means 83 Shape optimizing means 90 interrupt input with the display screen 100 cell library 110 library estimator 120a~120c layout design method described means 140a~140c interrupt input with the display screen 301 cell 302 cell row 303 feed through 304 channel 305 external pin 401 Function 402 function between the wires

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-250437 (JP, A) JP-A-4-247575 (JP, A) JP-A-3-182969 (JP, A) JP-A-3-182969 95679 (JP, A) JP-A-64-82544 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50

Claims (8)

(57) [Claims] 1. A register transfer level design support device for supporting a circuit design in which a data path portion and a control portion of a circuit are designed as independent blocks on a layout at a register transfer level. A plurality of library estimating means for generating a basic circuit group consisting of a plurality of basic circuits for realizing the above operation with different areas and operation speeds; and a plurality of layout design method description means for supplying different layout design methods. A combination of a library including a plurality of the basic circuit groups and any one of the plurality of layout design methods is selected as a data path block realization method, and the data is selected based on the selected data path block realization method. Multiple data paths for estimating path area and operating speed Unit performance estimating means, a plurality of control unit performance estimating means for estimating the area and operation speed of the control unit based on different control block realization methods, and a plurality of control unit performance estimating units based on constraints on the operation speed of the entire circuit. The data path block realizing method and the plurality of control block realizing methods are selected, and the data path unit and the control unit are selected based on the selected plural data path block realizing methods and the plurality of control block realizing methods. And a floor plan optimizing means for optimizing the block shape of the register. 2. A plurality of library estimation result display means each provided corresponding to each of the plurality of library estimation means and displaying the estimation result of the corresponding library estimation means; A plurality of data path section performance estimation result display means provided corresponding to each of the path section performance estimation means and displaying the estimation results of the corresponding data path section performance estimation means; A plurality of control section performance estimation result display means provided corresponding to each of the means and displaying the estimation result of the corresponding control section performance estimation means; and the optimization result provided corresponding to the floor plan optimization means. A floor plan optimization result display means to be displayed, each of which corresponds to each of the plurality of library estimation means. A plurality of library estimating interrupt means provided for receiving a user interrupt of the corresponding library estimating means; and a corresponding data path part performance estimating means provided corresponding to each of the plurality of data path part performance estimating means. A plurality of data path section performance estimating interrupt means for receiving a user interrupt of the means; and a plurality of data path section performance estimating means each corresponding to each of the plurality of control section performance estimating means for receiving a user interrupt of the corresponding control section performance estimating means. Control section performance estimating interrupt means, and floor plan optimizing interrupt means provided corresponding to the floor plan optimizing means for receiving a user interrupt, wherein the plurality of Library estimation means, multiple Data path section performance estimating means, a plurality of control section performance estimating means and a floor plan optimizing means, by selecting and activating the means relating to the changed setting conditions, the plurality of library estimating means, the plurality of 2. The register transfer level according to claim 1, wherein the register transfer level is configured to eliminate inconsistencies in setting conditions among the data path unit performance estimating unit, the plurality of control unit performance estimating units, and the floor plan optimizing unit. Design support equipment. 3. A display means for displaying a delay time required for inter-register transfer and control thereof, data expressed in a language or a diagram for a control method of inter-register transfer and processing order, and an operation speed of the entire circuit. Interrupting means for accepting a request to change the operating speed of the entire circuit and a request to change the delay time as a user interrupt, wherein the plurality of library estimating means and the plurality of data path unit performance estimating means are provided by the user interrupt. And activating a plurality of control section performance estimating means and floor plan optimizing means to perform optimization in consideration of both the circuit area and the operation speed. 2. The register transfer level design support device according to 1. 4. The method according to claim 1, wherein each of the plurality of library estimating means determines an area and an operation speed of the corresponding function by using a ratio of the width W to the length L of the transistor, that is, W / L as a parameter. 2. The method according to claim 1, wherein the connection relationship is estimated using an abstract gate circuit structure template that indicates a bit-expandable configuration and information depending on a manufacturing technology for the abstract gate circuit of the abstract gate circuit structure template. Register transfer level design support device. 5. Each of the plurality of data path unit performance estimating means includes: a switch means corresponding to an on / off state corresponding to setting of a layout condition of a layout design method; and a switch means corresponding to the layout condition when the layout condition is set. Means for estimating the area and the operation speed of the data path section based on the layout design method. 2. The register transfer level design support device according to claim 1, wherein a layout condition of the system is set. 6. Each of the plurality of data path unit performance estimating means includes a switch means corresponding to an on / off state corresponding to a setting of a layout condition of a layout design method, and a switch means corresponding to the layout condition when the layout condition is set. Means for estimating the area and operation speed of the data path unit based on the data path unit, and further, means for optimizing the one-dimensional arrangement of the function cells when arranging the function cells in one row, and realizing the wiring by a bus or a multiplexer. 2. The register transfer level design according to claim 1, further comprising at least one of a means for optimizing a method for realizing the data transfer and a means for estimating a data transfer speed and a block area. Support equipment. 7. Each of the plurality of data path unit performance estimating means, when arranging one or a plurality of cells in each cell row, determines a width of a cell included in each cell row and a width of a feedthrough wiring. The sum is defined as the width of the cell row, the maximum width of the widths of all the cell rows is defined as the block width W, the sum of the cell heights is defined as the block height H, and the delay time required for data transfer between registers is calculated. The maximum value is set to the operation speed S of the block, and the change of the arrangement of the cell rows is sequentially repeated to minimize the evaluation function defined by the functions of the width W, the height H and the operation speed S in the block. 2. The register transfer level design support device according to claim 1, wherein optimization of the linear arrangement is performed. 8. The floor plan optimizing means obtains, for each block, a constraint on the operation speed of the block based on a constraint on the operation speed of the entire circuit, and realizes a block that satisfies the constraint on the operation speed of the block. enumerating a combination of methods and block shape, the serial to claim 1, characterized in that selecting a combination of the block implementation and the block shape of each block so that the area of the whole circuit is minimized
Mounting of the register transfer level design support apparatus.