JPH07288253A - Flattening of insulating film - Google Patents

Abstract

PURPOSE:To form an almost completely flat interlayer insulating film which has an excellent burying property by etching back by CMP an insulating film formed by CVD or SOG using an organic silicon compound as a raw material. CONSTITUTION:A BPSG film 12 is deposited on a semiconductor wafer 11 by atomospheric CVD and then the substrate is heat-treated and an interconnection 13 is formed on the semiconductor substrate. Nextly, an NSG film 14 is formed by plasma CVD and an NSG film 25 is deposited on the NSG film 14. After that, an NSG film 34 is deposited on the NSG film 25 and an Si oxide film 44 is deposited on the NSG film 34. Then, the Si oxide film 44 and the NSG film 34, formed on a projecting section of the substrate is etched back. By this method, an almost completely flat interlayer insulating film which has an excellent burying property can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of flattening an insulating film of a semiconductor device, and more particularly to a method of flattening an interlayer insulating film provided between successive metal wiring layers of an integrated circuit semiconductor device.

[0002]

2. Description of the Related Art In a recent miniaturized semiconductor integrated circuit, wirings made of polycrystalline Si, Al alloy or the like are laminated via an interlayer insulating film made of an insulating material such as SiO ₂ .
The interlayer insulating film is formed on the semiconductor substrate having the unevenness formed by the wiring formed in the lower layer. Therefore, if the insulating film is simply deposited on the substrate, unevenness similar to that of the substrate is also formed on the surface of the insulating film. Further, fine wiring cannot be formed on the interlayer insulating film.

In order to perform such flattening, an insulating film formed on a substrate having irregularities is subjected to plasma etching or
Chemical-mechanical polishing,
A method of etching back by a process such as CMP) is used. Particularly, when the CMP process is used, the planarization can be performed almost completely.

On the other hand, a method of forming an insulating film having a high embedding property, in which minute wirings are completely filled with an insulating film, is required, and tetraethylorthosilicate (tetraethylorsilicate) is required.
thosilicate (hereinafter referred to as TEOS) or other chemical vapor deposition method using an organic silicon compound as a raw material.
An insulating film forming method using ion (hereinafter referred to as CVD) is used. Especially, atmospheric pressure CV using TEOS and ozone (hereinafter referred to as O ₃ ) as raw materials
D (hereinafter referred to as “AP CVD”) has an extremely high embedding property, for example, H. Kotani et al. Tech.
nical Digest of International Device Meeting, p.66
9, 1989.

However, this insulating film has a problem that it depends on the base, that is, the deposition rate varies depending on the material of the base (lower layer). In order to eliminate this background dependency,
First, an insulating film is deposited by a plasma CVD method, and then TEOS
A method of depositing an insulating film by atmospheric pressure CVD using strontium and O ₃ as raw materials is disclosed in the Kotani document, and the surface of the insulating film deposited by the plasma CVD method is treated with N ₂ plasma. Method is K. Fujino et al. J. Electroch
em. Soc., Vol. 6, June 1992 pp.1690-1692.

Further, a method in which the surface of the substrate is treated with an organic solvent such as ethanol to improve the embedding property and film quality of an insulating film formed by CVD using an organic silicon compound as a raw material is characterized by the applicant's application. Wishhei 5-52412
No. specification.

Furthermore, a method of forming an insulating film by applying a solution of an insulating film substance or a precursor thereof and then performing heat treatment at an appropriate temperature, so-called spin on glass (hereinafter referred to as S
The method called OG) is also known as an insulating film forming method having excellent embedding properties. For example, U.S. Pat. No. 4,775,550 shows a method of planarizing an insulating film by etch back using SOG and plasma etching.

[0008]

In order to form an interlayer insulating film by flattening by etching back, first, an insulating film is formed by a method having a high embedding property so as to completely fill fine wiring. It is necessary to. When the insulating film formed in the state where the filling property is insufficient and there are voids between the wirings is etched back by CMP treatment, cracks may be generated from the voids during CMP treatment, resulting in insulation failure or CMP treatment. The strong alkaline slurry used for remains in the voids, causing wiring corrosion. But,
There is no example in which an insulating film formed by a method having excellent embedding property such as CVD or SOG using an organic silicon compound as a raw material is etched back by CMP to flatten the insulating film.

When etching back is performed using the CMP method, it is necessary to use an etching stop in order to compensate for the lack of controllability of the etching amount, as disclosed in US Pat. No. 5,169,491. Required. For example, US Pat. No. 5,169,491 and S. Kishii et al., Extende
d Abstracts of the 1993 International Confere nce
on Solid State Devices and Materials, Makuhari, 19
93, pp.189-191, a SiO ₂ film is used as an etching stop to produce borophosphos glass.
ilicate glass (hereinafter referred to as BPSG) film is disclosed. US Pat. No. 4,944,936 discloses a method of etching a Si ₃ N ₄ film as an etching stop.
A method of etching back an io ₂ film is disclosed in US Pat. No. 5,246,884.
A method of etching back a SiO ₂ film using a mond-like carbon) film as an etching stop is disclosed.

However, a suitable etching stop material for etching back the insulating film formed by CVD using the above-mentioned organosilicon compound as a raw material or by coating with a solution of an insulating substance or its precursor by the CMP method is obvious. Was not done.

The object of the present invention is to solve the above-mentioned drawbacks and to improve the embedding property by using a CVD method using an organic silicon compound as a raw material.
A method of flattening an insulating film is provided by etching back an insulating film formed by the SOG method or the SOG method by CMP processing to form an almost completely flat interlayer insulating film having excellent embedding property. There is.

Another object of the present invention is to provide a method of planarizing an insulating film excellent in controllability by using an etching stop suitable for etching back the insulating film formed by the above method by CMP processing. It is in the field.

[0013]

According to the method of flattening an insulating film of the present invention, a semiconductor substrate is provided, wiring is formed on the surface of the semiconductor substrate, and an organic film is formed on the surface of the semiconductor substrate having the wiring formed thereon. An insulating film is formed by a CVD method using a silicon compound as a raw material or an SOG method, and at least a part of the insulating film formed on the convex portion of the substrate is etched back by a CMP process to flatten the insulating film. It is characterized by doing so.

[0014]

According to the method of flattening an insulating film of the present invention, a semiconductor substrate is provided, a wiring is formed on the surface of the semiconductor substrate, and an organosilicon compound is used as a raw material on the uneven surface of the semiconductor substrate on which the wiring is formed. To form an insulating film by applying a solution of an insulating substance or its precursor, and etch back at least a part of the insulating film formed on the convex portion of the substrate by CMP. It is characterized by doing so. This makes it possible to form an almost completely flat interlayer insulating film having excellent embedding properties.

In a preferred example of the present invention, a film having a slower CMP etching rate than the insulating film is provided below or above the insulating film or on the wiring metal film, and the CM is used.
CMP treatment is performed by using a film having a low P etching rate as an etching stop. Therefore, according to the present invention, the insulating film is flattened by using an etching stop suitable for etching back by the CMP process, whereby the lack of controllability of the CMP process is solved, the film quality is good, and the embedding property is excellent. Moreover, an almost completely flat interlayer insulating film can be formed.

In a preferred example of the present invention, the film having a low etching rate is formed by depositing either a silicon oxide or a silicon oxynitride by a CVD method using an inorganic silicon compound as a raw material.

In another embodiment of the present invention, a step of applying a solution of an insulating film substance or its precursor is included before the step of performing the surface treatment with the organic solvent.

In a preferred example of the present invention, before the step of forming the insulating film, a step of subjecting the surface of the semiconductor substrate having irregularities to a surface treatment with an organic solvent is further included.

Further, the insulating film is formed by CVD using TEOS as a raw material, or by CVD using TEOS and O ₃ as raw materials.

Further, the insulating film is made of TEOS and O ₃
Is formed by CVD using as a raw material, and the surface treatment of the substrate is performed using an organic solvent containing ethanol.

The substrate is formed so as to include a step of processing a laminated film in which a film having a low etching rate is deposited on a metal film containing any of aluminum, copper and gold into a required pattern. To do.

The insulating film is formed after forming the film having a low etching rate on the substrate.

Further, the film having a low CMP etching rate is formed after forming the insulating film.

Examples of the organic compound which is the organic solvent containing ethanol include aliphatic saturated monohydric alcohols, aliphatic unsaturated monohydric alcohols, aromatic alcohols, aliphatic saturated polyhydric alcohols and their derivatives, and aldehydes. ,
Examples thereof include ethers, ketones / keto alcohols, carboxylic acids, nitroalkanes, amines, acyl nitrites, acid amides, and heterocyclic compounds, and the following substances can be specifically used. Aliphatic saturated monohydric alcohols: methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, 2-methyl-1-propanol, 2-butanol, 2-methyl-2-propanol, 1-pentanol, 3 -Methyl-1-butanol, 3-methyl-2-butanol, 2-methyl-2-butanol, 1-hexanol, cyclohexanol Aliphatic unsaturated monohydric alcohols: allyl alcohol, propargyl alcohol, 2-methyl-3 -Butin-2-ol aromatic alcohols: benzyl alcohol, furfuryl alcohol, aliphatic saturated polyhydric alcohols and their derivatives: ethylene glycol, propylene glycol, diethylene glycol, ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, Tylene glycol mono-n-butyl ether, ethylene glycol monoisobutyl ether, propylene glycol monomethyl ether, ethylene glycol dimethyl ether, diethylene glycol monomethyl ether, diethylene glycol monoethyl ether, diethylene glycol dimethyl ether Aldehyde: formaldehyde, acetaldehyde, glyoxal ether: diethyl ether, dioxane, tetrahydrofuran, tetrahydroflur Furyl alcohol ketone
Keto alcohol: acetone, 2-butanone, diacetone alcohol, γ-butyrolactone, propylene carbonate carbonate: formic acid, acetic acid, propionic acid, glycolic acid, lactic acid, ethyl lactate nitroalkane: nitromethane, nitroethane, nitropropane, nitrobenzene amine: ethylamine, Propylamine, isopropylamine, butylamine, isobutylamine, allylamine, aniline, toluidine, ethylenediamine, diethylamine, ethyleneimine, dipropylamine, diisopropylamine, dibutylamine, triethylamine,
Tri-n-propylamine, tri-n-butylamine acyl nitriles: acetonitrile, propiononitrile, butyronitrile, acrylonitrile, methacrylonitrile, benzonitrile Acid amide: formamide, N-methylformamide,
N, N-dimethylformamide, N-methylacetamide, N, N-dimethylacetamide, heterocyclic compound: pyridine, quinoline, pyrrole, piperidine, piperazine, morpholine, 2-pyrrolidinone,
1-Methyl-2-pyrrolidinone However, lower alcohols and acetylene alcohols are particularly preferable.

However, it was confirmed that the best film quality and embedding property were achieved when the insulating film was formed by the atmospheric pressure CVD using TEOS and O ₃ as raw materials by performing the treatment using ethanol.

The following compounds can be used as the organosilane compound, which is an organosilicon compound containing TEOS. Organic silane Tetraalkoxysilane (orthosilicate ester): tetramethoxysilane, tetraethoxysilane, tetra-n
Propoxysilane, tetraisopropoxysilane, tetra-n-butoxysilane trialkoxysilane: trimethoxysilane, triethoxysilane, tri-n-propoxysilane, triisopropoxysilane, tri-n-butoxysilane alkylalkoxysilane: methyltrimethoxysilane, methyltriethoxy Silane, methyl n propoxy silane, methyl isopropoxy silane, ethyl trimethoxy silane, ethyl triethoxy silane, ethyl tri n propoxy silane, ethyl triisopropoxy silane, vinyl trimethoxy silane, vinyl triethoxy silane,
Phenyltrimethoxysilane dimethyldimethoxysilane, dimethyldiethoxysilane, diethyldimethoxysilane, diethyldiethoxysilane, diethyldi-n-propoxysilane, diethyldiisopropoxysilane, methylvinyldimethoxysilane, methylvinyldiethoxysilane methyldimethoxysilane, methyldiethoxy Silane dimethyl vinyl methoxy silane, dimethyl vinyl ethoxy silane polysiloxane: tetrakis (dimethylsiloxy) silane cyclosiloxane: octamethylcyclotetrasiloxane, pentamethylcyclotetrasiloxane, tetramethylcyclotetrasiloxane, hexamethylcyclotrisiloxane, trimethylcyclotrisiloxane : Hexamethyldisiloxane, tetramethyldimethoxydisiloxane, di Chill tetramethoxy disiloxane, hexamethoxydisiloxane alkylsilane: monomethylsilane, dimethylsilane,
Trimethylsilane, triethylsilane, tetramethylsilane, tetraethylsilane allyltrimethylsilane hexamethyldisilane silylamine: dimethyltrimethylsilylamine, diethyltrimethylsilylamine silane nitrogen derivative: aminopropyltriethoxysilane trimethylsilylazide, trimethylsilylcyanide silazane: hexamethyldisilazane, tetra Methyldisilazane Octamethylcyclotetrasilazane, Hexamethylcyclotrisilazane Halogenated silanes and derivatives: trimethylchlorosilane, triethylchlorosilane, tri-n-propylchlorosilane, methyldichlorosilane, dimethylchlorosilane,
Chloromethyldimethylchlorosilane, chloromethyltrimethylsilane, chloropropylmethyldichlorosilane,
Chloropropyltrimethoxysilane dimethyldichlorosilane, diethyldichlorosilane, methylvinyldichlorosilane, methyltrichlorosilane,
Ethyltrichlorosilane, vinyltrichlorosilane, trifluoropropyltrichlorosilane, trifluoropropyltrimethoxysilane, trimethylsilyl iodide

The above-mentioned organosilane compounds can be used alone or in combination of two or more substances. When mixed and used, the mixing ratio may be appropriately adjusted.

It is also possible to mix an organic phosphorus compound such as trimethyl phosphonate to deposit a phosphosilicate glass film, or to mix an organic boron compound such as trimethyl borate to deposit a BPSG film. is there.

As the surface treatment, coating treatment of the organic compound or its aqueous solution or organic solvent solution, immersion treatment in the organic compound or its aqueous solution or organic solvent solution, or said organic compound or its aqueous solution or organic solvent solution. Examples of the exposure treatment using vapor of the above, a spray treatment, a shower treatment, and the like, and a coating treatment using a spin coater are particularly preferable.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In various embodiments of the present invention described below, a semiconductor wafer 11 is provided with a MOS (not shown).
It is assumed that structures necessary for a semiconductor integrated circuit, such as transistors and isolation oxide films, have already been formed.

Example 1 In this example, first of all, FIG.
As shown in FIG. 1, B is formed by the atmospheric pressure CVD method on the semiconductor wafer 11 on which the structure required for the semiconductor integrated circuit such as the MOS transistor and the isolation oxide film is already formed as described above.
A PSG film 12 is deposited and heat-treated at 850 ° C. to form a Ti film with a thickness of 20 nm and a Ti film with a thickness of 100 nm on the semiconductor substrate.
N film, 750 nm Al-0.5 wt% Cu alloy film, 30
A laminated metal film in which a TiN film having a thickness of 10 nm is laminated in this order on TiN is deposited by a sputtering method, and aluminum (Al) wirings 13 having various widths and intervals are formed by ordinary photolithography and dry etching techniques. Then, plasma C using TEOS and O ₂ as raw materials is formed on the surface of the plasma C.
By VD, the thickness of the flat part is 50 nm.
ed silicate glass (NSG) film (hereinafter p-TEOS)
(Referred to as NSG film) 14 is deposited. Concavities and convexities are formed on the surface of the substrate thus formed.

The surface of the substrate having such irregularities as shown in FIG. 1b is surface-treated with ethanol. Specifically, the silicon wafer is placed on a spin coater (not shown), and 30
While rotating at 00 rpm, 3 ml of ethanol is added dropwise and kept for 3 minutes to dry. Then TEO
By atmospheric pressure CVD using S and O ₃ as raw materials, N is formed under the condition that the film thickness when directly deposited on a Si substrate is 500 nm.
SG film (hereinafter referred to as O ₃ -TEOS NSG film) 25
Deposit. At this time, the O ₃ -TEOS NSG film 25
Is formed to have a film thickness of about 450 nm on dense wiring and a film thickness of about 50 nm on a flat portion where wiring is not formed.

The film forming conditions at this time are as follows. Deposition temperature 400 ℃ Deposition pressure Atmospheric pressure Nitrogen gas flow to gas bubbler 1.5 l / mi
n Constant temperature bath temperature 65 ℃ Oxygen flow rate to ozone generator 7.5 l / mi
n Ozone concentration 120 g / m ³ Carrier N ₂ 18 l / min

The O ₃ -TEOS NSG film 25 has an extremely high embedding property, so that the wiring interval is 0.3 μm, that is, even if the aspect ratio (the ratio between the wiring height and the wiring interval) is reduced to 3.0. Can be completely embedded between wirings. Note that as the film thickness of the p-TEOS NSG film 14 becomes thicker, the portion to be filled with the O ₃ -TEOS NSG film 25 becomes narrower than the wiring interval, the substantial aspect ratio increases, and the filling becomes difficult. Therefore p
The thickness of the -TEOS NSG film 14 is 150 nm or less, preferably 50 nm or less.

The pressure at the time of depositing the O ₃ -TEOS NSG film 25 can be set to the atmospheric pressure or higher or to the pressure below the atmospheric pressure. However, in order to obtain good embedding properties and good film quality, it is desirable to carry out deposition at a pressure of 600 torr or higher.

[0036] Then the thickness of the flat portion as shown in FIG. 1c is a p-TEOS NSG film 34 of 1.5 [mu] m O ₃ -T
It is deposited on the EOS NSG film 25, and Si is further formed thereon.
By plasma CVD using H ₄ and N ₂ O as raw materials,
Si oxide film (hereinafter p-
A SiH ₄ SiO ₂ film) 44 is deposited.

Next, the p-SiH ₄ SiO ₂ film 44 and p-TEOS formed on the convex portion of the substrate by CMP.
The NSG film 34 is etched back. The conditions of CMP are as follows.

Pad IC-60 slurry SC112 pressure 1.3 bar rotation speed 45 rpm

Under these conditions, the p-SiH ₄ SiO ₂ film and p-TEOS formed on the substrate having no unevenness.
Comparing the etching rates of the NSG films, the latter was about 3 times faster. Therefore, immediately after the start of CMP, a strong local pressure is applied to the convex portion, so that the p-SiH ₄ SiO ₂ film 44 formed on the convex portion is etched, and then the p-TEOS formed on the convex portion is etched. NSG film 3
4 is etched. However, the p-SiH ₄ SiO ₂ film 44 formed in the concave portion, that is, the flat portion is hardly etched. Therefore, the p-TEOS NSG film 3
4 is removed and the surface is substantially flattened, the p-SiH ₄ S having a low etching rate is removed.
Due to the presence of the iO ₂ film 44, the p-TEOS NSG film 3
4 The pressure applied to the surface weakens, and if it exceeds that, p-TEOS
The etching of the NSG film 34 also does not proceed. In the present invention, the p-SiH ₄ SiO ₂ film 44 on this flat portion is used as an etching stop. Therefore, by setting an appropriate etching time, it is possible to obtain an interlayer insulating film whose surface is flattened as shown in FIG. 1d.

Source materials other than SiH ₄ which can be used for depositing a film of Si oxide include Si ₂ H ₆ and Si ₃ H
There are inorganic silicon compounds such as ₈ . It is also possible to use a Si oxide film deposited by atmospheric pressure CVD using SiH ₄ and O ₂ as raw materials. In addition, SiH ₄ , N
By using the Si oxynitride film made of ₂ O and NH ₃ as raw materials, the difference in etching rate from the p-TEOS NSG film can be further increased and the process window can be widened.

Materials other than Si oxide and Si oxynitride that can be used as etching stoppers include Si nitride and alumina. However, since these materials have a strong stress, there is a possibility of causing a defect in the Al wiring.

Diamond-like carbon deposited by the CVD method can also be used as an etching stop, but since this material has conductivity, it needs to be removed after the planarization processing step. Furthermore, Ti, W, T
A refractory metal such as a and a refractory metal compound such as TiN, TiB, and WN can be used, but these refractory metal and refractory metal compounds also need to be removed after the planarization process.

[Embodiment 2] In this embodiment, as shown in FIG. 2A, after forming an Al wiring in the same manner as described in Embodiment 1, an SOG film 45 is formed on the Al wiring and a film thickness in the flat portion is formed. Two
It is formed to have a thickness of 0 nm. The SOG film 45 is formed by applying a 0.5 to 5% solution of silanol oligomer obtained by hydrolytically polymerizing silicate ester, and performing heat treatment at 400 ° C. for 30 minutes.

As shown in FIG. 2b, the surface of the substrate thus formed was surface-treated with ethanol, and then the thickness of the densely packed wiring was about 450 nm under the same film forming conditions as in Example 1. The O ₃ -TEOS NSG film 25 of SO
It is deposited on the G film 45. Then, as shown in FIG.
P-TEOSNSG film 3 having a flat thickness of 1.5 μm
4 is deposited on the O ₃ -TEOS NSG film 25, and p-SiH ₄ S having a thickness of 0.2 μm in the flat portion is further deposited thereon.
An iO ₂ film 44 is deposited. Then, a CMP process is performed in the same manner as in Example 1 to obtain an interlayer insulating film whose surface is planarized as shown in FIG. 2d. In this case p-Si
The H ₄ SiO ₂ film 44 serves as an etching stop.

By thus forming the SOG film 45 and treating the surface of the SOG film 45, it was possible to completely eliminate the dependency on the substrate, with extremely good reproducibility as compared with the case of the first embodiment.

The thickness of this SOG film is 150 nm or less, preferably 50 nm or less. The concentration of silanol oligomer is low, for example, 1% or less is preferable in order to form a thin SOG film with good uniformity. As a result, p-TEOS in the case of Example 1 is obtained.
The SOG film 45, which is thinner than the NSG film 14, is formed, and it becomes possible to embed finer wiring.

[Embodiment 3] In this embodiment, as shown in FIG. 3A, after the Al wiring 13 is formed as in the case of Embodiment 1, p-
The SiH ₄ SiO ₂ film 44 has a thickness of 100 at the flat portion.
to be nm. In this embodiment, this p-Si
The H ₄ SiO ₂ film 44 serves as an etching stop.

Next, as shown in FIG. 3b, this p-SiH
The surface of the ₄ SiO ₂ film 44 is surface-treated with ethanol, and the O ₃ -TEOS NSG film 25 is deposited as in the case of the first embodiment.

Then, the convex portion, that is, A
The O ₃ -TEOS NSG film 25 on the l wiring is etched back. At this, O ₃ etch rate of -TEOS NSG film is substantially the same as the etch rate of p-TEOS NSG film, the etching rate of the p-SiH ₄ SiO ₂ film thus about the etching rate of the O ₃ -TEOS NSG film It is 1/3. Therefore, p-SiH on Al wiring
_{When the 4} SiO ₂ film is exposed, etching hardly progresses, and a structure as shown in FIG. 3c is obtained. p-
If there is no SiH ₄ SiO ₂ film 44, or if p-Si
If a p-TEOS NSG film is used instead of the H ₄ SiO ₂ film 44, the etching cannot be stopped in the illustrated state, the Al wiring 13 is exposed, and as a result, A
A defect such as an increase in resistance of the l-wiring 13 and disconnection occurs. Finally, as shown in FIG. 3d, p-TEOS having a film thickness of 0.8 μm is formed.
The NSG film 34 is deposited and the interlayer insulating film forming step is completed.

In this case, the O3-TEOS NSG film 25 could be completely filled up to the wiring interval of 0.45 .mu.m. By making the p-SiH ₄ SiO ₂ film 44 thinner, even finer wiring can be embedded.
Since the film 44 has a function of stopping the etching of CMP, thinning the film 44 narrows the process window of the CMP process.

Here, instead of the p-TEOS NSG film 34, it is possible to deposit a p-SiH ₄ SiO ₂ film with the same film thickness. The p-SiH ₄ SiO ₂ film has an effect of preventing the permeation of moisture and hydrogen, and has an adverse effect due to the moisture contained in the O ₃ -TEOS NSG film 25 reaching the wiring formed on the interlayer insulating film. Can be prevented. Also, SiH ₄ and NH are used as a surface protective film on the uppermost wiring.
_{When a} Si nitride film is formed by plasma CVD using ₃ and ₃ as raw materials, it is possible to prevent adverse effects due to hydrogen contained in the Si nitride film reaching the MOS transistor formed on the surface of the Si wafer 11. it can. The p-SiH ₄ SiO ₂ film 44 is also effective for the latter,
By depositing a thicker p-SiH ₄ SiO ₂ film, a higher hydrogen permeation preventing effect can be obtained.

[Embodiment 4] Also in this embodiment, the Al wiring 1 is used.
3 is formed, a p-SiH ₄ SiO ₂ film 44 is deposited (FIG. 4a), ethanol treatment is performed, and then O ₃ -T is formed thereon.
The steps up to the deposition of the EOS NSG film 25 (FIG. 4b) are carried out in the same manner as in Example 3.

Next, as shown in FIG. 4c, the SOG film 35 is formed.
O ₃ -TEOS so that the film thickness at the flat part is 1 μm
It is deposited on the NSG film 25.

Then, etch back is performed by CMP. The etching rate of the SOG film 35 is p-TEOS N
It is close to the etching rate of SG film, and p-SiH ₄ SiO ₂
P-TEOS while maintaining the etching rate ratio with the film
It is possible to etch at almost the same rate as the NSG film. Therefore, as in Example 3, p-SiH ₄ S
The iO ₂ film 44 is used as an etch stop, Fig. 4
As shown in d, the convex portion, that is, SO on the Al wiring 13
The G film 35 and the O ₃ -TEOS NSG film 25 can be etched, and the etching can be stopped when the p-SiH ₄ SiO ₂ film 44 is exposed. In this case, CMP
The surface of the SOG film 35 in the flat portion before the start of the treatment is higher than the surface of the p-SiH ₄ SiO ₂ film 44 on the Al wiring 13 by about 150 nm, so that the concave portion, that is, the surface of the SOG film 35 in the flat portion. The part is also etched, and p on the Al wiring 13
-Etching stops when the SiH ₄ SiO ₂ film 44 is slightly lower than the surface thereof.

Finally, as shown in FIG. 4e, the film thickness is 0.8 μm.
P-TEOS NSG film 34 is deposited, and the interlayer insulating film forming step is completed. Here, the p-TEOS NSG film 34 is used.
It is also possible to deposit a p-SiH ₄ SiO ₂ film in the same thickness instead of.

Although this method has a longer process than that of the third embodiment, an interlayer insulating film having higher flatness can be obtained.

[Embodiment 5] In this embodiment, as shown in FIG. 5A, a BPSG film 12 is deposited on a semiconductor wafer 11 and subjected to heat treatment, and then, a laminated structure having the same structure as that in Embodiments 1 to 4 is formed. The metal film 13a is deposited by the sputtering method, and then p
The SiH ₄ SiO ₂ film 13b is deposited to a film thickness of 100 nm. Then, as shown in FIG. 5b, this laminated metal film 13a is formed.
And a p-SiH ₄ SiO ₂ film 13b are laminated to form a desired pattern, and p-SiH ₄ SiO ₂ 1 is formed on the upper part.
The Al wiring 13 in which 3b is laminated is formed.

Then, as shown in FIG.
P-TE so that the film thickness of the flat part is 50 nm.
After depositing the OS NSG film 14 and surface-treating the surface thereof with ethanol, an O ₃ -TEOS NSG film 25 is deposited under the same conditions as in Example 1 as shown in FIG. 5C.

Next, the convex portion, that is, O on the Al wiring 13 is formed.
_3- TEOS NSG film 25 is etched back by CMP processing. At this time, p-SiH ₄ SiO ₂ on the Al wiring 13
13b acts as an etching stopper, and etching stops in the state shown in FIG. 5d.

Finally, as shown in FIG. 5e, the film thickness is 0.8 μm.
P-TEOS NSG film 34 is deposited, and the interlayer insulating film forming step is completed. Here, the p-TEOS NSG film 34 is used.
It is also possible to deposit a p-SiH ₄ SiO ₂ film in the same thickness instead of.

P-TEOS NSG used in this method
The film 14 does not serve as an etching stop, and can be made thinner than the p-SiH ₄ SiO ₂ film 44 used in the third embodiment, so that finer wiring can be filled between the wirings. Specifically, the line spacing is 0.35μ
It was possible to completely embed up to m. However, p-SiH
_{4 As the} SiO ₂ film 13a becomes thicker, the height of the Al wiring 13 becomes higher, and the aspect ratio becomes higher even with the same line spacing.
The line spacing that can be embedded becomes wider. On the other hand, p-SiH ₄ S
As the iO ₂ film 13a becomes thinner, the effect of etching stop is reduced and the process window becomes narrower.

[Embodiment 6] Also in this embodiment, the steps until the Al wiring 13 is formed and the p-TEOS NSG film 14 is deposited as shown in FIG.

Next, p-TESO was applied by NH ₃ plasma.
The surface treatment of the surface of the NSG film 14 is performed.

The conditions of this plasma treatment are as follows. NH ₃ gas flow rate 30 sccm N ₂ gas flow rate 1000 sccm Pressure 0.35 torr High frequency power 1000 W Temperature 350 ° C Time 60 sec

After such surface treatment, the film thickness when directly deposited on the Si substrate is 500 as shown in FIG. 6b.
the O ₃ -TEOS NSG film 25 under p-
Deposit on the TESO NSG film 14. At this time, the film thickness on the Al wiring and on the flat portion where the Al wiring is not formed is about 500 nm. According to this example, the O ₃ -TEOS NSG film 25 can be completely filled up to the wiring interval of 0.5 μm.

Then, as shown in FIG. 6c, O ₃ -TEO
On the S NSG film 25, a p-T film having a flat film thickness of 1 μm
An EOS NSG film 34 is deposited, and a p-SiH ₄ SiO ₂ film 44 having a flat portion having a film thickness of 0.2 μm is further deposited thereon.

Next, the p-SiH ₄ SiO ₂ film 44 and p-TEO formed on the convex portion of the substrate by CMP treatment.
The S NSG film 34 is etched back. At this time, the p-SiH ₄ SiO ₂ film 44 having a slow etching rate serves as an etching stop, and an interlayer insulating film having a flat surface can be obtained as shown in FIG. 9D.

[Embodiment 7] Also in this embodiment, the Al wiring 13 is formed, the p-TEOS NSG film 14 is deposited thereon (FIG. 7a), and the p-TEOS NS is formed by NH ₃ plasma.
After the surface of the G film 14 is processed, O ₃ -TEOS N
The steps up to the step of depositing the SG film 25 (FIG. 7b) are performed in the same manner as described in the ninth embodiment.

Then, as shown in FIG. 7c, O ₃ -TEOS
On the NSG film 25, a p-type film having a flat thickness of 0.2 μm
A SiH ₄ SiO ₂ film 44 is deposited, and a p-TEOS NSG film 34 having a flat portion having a thickness of 1 μm is further deposited thereon.

Next, the p-TEOS NSG film 34 and p-SiH formed on the convex portion of the substrate by CMP treatment.
_{4 The} SiO ₂ film 44 is etched back. At this time, the p-SiH ₄ SiO ₂ film 44 having a slow etchback rate plays a role of an etching stop, and as shown in FIG.
Etching is stopped when the p-SiH ₄ SiO ₂ film 44 on the 1-wiring 13 is exposed, and an interlayer insulating film having a flat surface can be obtained.

[Embodiment 8] In this embodiment, as shown in FIG. 8A, an Al wiring 13 is formed as in the case of Embodiment 3, and a p-SiH ₄ SiO ₂ film 44 is formed to have a thickness of 100 nm thereon. Deposit on. Then, as shown in FIG. 8b, p-SiH ₄
The SOG film 35 is deposited on the SiO ₂ film 44 so that the film thickness in the flat portion is 0.6 μm.

Next, a convex portion, that is, Al is formed by CMP processing.
The SOG film 35 on the wiring is etched back. At this time, S
The etching rate of the OG film is close to that of the p-TEOS NSG film, and the p-TEOS NSG film is maintained while maintaining the etching rate ratio with the p-SiH ₄ SiO ₂ film.
It is possible to etch at about the same rate as the film. Therefore, as in Example 3, p-SiH ₄ SiO
_As shown in FIG. 8C, the ₂ film 44 is used as an etching stop, and the convex portion, that is, the SOG film 35 on the Al wiring 13 is etched, and the etching is stopped when the p-SiH ₄ SiO ₂ film 44 is exposed. be able to.

Finally, as shown in FIG. 8d, the SOG film 3
A p-TEOS NSG film 34 having a film thickness of 0.8 μm is deposited on the film 5, and the interlayer insulating film forming step is completed. Where p-T
P-SiH ₄ SiO ₂ instead of the EOS NSG film 34
It is also possible to deposit the films to the same thickness.

[0074]

As described above, according to the present invention, the insulating film formed by the CVD method or the SOG method using an organic silicon compound as a raw material, which is excellent in the embedding property, is etched back by the CMP process so that the embedding property is improved. Excellent in
An almost completely flat interlayer insulating film can be formed.

Further, the insulating film formed by the above method is subjected to CMP.
By using an etching stop suitable for etching back in the process, the insulating film can be planarized with high controllability.

[Brief description of drawings]

FIG. 1A is a cross-sectional view showing an Al wiring forming step and a p-TEOS NSG film depositing step of a first example of a method for planarizing an insulating film of the present invention, and FIG. 1B is a planar view of an insulating film of the present invention. Ethanol surface treatment and O ₃ -TEOS of the first example of the method
Is a sectional view showing a NSG film deposition step, (c) is a sectional view showing a p-TEOS NSG film deposited and p-SiH ₄ SiO ₂ film deposition process of the first example of the flattening process of the present invention the insulating film , (D) are cross-sectional views showing a CMP process step of the first example of the insulating film flattening method of the present invention.

2A is a sectional view showing an Al wiring forming step and an SOG film depositing step of a second example of the insulating film planarizing method of the present invention, and FIG. 2B is a sectional view of the insulating film planarizing method of the present invention. is a sectional view showing a second example ethanol surface treatment and O ₃ -TEOS NSG film deposition step, (c) the second example p-TEOS NSG film deposition and planarization process of the present invention the insulating film p-
Is a sectional view showing a SiH ₄ SiO ₂ film deposition step,
(D) is sectional drawing which shows the CMP process process of the 2nd example of the planarization method of the insulating film of this invention.

FIG. 3A shows a third example of a method for planarizing an insulating film according to the present invention.
Al wiring formation and p-SiH _FourSiO₂Film deposition process
It is sectional drawing which shows, (b) is the planarization method of the insulating film of this invention.
Of the third example of ethanol surface treatment and O₃-TEOS
It is sectional drawing which shows the NSG film deposition process, (c) is this invention.
A disconnection showing the CMP process step of the third example of the method of planarizing the insulating film
FIG. 3D is a plan view, and FIG. 3D shows a third method of planarizing an insulating film according to the present invention.
FIG. 6 is a cross-sectional view showing an example p-TEOS NSG film deposition process.
It

FIG. 4A shows a fourth example of the method for planarizing an insulating film according to the present invention.
Al wiring formation and p-SiH _FourSiO₂Film deposition process
It is sectional drawing which shows, (b) is the planarization method of the insulating film of this invention.
Surface treatment and O of the fourth example of₃-TEOS
It is sectional drawing which shows the NSG film deposition process, (c) is this invention.
The SOG film coating process of the 4th example of the planarization method of an insulating film is shown.
It is a sectional view, (d) is the first of the planarization method of the insulating film of the present invention.
It is sectional drawing which shows the CMP process process of 4 examples, (e) is this book.
Invention p-TEOS NS of Fourth Example of Insulating Film Flattening Method
It is sectional drawing which shows a G film deposition process.

5A is a sectional view showing a laminated film deposition and p-SiH ₄ SiO ₂ film deposition step of a fifth example of the insulating film flattening method of the invention, and FIG. 5B is a sectional view of the insulating film of the invention. It is sectional drawing which shows the Al wiring formation and p-TEOS NSG film deposition process of the 5th example of the planarization method, (c) is ethanol surface treatment and O ₃ of the 5th example of the planarization method of this invention. T
It is sectional drawing which shows an EOS NSG film deposition process, (d)
FIG. 6A is a cross-sectional view showing a CMP process step of a fifth example of the insulating film flattening method of the present invention, and (e) shows a p-TEOS NSG film deposition step of the fifth example of the insulating film flattening method of the present invention. FIG.

FIG. 6A is a cross-sectional view showing an Al wiring formation and p-TEOS NSG film deposition step of a sixth example of a method for planarizing an insulating film of the present invention, and FIG. NH ₃ Plasma Treatment and O ₃ -TEOS of Example 6 of Method
Is a sectional view showing a NSG film deposition step, (c) is a sectional view showing a p-TEOS NSG film deposited and p-SiH ₄ SiO ₂ film depositing step of the sixth example of the flattening process of the present invention the insulating film , (D) are cross-sectional views showing a CMP process step of a sixth example of the method for planarizing an insulating film of the present invention.

FIG. 7A is a cross-sectional view showing Al wiring formation and p-TEOS NSG film deposition steps of a seventh example of a method for planarizing an insulating film of the present invention, and FIG. NH ₃ Plasma Treatment and O ₃ -TEOS of Example 7 of Method
Is a sectional view showing a NSG film deposition step, (c) is a sectional view showing a p-SiH ₄ SiO ₂ film deposition and p-TEOS NSG film deposition process of the seventh example of the flattening process of the present invention the insulating film , (D) are cross-sectional views showing a CMP treatment step of a seventh example of the method for planarizing an insulating film of the present invention.

FIG. 8A is an eighth example of a method for planarizing an insulating film of the present invention.
Al wiring formation and p-SiH _FourSiO₂Film deposition process
It is sectional drawing which shows, (b) is the planarization method of the insulating film of this invention.
FIG. 9B is a cross-sectional view showing the SOG film coating step of the eighth example of
(C) is a CMP treatment of an eighth example of the method for planarizing an insulating film of the present invention
It is sectional drawing which shows the process of processing, (d) is the flatness of the insulating film of this invention.
The p-TEOS NSG film deposition step of the eighth example of the supporting method is performed.
It is sectional drawing shown.

[Explanation of symbols]

11 Semiconductor Wear 12 BPSG Film 13 Aluminum Wiring 13a Aluminum Alloy Film 13b p-SiH ₄ SiO ₂ Film 14 p-TEOS NSG Film 16 Dummy Pattern 17 Photoresist 25 O ₃ -TEOS NSG Film 34 p-TEOS NSG Film 35 SOG Film 44 p-SiH ₄ SiO ₂ film 45 SOG film

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Nobuyoshi Sato 1 Kawasaki-cho, Chuo-ku, Chiba-shi, Chiba Kawasaki Steel Corporation Technical Research Headquarters (72) Inventor Hiroshi Yamamoto 1 Kawasaki-cho, Chuo-ku, Chiba-shi Address: Kawasaki Steel Corporation Technical Research Division

Claims (5)

[Claims] 1. A semiconductor substrate is provided, wiring is formed on the surface of the semiconductor substrate, and the surface of the semiconductor substrate on which the wiring is formed has irregularities by a CVD method using an organic silicon compound as a raw material or an insulating material. Alternatively, a solution of the precursor is applied to form an insulating film on the substrate, and at least a part of the insulating film formed on the convex portion of the substrate is etched back by CMP treatment. A method for planarizing a characteristic insulating film. 2. A film having a slower CMP etching rate than the insulating film is formed below or above the insulating film or on a metal film for wiring, and the film having a slower CMP etching rate is etched. Used as C
The method of planarizing an insulating film according to claim 1, wherein MP processing is performed. 3. The low etching rate film is formed by depositing one of silicon oxide and silicon oxynitride by a CVD method using an inorganic silicon compound as a raw material. Method of flattening insulating film. 4. The method of planarizing an insulating film according to claim 1, wherein the insulating film is formed by CVD using tetraethyl orthosilicate as a raw material. 5. The insulation according to claim 3, further comprising a step of performing a surface treatment with an organic solvent on the uneven surface of the semiconductor substrate before the step of forming the insulating film. Method of planarizing a film.