JPH07287938A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To obtain a data transmission equipment capable of decoding easily and surely a receiving signal with a signal processing means of a simple constitution. CONSTITUTION:The data transmission is performed via a transmission line of a partial response PR(1, 1) form in which an edge recording system is adopted. A signal processing means performing a signal procession allowing the signal passed through the transmission line 20 to be a DC-free is provided in the precoder 10 on the transmission side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device employing a partial response (PR) system, and in particular PR (1,1) which is a basic correlation waveform of partial response class 1. ) Type transmission system for performing data transmission.

[0002]

2. Description of the Related Art Conventionally, the partial response method is known as a high-efficiency transmission method for performing pulse transmission using a correlation code. In particular, the PR (1,1) format, which is a basic correlation waveform of partial response class 1, is well known as a simple and highly effective method.

Further, in a transmission system for recording / reproducing data via a magnetic recording medium, an optical recording medium, etc., an edge recording system is adopted to invert from a high level to a low level or from a low level to a high level. There is a method of transmitting data, that is, recording / reproducing by giving information to the inversion. Furthermore, high density recording of data is performed by adopting the partial response method.

[0004]

By the way, in the data transmission apparatus adopting the partial response method, multi-value discrimination is performed on the receiving side and the data is decoded by the Viterbi decoding method. Since the signal received via the 1, 1) type transmission system is not DC free,
There is a problem in that DC reproduction is required on the receiving side and processing such as level clamping must be performed for this DC reproduction, which complicates the configuration of the signal processing means on the receiving side.

Therefore, an object of the present invention is to provide a data transmission device capable of easily and surely decoding a received signal by a signal processing means having a simple structure.

Another object of the present invention is to ensure that the signal processing means on the transmission side performs DC-free signal processing for a signal passing through a PR (1,1) type transmission system adopting an edge recording method. It is to provide a data transmission device capable of performing.

Another object of the present invention is to realize high-density recording / reproducing with a simple structure at low cost.

[0008]

In order to solve the above-mentioned problems, the present invention provides a data transmission device for performing data transmission via a partial response PR (1,1) type transmission system adopting an edge recording method. Therefore, a signal processing means for performing signal processing for making a signal passing through the transmission system DC-free is provided in the precoder on the transmission side.

In the data transmission device according to the present invention, the signal processing means is a digital sum variation (DSV: digtal) for each predetermined data amount of the input data of the precoder.
a first DSV detecting means for detecting the sum variation), a second DSV detecting means for detecting the sum of the DSVs of the output data of the precoder, and the respective detection outputs by the first and second DSV detecting means. It is characterized by comprising control bit generation means for generating two control bits and control means for adding the control bit generated by the control bit generation means to the input data of the precoder.

In the data transmission apparatus according to the present invention, the PR (1,1) type transmission system is an optical recording / reproducing system.

[0011]

In the data transmission apparatus according to the present invention, the signal processing means provided in the precoder on the transmission side is provided with the signal processing for making the signal passing through the PR (1,1) type transmission system adopting the edge recording system DC-free. By. It

In the data transmission device according to the present invention, the signal processing means detects the DSV for each predetermined data amount of the input data of the precoder by the first DSV detection means, and the precoder by the second DSV detection means. Of the output data of the precoder by detecting the total sum of the DSVs of the output data and adding the control bits of 2 bits generated by the control bit generating means to the input data of the precoder by the control means. Control the DSV.

In the data transmission apparatus according to the present invention, the PR (1,1) type transmission system is an optical recording / reproducing system MT.
It is realized by the F characteristic.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. A data transmission apparatus according to the present invention transmits data from a transmission side to a reception side via a transmission line 20 which is a PR (1,1) type transmission system as shown in FIG. Precoder 10 on the transmitting side
In addition, the multi-level discrimination circuit 30 and the decoder 40 are provided on the reception side.

The precoder 10 is, for example, as shown in FIG. 2, input via the memory section 11 and the first DSV (digtal sum variation) detecting section 12 to which the input data d _i is supplied, and the memory section 11. D supplied with data d _i
C control unit 13 and output data d of this DC control unit 13
Is supplied to the precoding section 14 and the precoding section 1
The second DSV detection section 1 to which the output data d 4 of 4 is supplied
5 and a control bit calculator 16 to which the detection outputs of the first and second DSV detectors 12 and 15 are supplied, and a control bit c generated by the control bit calculator 16
₁ and c ₂ are supplied to the DC control unit 13.

In the precoder 10, the memory section 11 is a FIFO (first in first out) memory in which the input data d _i are sequentially written by the data clock W _{CK and} sequentially read by the read clock R _CK .

Further, the first DSV detection section 12 clocks the first AND gate circuit 12A to which the input data d _i and the data clock W _CK are supplied, and the output of the first AND gate circuit 12A. A first D-type flip-flop 12B, a second D-type flip-flop 12C and an up / down counter 12F that use the data clock W _CK as a clock, and a negative logic output of the first D-type flip-flop 12B. It is composed of a second AND gate circuit 12D and a NOR gate circuit 12E to which the positive logic output of the second D-type flip-flop 12C is respectively supplied.

In the first DSV detecting section 12, the first D-type flip-flop 12B uses its negative logic output as data and synchronizes with the output of the first AND gate circuit 12A, that is, the data clock W _CK . The input data d _{i is} latched at a timing, and the input data d _i is input to NRZI (Non Return to Zer).
A process corresponding to conversion from (Inverse) to NRZ (Non Return to Zero) output data c _i is performed.

The second D-type flip-flop 1 is also provided.
The 2C latches the negative logic output of the first D-type flip-flop 12B as data by the data clock W _CK , and the negative logic output of the first D-type flip-flop 12B for only one clock. It is delayed and supplied to the second AND gate circuit 12D and the NOR gate circuit 12E.

Further, the second AND gate circuit 12 is provided.
D is logic "1" when the negative logic output of the first D-type flip-flop 12B is logic "1" twice in a row.
Is output. The output of the second AND gate circuit 12D is supplied to the up / down counter 12F as an addition control signal. In addition, the NOR gate circuit 12
E is a logic "1" when the negative logic output of the first D-type flip-flop 12B is a logic "0" twice in a row.
Is output. The output of the NOR gate circuit 12E is supplied to the up / down counter 12F as a subtraction control signal.

The up / down counter 12F
Is reset by a block signal BLOCK indicating one block of the input data d _i , and when the output of the second AND gate circuit 12D is logic “1”, that is, the first When the negative logic output of the D-type flip-flop 12B is logical "1" twice in a row, the addition operation is performed with DSV = 1, and the above NO
When the output of the R gate circuit 12E is logic "1",
That is, when the negative logic output of the first D-type flip-flop 12B is logic "0" twice consecutively, DSV =
By performing the subtraction operation as -1, PR (1,1)
2 in DSV = 1, 1 in DSV = 0, 0
Is set as DSV = −1, and the DSV of each block of the input data d _i is calculated.

The DC control unit 13 is composed of a switching control circuit 13A to which the block signal BLOCK is supplied and a switching circuit 13B controlled by the switching control circuit 13A, and the input data supplied from the memory unit 11 is supplied. d _i
And the control bits c ₁ and c ₂ supplied from the control bit operation unit 16 are switched by the switching circuit 13B and output, so that the input data d is input as shown in FIG.
Control bits c ₁ and c ₂ are added to each block of _i .

Further, the precoding section 14 is provided with the DC
The control unit 13 controls the control bits c ₁ and c in the input data d _i.
The AND gate circuit 14A is supplied with the data d _n added with ₂ and the read clock R _CK, and the D-type flip-flop 14B which uses the output of the AND gate circuit 14A as a clock. In this precoding section 14,
The D-type flip-flop 14B latches the negative logic output as the data with the output of the AND gate circuit 14A, that is, the data d _n synchronized with the timing of the read clock R _CK , and thereby the data d _n is N.
A process equivalent to converting RZI to NRZ output data c _n is performed. That is, in the PR (1,1) transmission system, when data is transmitted as it is, errors occur one after another. Therefore, in order to prevent this, the precoding unit 14 considers the data d _n as NRZI. N
It is performed precoding as shown in Table 1 corresponding to convert the output data c _n of RZ.

Further, the second DSV detecting section 15 is
AND that the D-type flip-flop 15A and the up-down counter 15D to clock the read clock R _CK, and a positive logic output of the output data c _n and the D-type flip-flop 15A from the pre-coding unit 14 are supplied Gate circuit 15B and NOR gate circuit 15C
Consists of.

In the second DSV detecting section 15, the D-type flip-flop 15A has the precoding section 1
4 of the output data c _n being adapted to latch with said read clock R _CK, supplied to the AND gate circuit 15B and the NOR gate circuit 15C by delaying the output data c _n by one clock.

Further, the AND gate circuit 15B is
When a logic "1" continue outputting data c _n of the pre-coding unit 14 twice, and outputs a logical "1". This A
The output of the ND gate circuit 15B is supplied to the up / down counter 15D as an addition control signal. Further, the NOR gate circuit 15C, the output data c _n of the pre-coding unit 14 is at a logic "0", and outputs a logical "1". The output of the NOR gate circuit 15C is supplied to the up / down counter 15D as a subtraction control signal.

Then, the up / down counter 15D
DS, when the output of the AND gate circuit 15B is a logic "1", i.e., when the output data c _n of the said pre-coding unit 14 is a logic "1" twice in succession
Performs addition operation as V = 1, also when the output of the NOR gate circuit 15C is a logic "1", i.e., a DSV = -1 when it is output data c _n of the said pre-coding unit 14 By performing the subtraction operation,
2 in PR (1,1) is set as DSV = 1, and 1 is set as DS
With V = 0 and 0 as DSV = -1, the sum of the DSVs of the input data d _i is calculated.

Further, the control bit operation unit 16 includes a DSV determination unit 16A which operates by using the data clock W _CK as a clock and a control bit generation unit 16B, and the input data d _i and the block signal BLOCK determine the DSV. This DSV determination unit 1 is supplied to the unit 16A.
6A determination output and the first and second DSV detection units 1
The detection outputs 2 and 15 are supplied to the control bit generation unit 16B.

Here, for example, as shown in FIG.
[0110101101100111], one block of input data d _i has two control bits [c ₁ c ₂ ].
=

The output data c _n precoded by the precoder unit 14 by adding [00] is [0011101001] when the last bit b of the previous block is [1].
101101110101], and the DSV when transmitted through the PR (1,1) transmission path 20 is +3.

Further, as shown in FIG. 5, the above [1001
110101101100111], one block of input data d _i has two control bits [c ₁ c ₂ ] =
The output data c _n precoded by the precoder unit 14 by adding [10] is [11000101100] when the last bit b of the previous block is [1].
10010001010], and the DSV when transmitted through the PR (1,1) transmission path 20 is -4.

The input data d _i is an NRZI signal which is an edge recording signal. 4 and 5, the blank portion between the blocks of the input data d _i is the portion in which the control bits [c ₁ c ₂ ] of ₂ bits are inserted. There is no continuous signal.

Thus, the two control bits [c ₁ c
₂ ] can be selected to control DSV positively and negatively,
Control bit [c ₂ ] =

In the case of [0], by inserting the control bit [c ₁ c ₂ ] between the _first bit a of a block and the last bit b of the previous block, the DSV of the connecting portion of two blocks is As shown in 6,
It can have values from 1 to -3. Further, by selecting the DSV of the joining portion, it is possible to control the DSV of the output data c _n.

Therefore, the DSV determining section 16A in the control bit calculating section 16 determines the DSV of the connecting portion of the two blocks.

Then, the control bit generator 16B is
The DSV of the input data d _i of the next block obtained by the first DSV detector 12 and the DV from the signal transmission start to the present time obtained by the second DSV detector 15
A 2-bit control bit [c ₁ c ₂ ] that minimizes the DSV of the output data c _n is generated from the sum of the SVs and the DSV determination result of the connecting portion of the two blocks by the DSV determination unit 16A.

Here, in the precoder 10, considering the recording / reproducing system adopting the edge recording method as the transmission path 20, it is sufficient to perform the polarity control with 1 bit.
Since the transmission line 20 is a PR (1,1) transmission system, the control bit generation unit 16B generates two control bits [c ₁ c ₂ ] of 2 bits so that the polarity control is performed at the same time as the next. Make a bit decision of.

The output data c _n obtained through the precoder 10 having such a configuration is the transmission line 20 or P
Since the DSV is controlled to be the smallest when transmitted via the R (1,1) transmission system, D on the receiving side
It can be handled as a C-free signal.

An optical recording / reproducing system, for example, is used as the transmission line 20 in the data transmitting apparatus of this embodiment.

Here, the partial response PR (1,
The 1) type transmission system can be realized by a transmission line having a frequency characteristic of a cosin characteristic exhibiting an impulse response characteristic as shown in FIG. Then, for example, M of an optical recording / reproducing system for recording / reproducing data via an optical disc.
The logical value of TF can be shown as in FIG. 8, and the optical recording / reproducing system having such an MTF characteristic exhibits the impulse response characteristic as shown in FIG.
It is an R (1,1) type transmission system. The impulse response characteristic shown in FIG. 9 is obtained by calculation from the logical value of MTF.

In the transmission line 20 using such an optical recording / reproducing system, the PR can be realized without the need for a special additional circuit.
A (1,1) type transmission system can be realized.

Further, in the data transmission apparatus of this embodiment, on the reception side that receives the data transmitted from the transmission side equipped with the precoder 10 via the transmission line 20, the received signal is DC free, that is, 2] and

Since the numbers of [0] are the same, for example, the received signal can be easily decoded by the multi-level discrimination circuit 30 and the decoder 40 having a simple configuration shown in FIG. Note that FIG. 11 shows the signal waveform of each part in the multilevel discrimination circuit 30 and the decoder 40 shown in FIG.

That is, in FIG. 10, the multilevel discriminating circuit 30 is supplied with an absolute value amplifier 31 to which the signal received via the transmission line 20 is supplied, and a reception signal amplified by the absolute value amplifier 31. Peak hold circuit 3
2 and the level comparator 33, and the 1/2 attenuator 34 to which the hold output of the peak hold circuit 32 is supplied.
And the output of the 1/2 attenuator 34 is supplied to the level comparator 33.

In the multi-level discrimination circuit 30 having such a configuration, the level comparator 33 changes the hold output level of the peak hold circuit 32 into the 1/2 attenuator 3.
The signal level attenuated to 1/2 by 0D is used as a threshold level to perform level discrimination, thereby performing multi-level discrimination of the received signal.

The decoder 40 is connected to the transmission line 2
Clock recovery unit 4 to which the signal received via 0 is supplied
1 and a D-type flip-flop 45 to which the reproduced clock from the clock reproducing unit 41 and the output of the multi-level discriminating circuit 30 are supplied.

The clock reproducing section 41 is connected to the transmission line 2
A hysteresis comparator 42 to which a signal received via 0 is supplied, a low-pass filter 43 to which the output of the hysteresis comparator 42 is supplied, and a PLL circuit 44 are provided. By performing level discrimination, a clock is extracted from the received signal and the PLL circuit 44 reproduces the clock.

Then, the D-type flip-flop 45
Outputs the reproduction data by latching the output of the multi-level discrimination circuit 30 with the reproduction clock supplied from the clock reproduction unit 41.

[0046]

As described above, in the data transmission device according to the present invention, the signal processing for making the signal DC free through the PR (1,1) type transmission system adopting the edge recording method is performed on the transmission side. Since it is performed by the signal processing means provided in the precoder, the received signal is DC at the receiving side which receives the signal processed by the signal processing means via the PR (1,1) type transmission system. Since it is free, the received signal can be easily and surely decoded by the signal processing means having a simple structure.

The signal processing means on the transmitting side is the first
The DSV detecting means detects the DSV for each predetermined data amount of the input data of the precoder, and the second DSV
By detecting the total sum of the DSVs of the output data of the precoder by the detecting means, and adding the two control bits generated by the control bit generating means based on each detected output to the input data of the precoder by the controlling means, The DSV of the output data of the precoder can be controlled so that the signal that has passed through the PR (1, 1) type transmission system adopting the edge recording method is DC-free.

Further, in the data transmission apparatus according to the present invention, by using the optical recording / reproducing system as a transmission system, a PR (1,1) type transmission system can be realized without requiring a special additional circuit. You can Therefore, it is possible to realize a high-density recording / reproducing apparatus having a simple structure and low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a precoder that is a signal processing means on the transmission side in the data transmission device.

FIG. 3 is a diagram showing data in which a control bit is added to each block of input data in the precoder.

FIG. 4 is a diagram schematically showing an example of output data of the precoder.

FIG. 5 is a diagram schematically showing another example of output data of the precoder.

FIG. 6 is a diagram schematically showing a DSV state in a joint portion of two blocks in which control bits are inserted.

FIG. 7 is a characteristic diagram showing impulse response characteristics of a partial response PR (1,1) type transmission system.

FIG. 8 is a characteristic diagram showing MTF characteristics of an optical recording / reproducing system.

FIG. 9 is a characteristic diagram showing an impulse response characteristic according to the MTF characteristic of the optical recording / reproducing system.

FIG. 10 is a block diagram showing a specific configuration of a multilevel identification circuit and a decoder, which are signal processing means on the transmission side in the data transmission device.

FIG. 11 is a waveform diagram showing the signal waveform of each part in the multi-level discrimination circuit and decoder 40.

[Description of Reference Signs] 10 precoder 11 memory unit 12 first DSV detection unit 13 DC control unit 14 precode unit 15 second DSV detection unit 16 control bid arithmetic unit 20 transmission circuit 30 multi-level discrimination circuit 40 decoder

Claims (3)

[Claims] 1. A data transmission device for performing data transmission via a partial response PR (1,1) type transmission system adopting an edge recording method, wherein a signal passing through the transmission system is made DC free. A data transmission device characterized in that a signal processing means for performing processing is provided in a precoder on the transmission side. 2. The signal processing means calculates a sum of the digital sum variation of the first digital sum variation detecting means for detecting the digital sum variation of the predetermined data amount of the input data of the precoder and the digital sum variation of the output data of the precoder. Second digital sum variation detecting means for detecting, control bit generating means for generating two control bits based on each detection output by the first and second digital sum variation detecting means, and the control bit generating means 2. The data transmission device according to claim 1, further comprising control means for adding the control bit generated by the above to the input data of the precoder. 3. The partial response PR (1,
2. The data transmission device according to claim 1, wherein the 1) type transmission system is an optical recording / reproducing system.