JPH07284278A - Biased magnetization suppression control circuit - Google Patents
Biased magnetization suppression control circuitInfo
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- JPH07284278A JPH07284278A JP6068838A JP6883894A JPH07284278A JP H07284278 A JPH07284278 A JP H07284278A JP 6068838 A JP6068838 A JP 6068838A JP 6883894 A JP6883894 A JP 6883894A JP H07284278 A JPH07284278 A JP H07284278A
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- magnetic flux
- voltage
- voltage source
- transformer
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電圧形インバータの多重
変圧器の偏磁を抑制する偏磁抑制制御回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an eccentricity suppression control circuit for suppressing eccentricity of a voltage transformer multi-transformer.
【０００２】[0002]
【従来の技術】多重変圧器で構成されるインバータ装置
を図７に示す。図７において、１ａ，１ｂは多重変圧
器、２ａ，２ｂは電圧検出用変圧器、３は直流電圧検出
回路、４ａ，４ｂは変流器、２０ａ，２０ｂは電圧形イ
ンバータを示し、その詳細を図８に示す。2. Description of the Related Art FIG. 7 shows an inverter device composed of multiple transformers. In FIG. 7, 1a and 1b are multiple transformers, 2a and 2b are voltage detection transformers, 3 is a DC voltage detection circuit, 4a and 4b are current transformers, and 20a and 20b are voltage source inverters. It shows in FIG.
【０００３】図８において、２２Ｕ，２２Ｘ，２２Ｖ，
２２ＹはＧＴＯ等の自己消弧形素子、２３Ｕ，２３Ｘ，
２３Ｖ，２３Ｙは、前記自己消弧形半導体素子にそれぞ
れ逆並列接続される帰還ダイオード、２４ａ，２４ｂは
直流コンデンサである。In FIG. 8, 22U, 22X, 22V,
22Y is a self-extinguishing element such as GTO, 23U, 23X,
23V and 23Y are feedback diodes respectively connected in anti-parallel to the self-arc-extinguishing type semiconductor element, and 24a and 24b are DC capacitors.
【０００４】Ｎo.2 電圧形インバータ２０ｂも同様にし
て構成される。電圧形インバータは多重接続することに
よって、高調波の低減と大容量化が図れることは一般に
知られている。The No. 2 voltage source inverter 20b is similarly constructed. It is generally known that by connecting multiple voltage source inverters, harmonics can be reduced and the capacity can be increased.
【０００５】図７の単相２直列多重インバータの場合、
Ｎo1. 電圧形インバータ２０ａとＮo.2 電圧形インバー
タ２０ｂの搬送波に９０°の位相差を設け各段の出力電
圧に位相差をもたせることで上記目的を満す。In the case of the single-phase two-series multiple inverter shown in FIG.
The above object is satisfied by providing a 90 ° phase difference between the carrier waves of the No. 1 voltage source inverter 20a and the No. 2 voltage source inverter 20b so that the output voltage of each stage has a phase difference.
【０００６】インバータ出力電圧の波形例を図１０
（ａ）に示す、しかしながら、インバータ出力電流を急
変させた場合における各段の出力電圧のバラツキが変圧
器の偏磁の原因となる。FIG. 10 shows a waveform example of the inverter output voltage.
However, the variation in the output voltage of each stage when the inverter output current is suddenly changed causes the transformer to be biased, as shown in (a).
【０００７】この現象について以下説明する。図９のよ
うに電圧形インバータを交流系統に接続した場合、イン
バータの出力電流は次のように示すことができる。This phenomenon will be described below. When the voltage type inverter is connected to the AC system as shown in FIG. 9, the output current of the inverter can be expressed as follows.
【０００８】[0008]
【数１】Ｉc ＝（Ｖs −Ｖc)／ｊωＬ ここで、Ｖs は交流系統の電圧、Ｖc は電圧形インバー
タの出力電圧、Ｌは連系リアクトル（変圧器）のリアク
タンスである。## EQU1 ## Ic = (Vs-Vc) / jωL where Vs is the voltage of the AC system, Vc is the output voltage of the voltage source inverter, and L is the reactance of the interconnection reactor (transformer).
【０００９】前式から、電圧形インバータの出力電圧は
交流系統の電圧Ｖs と電圧形インバータの出力電流Ｉc
、換言すれば電流指令値により決定されることがわか
る。多重変圧器１ａ，１ｂによって接続されたインバー
タ装置のインバータ出力電圧は図１０（ａ）に示すよう
に定常的には直流分を発生しない。ところが、電流指令
値が急変した場合には同図（ｂ）に示すように、電流変
化に必要な電圧として、例えば上段インバータの出力電
圧の矩形波の斜線部分が増加し、下段のインバータの矩
形波の点線部分が減少したとすれば、瞬時的にはかなり
の電圧時間積の直流分がインバータ出力電圧に現われて
おり、電圧の積分値である磁束について考えればある巻
線の磁束は正方向に、他の巻線は負方向に偏磁すること
になる。このような現象が繰り返されれば、変圧器の偏
磁が急速に進行し偏磁過電流に至る。From the above equation, the output voltage of the voltage source inverter is the voltage Vs of the AC system and the output current Ic of the voltage source inverter.
In other words, it can be seen that it is determined by the current command value. The inverter output voltage of the inverter device connected by the multiple transformers 1a and 1b does not steadily generate a DC component as shown in FIG. 10 (a). However, when the current command value suddenly changes, as shown in (b) of the same figure, as the voltage required for the current change, for example, the hatched portion of the rectangular wave of the output voltage of the upper inverter increases and the rectangular shape of the lower inverter increases. If the dotted line part of the wave is reduced, the DC component of a considerable voltage-time product instantaneously appears in the inverter output voltage, and considering the magnetic flux that is the integral value of the voltage, the magnetic flux of a certain winding is positive. Moreover, the other windings are demagnetized in the negative direction. If such a phenomenon is repeated, the demagnetization of the transformer rapidly progresses, leading to a demagnetization overcurrent.
【００１０】この多重変圧器の偏磁抑制を目的とした従
来の制御回路を図６に示す。各電圧形インバータ２０
ａ，２０ｂに流れる電流は各インバータ毎に取付けられ
た変流器４ａ，４ｂにより制御回路４０に取込まれる。
この各電圧インバータ２０ａ，２０ｂの個別電流ｉ1 及
びｉ2 は制御回路４０内のローパスフィルタ１４ａ，１
４ｂに入力されその直流分が抽出され、各段の減算器４
１ａ，４１ｂにより各段の信号波eo1 及びeo2 にそれぞ
れ減算される。各段のゲート回路３０内で各信号波と搬
送波が比較され図８の各相のスイッチング素子２２Ｕ〜
２２Ｙをオンオフすることによって出力電圧を制御す
る。これにより、多重変圧器の各段の出力電流の直流分
を相殺することによって変圧器の偏磁を抑制する。FIG. 6 shows a conventional control circuit for the purpose of suppressing magnetic bias in this multiple transformer. Each voltage source inverter 20
The currents flowing through a and 20b are taken into the control circuit 40 by the current transformers 4a and 4b attached to each inverter.
The individual currents i1 and i2 of the voltage inverters 20a and 20b are supplied to the low-pass filters 14a and 1a in the control circuit 40.
4b, the direct current component is extracted, and the subtractor 4 of each stage
The signal waves eo1 and eo2 of each stage are subtracted by 1a and 41b. The signal waves and the carrier waves are compared in the gate circuit 30 of each stage, and the switching elements 22U of the respective phases of FIG.
The output voltage is controlled by turning on and off 22Y. This cancels the DC component of the output current of each stage of the multiplex transformer to suppress the magnetic bias of the transformer.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら、従来の
偏磁抑制制御回路には以下のような問題がある。 (1) 多重変圧器のインバータ出力電流を検出しローパス
フィルタによりその直流分を抽出するが、本方式では変
圧器の励磁電流の直流分のみを抽出することができな
い。このため変圧器の偏磁を抑制する効果が低下する。 (2) 直流分検出のためのフィルタがあるため応答が遅
い。However, the conventional magnetic bias suppression control circuit has the following problems. (1) Although the inverter output current of the multiple transformer is detected and its direct current component is extracted by the low-pass filter, this method cannot extract only the direct current component of the exciting current of the transformer. Therefore, the effect of suppressing the magnetic bias of the transformer is reduced. (2) The response is slow because of the filter for detecting the DC component.
【００１２】従って、本発明の目的は、前記問題点を解
決するために、各段の単位変圧器１ａ，１ｂに誘起され
る磁束を模擬或は検出し、それらの平均値を基準値とし
て各段の模擬或は検出磁束との差分で信号波ｅo1，ｅo2
を補正することにより応答の速い偏磁抑制を可能とした
偏磁抑制制御回路を提供することにある。Therefore, in order to solve the above-mentioned problems, the object of the present invention is to simulate or detect the magnetic flux induced in the unit transformers 1a and 1b of each stage, and use the average value of them as a reference value. Signal wave eo1, eo2 by the difference between the simulated stage or the detected magnetic flux
An object of the present invention is to provide a magnetic bias suppression control circuit that can suppress magnetic bias with a fast response by correcting
【００１３】[0013]
【課題を解決するための手段】前記目的を達成するため
に、請求項１の発明は、少くとも２台の電圧形インバー
タの出力を多重変圧器を介して直列接続されて成るイン
バータ装置の多重変圧器の偏磁を抑制するため、電圧形
インバータのゲート信号から各々の電圧形インバータの
出力電圧に相当する信号を発生する出力電圧模擬手段
と、該出力電圧模擬手段の出力信号を積分し多重変圧器
の各巻線に誘起される磁束を模擬するそれぞれの磁束模
擬手段と、該磁束模擬手段から各巻線に誘起される磁束
の平均値を得る手段と、該平均値と各巻線の模擬磁束と
の差分を得る手段を設け、それぞれの差分で、各電圧形
インバータの信号波を補正することにより多重変圧器の
偏磁を抑制するようにしたものである。In order to achieve the above-mentioned object, the invention of claim 1 is a multiplex inverter device comprising outputs of at least two voltage source inverters connected in series via a multiplex transformer. Output voltage simulation means for generating a signal corresponding to the output voltage of each voltage-source inverter from the gate signal of the voltage-source inverter and an output signal of the output voltage simulation means are integrated and multiplexed in order to suppress the magnetic bias of the transformer. Magnetic flux simulating means for simulating magnetic flux induced in each winding of the transformer, means for obtaining an average value of magnetic flux induced in each winding from the magnetic flux simulating means, and the average value and simulated magnetic flux of each winding. Is provided, and the signal wave of each voltage source inverter is corrected by each difference, thereby suppressing the bias magnetization of the multiple transformer.
【００１４】又、請求項２の発明は、前記多重変圧器の
偏磁を抑制するため、前記電圧形インバータの出力電圧
を積分し多重変圧器の各巻線に誘起される磁束を模擬す
るそれぞれの磁束模擬手段と、該磁束模擬手段から各巻
線に誘起される磁束の平均値を得る手段と、該平均値と
各巻線の模擬磁束との差分を得る手段を設け、それぞれ
の差分で各電圧形インバータの信号波を補正することに
より前記多重変圧器の偏磁を抑制するようにしたもので
ある。Further, in order to suppress the magnetic bias of the multiple transformer, the invention of claim 2 integrates the output voltage of the voltage source inverter to simulate the magnetic flux induced in each winding of the multiple transformer. The magnetic flux simulating means, the means for obtaining the average value of the magnetic flux induced in each winding from the magnetic flux simulating means, and the means for obtaining the difference between the average value and the simulated magnetic flux of each winding are provided, and each voltage form By correcting the signal wave of the inverter, the magnetic bias of the multiple transformer is suppressed.
【００１５】更に、請求項３の発明は、前記多重変圧器
の偏磁を抑制するため、前記電圧形インバータのゲート
信号から各々の電圧形インバータの出力電圧に対応する
信号を得、該信号にそれぞれの電圧形インバータの直流
電圧を乗じて各々の電圧形インバータの出力電圧に相当
する信号を得る出力電圧模擬手段と、該出力電圧模擬手
段の出力信号を積分し多重変圧器の各巻線に誘起される
磁束を模擬するそれぞれの磁束模擬手段と、該磁束模擬
手段から各巻線に誘起される磁束の平均値を得る手段
と、該平均値と各巻線の模擬磁束との差分を得る手段を
設け、該それぞれの差分で前記それぞれの電圧形インバ
ータの信号波を補正することにより前記多重変圧器の偏
磁を抑制するようにしたものである。Further, according to the invention of claim 3, in order to suppress the magnetic bias of the multiplex transformer, a signal corresponding to the output voltage of each voltage type inverter is obtained from the gate signal of the voltage type inverter, and the signal is obtained. Output voltage simulation means for multiplying the DC voltage of each voltage source inverter to obtain a signal corresponding to the output voltage of each voltage source inverter, and integrating the output signal of the output voltage simulation means to induce in each winding of the multiple transformer A magnetic flux simulating means for simulating the magnetic flux to be generated, a means for obtaining an average value of the magnetic flux induced in each winding from the magnetic flux simulating means, and a means for obtaining a difference between the average value and the simulated magnetic flux of each winding. By correcting the signal waves of the respective voltage source inverters with the respective differences, the magnetic bias of the multiple transformers is suppressed.
【００１６】更に又、請求項４の発明は、前記多重変圧
器の偏磁を抑制するため、前記多重変圧器の各巻線に誘
起される磁束を検出するそれぞれの磁束検出手段と、該
磁束検出手段から各巻線に誘起される磁束の平均値を得
る手段と、該平均値と各巻線の磁束との差分を得る手段
を設け、該それぞれの差分で、それぞれの電圧形インバ
ータの信号波を補正することにより前記多重変圧器の偏
磁を抑制するようにしたものである。Further, in the invention of claim 4, in order to suppress the magnetic bias of the multiple transformer, each magnetic flux detecting means for detecting the magnetic flux induced in each winding of the multiple transformer, and the magnetic flux detecting means. Means for obtaining the average value of the magnetic flux induced in each winding from the means, and means for obtaining the difference between the average value and the magnetic flux of each winding, and correcting the signal wave of each voltage source inverter by the respective difference By doing so, the magnetic bias of the multiple transformer is suppressed.
【００１７】[0017]
【作用】前述のように構成された請求項１の発明によれ
ば、出力電圧模擬手段の各出力電圧をｖとし、この電圧
ｖを積分することによって各巻線の磁束φを模擬するこ
とができる。According to the invention of claim 1 configured as described above, each output voltage of the output voltage simulating means is v, and the magnetic flux φ of each winding can be simulated by integrating this voltage v. .
【００１８】[0018]
【数２】 次式に示すように、この模擬磁束φと各巻線の模擬磁束
を平均したものを基準値φ* としてそれらの差分をとり
その値Δφで各電圧形インバータの信号波を補正するこ
とにより各巻線の磁束を等しくできるので多重変圧器の
偏磁を抑制出来る。[Equation 2] As shown in the following equation, the average value of this simulated magnetic flux φ and the simulated magnetic flux of each winding is used as a reference value φ * , and the difference between them is taken to correct the signal wave of each voltage source inverter by the value Δφ. Since the magnetic fluxes of can be made equal, it is possible to suppress the magnetic bias of the multiple transformer.
【００１９】[0019]
【数３】 φ* ＝（１／２）（φ1 ＋φ2 ） ……（２） Δφ1 ＝φ1 −φ* ……（３） Δφ2 ＝φ2 −φ* ……（４） 又、請求項２の発明によれば、各電圧形インバ―タの出
力電圧そのものを積分することによって各巻線の磁束φ
を模擬することができる。従って、前述同様、この模擬
磁束φと各巻線の模擬磁束を平均したものを基準値φ*
としてそれらの差分をとりその値Δφで各電圧形インバ
ータの信号波を補正することにより各巻線の磁束を等し
くできるので多重変圧器の偏磁を抑制出来る。(3) φ * = (1/2) (φ1 + φ2) (2) Δφ1 = φ1−φ * (3) Δφ2 = φ2−φ * (4) Also, the invention of claim 2 According to the method, the magnetic flux φ of each winding is calculated by integrating the output voltage itself of each voltage source inverter.
Can be simulated. Therefore, similar to the above, the reference value φ * is the average of this simulated magnetic flux φ and the simulated magnetic flux of each winding .
As the magnetic flux of each winding can be made equal by taking the difference between them and correcting the signal wave of each voltage source inverter by the value Δφ, it is possible to suppress the bias magnetization of the multiple transformer.
【００２０】更に、請求項３の発明によれば、電圧形イ
ンバータのゲート信号から各々の電圧形インバータの出
力電圧に対応する信号を得、該信号にそれぞれの電圧形
インバータの直流電圧を乗ずることにより、電圧形イン
バータの直流電圧に含まれるリプル電圧が加味された各
々の電圧形インバータの出力電圧に相当する信号を得る
ことができ、この信号を積分することによって各巻線の
磁束φを模擬することができる。従って、前述同様、こ
の模擬磁束φと各巻線の模擬磁束を平均したものを基準
値φ* としてそれらの差分をとりその値Δφで各電圧形
インバータの信号波を補正することにより各巻線の磁束
を等しくできるので多重変圧器の偏磁を抑制出来る。更
に又、請求項４の発明によれば、多重変圧器の各巻線に
誘起される磁束φを直接磁束検出手段で検出することに
より、前述同様、この磁束φと各巻線の磁束を平均した
ものを基準値φ* としてそれらの差分をとりその値Δφ
で各電圧形インバータの信号波を補正することにより各
巻線の磁束を等しくできるので多重変圧器の偏磁を抑制
出来る。Further, according to the invention of claim 3, a signal corresponding to the output voltage of each voltage source inverter is obtained from the gate signal of the voltage source inverter, and the signal is multiplied by the DC voltage of each voltage source inverter. Can obtain a signal corresponding to the output voltage of each voltage source inverter to which the ripple voltage included in the DC voltage of the voltage source inverter is added, and the magnetic flux φ of each winding is simulated by integrating this signal. be able to. Therefore, similarly to the above, the average value of this simulated magnetic flux φ and the simulated magnetic flux of each winding is taken as the reference value φ * , and the difference between them is taken and the signal wave of each voltage source inverter is corrected by that value Δφ to correct the magnetic flux of each winding. Since it can be made equal, it is possible to suppress the magnetic bias of the multiple transformer. Further, according to the invention of claim 4, the magnetic flux φ induced in each winding of the multiplex transformer is directly detected by the magnetic flux detecting means, and the magnetic flux φ and the magnetic flux of each winding are averaged as described above. Is the reference value φ * and the difference between them is taken and the value Δφ
By correcting the signal wave of each voltage source inverter, the magnetic flux of each winding can be made equal, so that the magnetic bias of the multiple transformer can be suppressed.
【００２１】[0021]
【実施例】以下、請求項１の発明を図６と同一部に同一
符号を付して示す図１の構成図を参照して説明する。図
１において、Ｕ，Ｘ相変調回路４６ａは信号波ｅo1と搬
送波ｓs1からＮo1.電圧形インバータのＵ相ＧＴＯ（図
８の２２Ｕ）へのゲート信号を出力し、又、Ｕ相ＧＴＯ
（図８の２２Ｕ）へのゲート信号を反転してＸ相ＧＴＯ
（図８の２２Ｘ）へのゲート信号を作る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention of claim 1 will be described below with reference to the configuration diagram of FIG. 1 in which the same parts as those in FIG. In FIG. 1, a U / X phase modulation circuit 46a outputs a signal wave eo1 and a gate signal from a carrier wave ss1 to a U1 phase GTO (22U in FIG. 8) of a voltage source inverter, and also a U phase GTO.
X-phase GTO by inverting the gate signal to (22U in FIG. 8)
Create a gate signal to (22X in FIG. 8).
【００２２】Ｙ，Ｖ相変調回路４６ｂは信号波ｅo1と、
搬送波ｓs1を反転器４５で反転した信号からＮo1. 電圧
形インバータのＹ相ＧＴＯ（図８の２２Ｙ）へのゲート
信号を出力し、また、Ｙ相ＧＴＯ（図８の２２Ｙ）への
ゲート信号を反転してＶ相ＧＴＯ（図８の２２Ｖ）への
ゲート信号を作る。The Y and V phase modulation circuit 46b receives the signal wave eo1 and
The gate signal to the Y-phase GTO (22Y in FIG. 8) of the No. 1 voltage source inverter is output from the signal obtained by inverting the carrier wave ss1 by the inverter 45, and the gate signal to the Y-phase GTO (22Y in FIG. 8) is also output. It is inverted to create a gate signal to the V-phase GTO (22V in FIG. 8).
【００２３】同様にして、信号波ｅo2と搬送波ｓs2から
Ｎo2. 電圧形インバータのＵ相ＧＴＯ，Ｘ相ＧＴＯ，Ｖ
相ＧＴＯ，Ｙ相ＧＴＯへのゲート信号を作る。Ｎo1. 電
圧形インバータのＵ相ＧＴＯへのゲート信号ｕｇ1 と、
Ｙ相ＧＴＯへのゲート信号ｙｇ1 と、−１を加算器４１
ｃに印加し、加算器４１ｃから得られる合成信号ｅuy1
を積分器４２ａに印加する。又、Ｎo2. 電圧形インバー
タのＵ相ＧＴＯへのゲート信号ｕｇ2 と、Ｙ相ＧＴＯへ
のゲート信号ｙｇ2 と、−１を加算器４１ｄに印加し、
加算器４１ｄから得られる合成信号ｅuy2 を積分器４２
ｂに印加する。Similarly, from the signal wave eo2 and the carrier wave ss2 to No2. U-phase GTO, X-phase GTO, V of the voltage source inverter
Create a gate signal to the phase GTO and Y phase GTO. No1. Gate signal ug1 to U-phase GTO of voltage source inverter,
The gate signal yg1 to the Y-phase GTO and -1 are added to the adder 41.
composite signal euy1 obtained by the adder 41c by applying
Is applied to the integrator 42a. Further, the gate signal ug2 to the U-phase GTO of the No. 2 voltage source inverter, the gate signal yg2 to the Y-phase GTO, and -1 are applied to the adder 41d,
The combined signal euy2 obtained from the adder 41d is added to the integrator 42.
Apply to b.
【００２４】積分器４２ａの出力φ1 と積分器４２ｂの
出力φ2 を加算器４１ｅを介して平均値演算回路４３に
印加し、平均値演算回路４３の出力に、φ1 とφ2 の平
均値を磁束基準値φ* として得る。The output φ1 of the integrator 42a and the output φ2 of the integrator 42b are applied to the average value calculating circuit 43 via the adder 41e, and the average value of φ1 and φ2 is applied to the average value calculating circuit 43 as a magnetic flux reference. Obtained as the value φ * .
【００２５】加算器４７ａによってφ* とφ1 の偏差Δ
φ1 を、加算器４７ｂによってφ*とφ2 の偏差Δφ2
を導出し、偏差Δφ1 で信号波ｅo1を補正し、偏差Δφ
2 で信号波ｅo2を補正する。The deviation Δ between φ * and φ1 is added by the adder 47a.
φ1 is added to the deviation Δφ2 between φ * and φ2 by the adder 47b.
Is derived and the signal wave eo1 is corrected with the deviation Δφ1 to obtain the deviation Δφ
Correct the signal wave eo2 with 2.
【００２６】次に、前述構成から成る請求項１の発明の
作用を図１及び図２を参照して説明する。図２（ａ）
は、図１の信号波ｅo1と、搬送波ｅs1（ｅs1u ）と、搬
送波ｅs1を反転した信号ｅs1y を示したものである。図
２（ｂ）は、信号波ｅo1と搬送波ｅs1u から得られるＵ
相ＧＴＯへのゲート信号ｕｇ１、図２（ｃ）は、信号波
ｅo1と搬送波ｅs1y から得られるＹ相ＧＴＯへのゲート
信号ｙｇ１、図２（ｄ）は加算器４１ｃへ印加される
「−１」信号、図２（ｅ）は前記信号を合成した信号で
図１のｅuy1 となる。Next, the operation of the invention of claim 1 having the above-mentioned structure will be described with reference to FIGS. Figure 2 (a)
Shows the signal wave eo1 of FIG. 1, the carrier wave es1 (es1u), and the signal es1y obtained by inverting the carrier wave es1. FIG. 2B shows U obtained from the signal wave eo1 and the carrier wave es1u.
The gate signal ug1 to the phase GTO, FIG. 2 (c) is the gate signal yg1 to the Y phase GTO obtained from the signal wave eo1 and the carrier wave es1y, and FIG. 2 (d) is applied to the adder 41c "-1". The signal, FIG. 2 (e), is a signal obtained by synthesizing the above signals, and is euy1 in FIG.
【００２７】図１のｅuy2 はＮo2. 電圧形インバータ側
の合成信号である。前記合成信号ｅuy1 は図８に示すＮ
o1. 電圧形インバータの出力電圧を模擬した信号とな
り、この信号を積分器４２ａで積分すれば、前述したよ
うにＮo1. 電圧形インバータに接続される多重変圧器１
ａの磁束を模擬した信号φ1 となる。Euy2 in FIG. 1 is a composite signal on the side of No2. Voltage source inverter. The composite signal euy1 is N shown in FIG.
o1. It becomes a signal simulating the output voltage of the voltage source inverter, and if this signal is integrated by the integrator 42a, the multiple transformer 1 connected to the No. 1 voltage source inverter as described above.
The signal φ1 simulates the magnetic flux of a.
【００２８】一方、信号φ2 は、Ｎo2. 電圧形インバー
タに接続される多重変圧器１ｂの磁束を模擬した信号と
なる。ここで、多重変圧器に偏磁がなく、Ｎo1. 電圧形
インバータ及びＮo2. 電圧形インバータが正常に動作し
ていると、ｅuy1 ＝ｅuy2 となるため、φ1 ＝φ2 とな
る。従って、Δφ1 ＝Δφ2 ＝０となって、信号波ｅo
1，ｅo2は補正されることなく現状を維持するように制
御される。On the other hand, the signal φ2 becomes a signal simulating the magnetic flux of the multiple transformer 1b connected to the No2. Voltage source inverter. Here, when the multiple transformer has no magnetic bias and the No1. Voltage source inverter and the No2. Voltage source inverter are operating normally, euy1 = euy2 and φ1 = φ2. Therefore, Δφ1 = Δφ2 = 0 and the signal wave eo
1, eo2 is controlled so as to maintain the current state without being corrected.
【００２９】しかるに、多重変圧器に偏磁が生じるよう
になれば、Δφ1 及びΔφ2 の信号が発生し、この信号
Δφ1 によって信号波ｅuy1 が補正され、信号Δφ2 に
よって信号波ｅuy2 が補正され、この補正は偏磁が抑制
されるようになされるため、多重変圧器の偏磁を防止で
きる。However, if the multiple transformer becomes demagnetized, the signals Δφ1 and Δφ2 are generated, the signal Δeu1 corrects the signal wave euy1, and the signal Δφ2 corrects the signal wave euy2. Since the magnetic bias is suppressed, the magnetic bias of the multiple transformer can be prevented.
【００３０】又、図３は、請求項２の発明の一実施例を
示す構成図で、図１のように、ゲート信号から電圧形イ
ンバータの出力電圧を模擬する出力電圧模擬手段を設け
ることなく、Ｎo1. 電圧形インバータの出力電圧ｖ1 を
積分器４２ａに、Ｎo2. 電圧形インバータの出力電圧ｖ
2 を積分器４２ｂにそれぞれ印加し模擬磁束φ1 及びφ
2 を算出し、この模擬磁束φ1 及びφ2 から前述と同様
にΔφ1 及びΔφ2 を算出し、信号波ｅo1，ｅo2を補正
することによって多重変圧器の偏磁を抑制するようにし
たものである。Further, FIG. 3 is a block diagram showing an embodiment of the invention of claim 2, without providing an output voltage simulating means for simulating the output voltage of the voltage source inverter from the gate signal as in FIG. , No1. The output voltage v1 of the voltage source inverter is output to the integrator 42a, and the output voltage v2 of the voltage source inverter of No2.
2 are applied to the integrator 42b, and simulated magnetic fluxes φ 1 and φ
2 is calculated, Δφ1 and Δφ2 are calculated from the simulated magnetic fluxes φ1 and φ2 in the same manner as described above, and the signal waves eo1 and eo2 are corrected to suppress the demagnetization of the multiple transformer.
【００３１】更に、図４は、請求項３の発明の一実施例
を示す構成図で加算器４１ｃの出力信号にＮo1. 電圧形
インバータの直流電圧を乗算する乗算器４４ａを設け、
加算器４１ｄの出力信号にＮo2. 電圧形インバータの直
流電圧を乗算する乗算器４４ｂを設け、乗算器４４ａの
出力を積分器４２ａに、乗算器４４ｂの出力を積分器４
２ｂにそれぞれ印加するようにしたものである。Further, FIG. 4 is a block diagram showing an embodiment of the invention of claim 3, wherein a multiplier 44a for multiplying the output signal of the adder 41c by the DC voltage of the No. 1 voltage source inverter is provided.
A multiplier 44b for multiplying the output signal of the adder 41d by the DC voltage of the No. 2 voltage source inverter is provided, the output of the multiplier 44a is provided to the integrator 42a, and the output of the multiplier 44b is provided to the integrator 4
2b is applied to each.
【００３２】このように構成するたこにより、電圧形イ
ンバータの直流電圧に含まれるリプルを加味した電圧形
インバータの出力電圧を模擬することができる。積分器
４２ａ，４２ｂ以降の動作は前述と同様であるのでその
動作説明は省略するが、多重変圧器の偏磁を抑制できる
ことに変りない。With the thus constructed octopus, it is possible to simulate the output voltage of the voltage source inverter in which the ripple included in the DC voltage of the voltage source inverter is added. The operation after the integrators 42a and 42b is the same as that described above, and thus the description of the operation will be omitted, but it is still possible to suppress the demagnetization of the multiple transformer.
【００３３】更に又、図５は、請求項４の発明の一実施
例を示す構成図で、多重変圧器のそれぞれの磁束を直接
検出するために、例えば多重変圧器のそれぞれの変圧器
鉄心にホール素子等の磁束検出器を埋め込み、それらの
出力を磁束φ1 及び磁束φ２として用いるようにしたも
のである。これらの磁束φ１ 及び磁束φ2 から磁束の
偏差Δφ1 及びΔφ2 を求め、信号波ｅo1，ｅo2を補正
することは前述の実施例と同様である。以上の説明は、
電圧形インバータを単相インバータとして取扱ったが、
３相インバータでも同様に実施できるものである。Furthermore, FIG. 5 is a block diagram showing an embodiment of the invention of claim 4, in order to directly detect the magnetic flux of each of the multiple transformers, for example, in each transformer core of the multiple transformers. A magnetic flux detector such as a Hall element is embedded and the outputs thereof are used as the magnetic flux φ1 and the magnetic flux φ2. The deviations Δφ1 and Δφ2 of the magnetic flux are calculated from the magnetic flux φ1 and the magnetic flux φ2, and the signal waves eo1 and eo2 are corrected as in the above-described embodiment. The above explanation is
I handled the voltage source inverter as a single-phase inverter,
A three-phase inverter can be similarly implemented.
【００３４】[0034]
【発明の効果】以上の説明から明らかなように、請求項
１乃至請求項４の本発明によれば次のような利点が得ら
れる。 (1) 変圧器の磁束を模擬或いは直接検出して、その値を
用いて制御しているためた変圧器の偏磁の原因となる直
流磁束を簡単に検出することができる。As is apparent from the above description, according to the present invention of claims 1 to 4, the following advantages can be obtained. (1) The magnetic flux of the transformer can be simulated or directly detected, and the DC magnetic flux that causes the magnetic bias of the transformer, which is controlled by using the value, can be easily detected.
【００３５】(2) 直流分を検出するためのフィルタを省
略できるので応答が早い。 (3) 多重変圧器の各段の磁束を模擬或いは直接検出し
て、各段の磁束が等しくなるように制御しているため各
段の磁束変化にばらつきができずその結果として直流磁
束が生じないので偏磁抑制効果が向上する。(2) Since the filter for detecting the DC component can be omitted, the response is quick. (3) Since the magnetic flux of each stage of the multiple transformer is simulated or directly detected and the magnetic flux of each stage is controlled to be equal, there is no variation in the magnetic flux change of each stage, resulting in a DC magnetic flux. Since it does not exist, the effect of suppressing magnetic bias is improved.
【図１】請求項１の本発明の一実施例を示す偏磁抑制制
御回路の構成図。FIG. 1 is a configuration diagram of a magnetic bias suppression control circuit showing an embodiment of the present invention according to claim 1.
【図２】請求項１の本発明の作用を説明するための波形
図。FIG. 2 is a waveform diagram for explaining the operation of the present invention according to claim 1.
【図３】請求項２の本発明の一実施例を示す偏磁抑制制
御回路の構成図。FIG. 3 is a configuration diagram of a magnetic bias suppression control circuit showing an embodiment of the present invention according to claim 2;
【図４】請求項３の本発明の一実施例を示す偏磁抑制制
御回路の構成図。FIG. 4 is a configuration diagram of a magnetic bias suppression control circuit showing an embodiment of the present invention according to claim 3;
【図５】請求項４の本発明の一実施例を示す偏磁抑制制
御回路の構成図。FIG. 5 is a configuration diagram of a magnetic bias suppression control circuit showing an embodiment of the present invention according to claim 4;
【図６】従来の偏磁抑制制御回路の構成図。FIG. 6 is a block diagram of a conventional magnetic bias suppression control circuit.
【図７】本発明が適用出来る単相直列多重インバータの
主回路構成図。FIG. 7 is a main circuit configuration diagram of a single-phase serial multiple inverter to which the present invention can be applied.
【図８】［図７］における単位電圧形インバータの詳細
図。FIG. 8 is a detailed view of the unit voltage source inverter shown in FIG.
【図９】電圧形インバータと交流系統の等価回路を表わ
す図。FIG. 9 is a diagram showing an equivalent circuit of a voltage source inverter and an AC system.
【図１０】電圧形インバータで構成された多重変圧器の
インバータ側と交流側の電圧及びインバータ出力電流と
の関係を表わす図で、（ａ）は定常状態、（ｂ）は過渡
状態を表わす。FIG. 10 is a diagram showing a relationship between an inverter side voltage and an AC side voltage and an inverter output current of a multiple transformer composed of a voltage source inverter, where (a) shows a steady state and (b) shows a transient state.
１ａ，１ｂ …多重変圧器 ２ａ，２ｂ…
電圧検出用変圧器 ３ …直流電圧検出回路 ４ａ，４ｂ…
変流器 ２０ａ，２０ｂ…電圧形インバータ ３０…
ゲート回路 ４１ａ〜４１ｅ…加算器 ４２ａ，４２ｂ…
積分器 ４３ …平均値演算回路 ４５…
反転器 ４６ａ，４６ｂ…変調回路 ４７ａ，４７ｂ…
減算器1a, 1b ... Multiple transformers 2a, 2b ...
Voltage detection transformer 3 ... DC voltage detection circuit 4a, 4b ...
Current transformers 20a, 20b ... Voltage source inverter 30 ...
Gate circuits 41a to 41e ... Adders 42a, 42b ...
Integrator 43 ... Average value calculation circuit 45 ...
Inverters 46a, 46b ... Modulation circuits 47a, 47b ...
Subtractor
Claims (4)
出力を多重変圧器を介して直列接続されて成るインバー
タ装置の前記多重変圧器の偏磁を抑制するため、前記電
圧形インバータのゲート信号から各々の電圧形インバー
タの出力電圧に相当する信号を発生する出力電圧模擬手
段と、該出力電圧模擬手段の出力信号を積分し前記多重
変圧器の各巻線に誘起される磁束を模擬するそれぞれの
磁束模擬手段と、該磁束模擬手段から前記各巻線に誘起
される磁束の平均値を得る手段と、該平均値と前記各巻
線の模擬磁束との差分を得る手段を設け、該それぞれの
差分で前記それぞれの電圧形インバータの信号波を補正
することにより前記多重変圧器の偏磁を抑制することを
特徴とした偏磁抑制制御回路。1. A gate signal of the voltage source inverter is provided to suppress bias of the multiple transformer of an inverter device in which outputs of at least two voltage source inverters are connected in series via a multiple transformer. Output voltage simulation means for generating a signal corresponding to the output voltage of each voltage-source inverter, and respective magnetic fluxes for integrating the output signal of the output voltage simulation means and simulating the magnetic flux induced in each winding of the multiplex transformer. The simulation means, means for obtaining an average value of the magnetic flux induced in each winding from the magnetic flux simulation means, and means for obtaining a difference between the average value and the simulated magnetic flux of each winding are provided, and the difference is used to An eccentricity suppression control circuit for suppressing the eccentricity of the multiple transformer by correcting the signal wave of each voltage source inverter.
出力を多重変圧器を介して直列接続されて成るインバー
タ装置の前記多重変圧器の偏磁を抑制するため、前記電
圧形インバータの出力電圧を積分し前記多重変圧器の各
巻線に誘起される磁束を模擬するそれぞれの磁束模擬手
段と、該磁束模擬手段から前記各巻線に誘起される磁束
の平均値を得る手段と、該平均値と前記各巻線の模擬磁
束との差分を得る手段を設け、該それぞれの差分で前記
それぞれの電圧形インバータの信号波を補正することに
より前記多重変圧器の偏磁を抑制することを特徴とした
偏磁抑制制御回路。2. The output voltage of the voltage-source inverter is controlled in order to suppress biasing of the multiple-transformer of an inverter device in which the outputs of at least two voltage-source inverters are connected in series via a multiple-transformer. Magnetic flux simulation means for integrating and simulating the magnetic flux induced in each winding of the multiple transformer, means for obtaining an average value of the magnetic flux induced in each winding from the magnetic flux simulation means, the average value and the A means for obtaining a difference from the simulated magnetic flux of each winding, and correcting the signal wave of each of the voltage source inverters by the difference to suppress the bias of the multiple transformer. Suppression control circuit.
出力を多重変圧器を介して直列接続されて成るインバー
タ装置の前記多重変圧器の偏磁を抑制するため、前記電
圧形インバータのゲート信号から各々の電圧形インバー
タの出力電圧に対応する信号を得、該信号にそれぞれの
前記電圧形インバータの直流電圧を乗じて前記各々の電
圧形インバータの出力電圧に相当する信号を得る出力電
圧模擬手段と、該出力電圧模擬手段の出力信号を積分し
前記多重変圧器の各巻線に誘起される磁束を模擬するそ
れぞれの磁束模擬手段と、該磁束模擬手段から前記各巻
線に誘起される磁束の平均値を得る手段と、該平均値と
前記各巻線の模擬磁束との差分を得る手段を設け、該そ
れぞれの差分で前記それぞれの電圧形インバータの信号
波を補正することにより前記多重変圧器の偏磁を抑制す
ることを特徴とした偏磁抑制制御回路。3. A gate signal of the voltage source inverter for suppressing magnetic bias of the multiple transformer of an inverter device comprising outputs of at least two voltage source inverters connected in series via a multiple transformer. Output voltage simulating means for obtaining a signal corresponding to the output voltage of each voltage source inverter, and multiplying the signal by the DC voltage of each voltage source inverter to obtain a signal corresponding to the output voltage of each voltage source inverter; A magnetic flux simulating means for integrating the output signal of the output voltage simulating means and simulating a magnetic flux induced in each winding of the multiplex transformer, and an average value of the magnetic flux induced in each winding by the magnetic flux simulating means. And means for obtaining the difference between the average value and the simulated magnetic flux of each of the windings, and by correcting the signal wave of each of the voltage source inverters with the respective difference. An eccentricity suppression control circuit for suppressing eccentricity of the multiple transformer.
出力を多重変圧器を介して直列接続されて成るインバー
タ装置の前記多重変圧器の偏磁を抑制するため、前記多
重変圧器の各巻線に誘起される磁束を検出するそれぞれ
の磁束検出手段と、該磁束検出手段から前記各巻線に誘
起される磁束の平均値を得る手段と、該平均値と前記各
巻線の磁束との差分を得る手段を設け、該それぞれの差
分で前記それぞれの電圧形インバータの信号波を補正す
ることにより前記多重変圧器の偏磁を抑制することを特
徴とした偏磁抑制制御回路。4. In order to suppress magnetic bias of the multiple transformer of an inverter device in which the outputs of at least two voltage source inverters are connected in series via the multiple transformer, each winding of the multiple transformer is controlled. Each magnetic flux detecting means for detecting the induced magnetic flux, means for obtaining an average value of the magnetic flux induced in each winding from the magnetic flux detecting means, and means for obtaining a difference between the average value and the magnetic flux of each winding. And a bias magnetization suppression control circuit that suppresses bias magnetization of the multiple transformer by correcting the signal waves of the voltage source inverters with the respective differences.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06883894A JP3274274B2 (en) | 1994-04-07 | 1994-04-07 | Demagnetization suppression control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06883894A JP3274274B2 (en) | 1994-04-07 | 1994-04-07 | Demagnetization suppression control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07284278A true JPH07284278A (en) | 1995-10-27 |
| JP3274274B2 JP3274274B2 (en) | 2002-04-15 |
Family
ID=13385244
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|---|---|---|---|
| JP06883894A Expired - Lifetime JP3274274B2 (en) | 1994-04-07 | 1994-04-07 | Demagnetization suppression control circuit |
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| Country | Link |
|---|---|
| JP (1) | JP3274274B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010115033A (en) * | 2008-11-07 | 2010-05-20 | Toshiba Corp | Power converter |
| CN110912430A (en) * | 2019-11-23 | 2020-03-24 | 上海沪工焊接集团股份有限公司 | Method for improving magnetic bias of inverter transformer |
-
1994
- 1994-04-07 JP JP06883894A patent/JP3274274B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010115033A (en) * | 2008-11-07 | 2010-05-20 | Toshiba Corp | Power converter |
| CN110912430A (en) * | 2019-11-23 | 2020-03-24 | 上海沪工焊接集团股份有限公司 | Method for improving magnetic bias of inverter transformer |
| CN110912430B (en) * | 2019-11-23 | 2021-09-10 | 上海沪工焊接集团股份有限公司 | Method for improving magnetic bias of inverter transformer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3274274B2 (en) | 2002-04-15 |
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