JPH07283418A - Vertical junction type field-effect transistor with optimized bipolar operation mode and its rreparation - Google Patents

Abstract

PURPOSE: To form a transistor having a high switching speed by forming a hetero junction at an n-type channel between an inner layer and a channel region so as to show band discontinuity points in the valence band. CONSTITUTION: An Si/Ge alloy layer 23 is formed between overdoped p<+> semiconductor layers 4 in a intermediate region 7. The layers 4 are doped in the n-type, the same as in the region 7. This semiconductor material is selected so as to obtain such a hetero junction between an inner layer 23 and the channel region 7 that shows discontinuity points at the valence band in the energy band chart in case of an n<-> channel vertical JFET. As the result, the barrier lowers and minority carriers are injected from the gate region and concentrated at the inner layer 23 and confined by a nearby potential barrier of Si resulting from the band discontinuity points of the valence band. Thus the base width of the transistor in a bipolar opeartion mode can be controlled to ensure a high switching speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor structure capable of forming a vertical junction field effect transistor capable of bipolar operation.

[0002]

2. Description of the Related Art In a conventional vertical junction field effect transistor (vertical JFET), a gate region is implanted in a semiconductor substrate due to a commonly used manufacturing method. The substrate has a first conductivity type (N for N-channel JFET transistors) and the gate region has the opposite conductivity type (P for N-channel JFET transistors). A channel region is formed in at least a part of the substrate, and a drain region is formed in the lower portion. For example, N-channel vertical J
When the gate of a FET transistor is forward biased with respect to the source, minority carriers (holes) injected into the channel region are between the source (acting as an emitter) and the drain (acting as a collector). It constitutes the electrical "base". Then, the transistor operates in the bipolar mode. Such an operation mode characteristically has a very high transconductance (transconductance), and is particularly useful for high speed.

[0003]

The optimization of this bipolar operating mode depends in particular on the width of the base thus formed. However, in the current transistor structure, it is impossible to control this width. The present invention has been made to obtain a more effective solution to this problem. It is an object of the invention to optimize the bipolar mode of operation of a vertical JFET transistor, in particular to provide a transistor with a very high switching speed. It is also an object of the present invention to provide a high switching speed transistor that can be easily assembled with existing technical resources. Another object of the present invention is to minimize or suppress the gate-to-substrate parasitic capacitance which is usually caused by the PN junction formed in such a transistor. The purpose of this invention is also to minimize the drain-to-substrate parasitic capacitance.

[0004]

Accordingly, the present invention provides a vertical junction field effect transistor having a semiconductor structure including a semiconductor inner layer extending in a channel region between gate regions, the inner layer forming the channel region and the gate region. And a heterojunction formed between the inner layer and the channel region is an N-type channel (P-type gate). In the valence band, P-type channel (N-type gate)
In the case of, the vertical junction field effect transistor is characterized in that it exhibits a band discontinuity in the conduction band.
The inner semiconductor layer (semiconductor inner layer) has a thickness of 2, 30
The Angstrom order is convenient.

According to one embodiment of the present invention, the material forming the gate region and the channel region is silicon,
On the other hand, the material forming the semiconductor inner layer is a silicon / germanium alloy. However, it is also possible to use a Group 3-5 group material as a material for forming the semiconductor inner layer and form the gate and channel regions with a ternary alloy of this Group 3-5 group material. According to an embodiment of the present invention, the semiconductor structure of the vertical junction field effect transistor as described above has an intermediate region, which can form a channel region having a first conductivity type, and a first conductivity type. The structure has a shape and is preferably provided on top of a first region where the drain region can be formed in the overdoped substrate as compared to the intermediate region. The intermediate region has a protrusion on which a second region, which also has the first conductivity type and which is preferably overdoped in comparison with the intermediate region, can be formed.
Area is provided. The semiconductor region also has a third region which has a conductivity type opposite to that of the above and which can preferably form an overdoped gate region, the gate region being a part of the intermediate region. It is located on both sides and is separated from the second region by an insulating isolation layer or spacer located around the protrusion; the inner layer extends into the intermediate region between the gate regions.

In this semiconductor structure, it is effective to provide an insulating layer outside the channel region between the gate region and the substrate in order to minimize or suppress the parasitic capacitance between the gate and the substrate. This insulating layer preferably has a thickness at least equal to the width of the space charge region of the PN junction obtained from the basic semiconductor material of the field effect transistor. This thickness is between about 0.2 and about 1 μm, preferably 0.5 μm.
Order. When manufacturing a transistor based on silicon, the channel, source and drain regions include single crystal silicon, while the insulating layer is silicon dioxide,
Conveniently, the gate region comprises polycrystalline silicon. It is particularly effective to provide the substrate on the insulating layer in order to minimize the parasitic capacitance between the drain and the substrate. Such a transistor can also be used in a bipolar operating mode. In that case, the drain region serves as a collector region, the source region serves as an emitter region, and the gate region serves as a base region.

The invention also resides in a method of forming a semiconductor structure capable of forming a junction field effect transistor or a bipolar transistor. According to one embodiment compatible with the BiCMOS type manufacturing technique, the method of the invention comprises: a) a first substrate on a semiconductor substrate comprising a first region having a first conductivity type (eg N type); It has a conductivity type and has an energy gap smaller than that of the material of the first region, and has no band gap in the valence band when the first conductivity type is N and in the conduction band when the first conductivity type is P. Depositing (evaporating) a surface layer of semiconductor material capable of forming a heterojunction containing continuous points; and b) removing a portion of this surface layer to expose a corresponding portion of the substrate, Delimiting the layers known as inner layers; and c) a laminated structure comprising on the structure thus obtained another layer of the same semiconductor material as the material forming the first region. And then next Depositing an upper layer also made of another semiconductor material having the first conductivity type; and d) forming second regions in the areas located on both sides of the inner layer, where source regions can be formed. Removing a portion of the laminated structure over a region near the top of the inner layer to form a protrusion that includes a portion of the upper layer on the top; and e) on both sides of the protrusion in the substrate. A contact type that is in contact with the inner layer and that is opposite to the first conductivity type, such as P
Implanting a third region capable of forming a gate region having a shape-conductivity and forming an insulating spacer in contact with a side surface of the protrusion; f) first, second and third Metallizing at least a portion of the region.

[0008] The semiconductor material forming the upper layer of the layered structure intended to form the source or emitter region is effectively overdoped polycrystalline silicon. According to one embodiment of the method of the present invention, in step e) above, first an implant of a dopant is first performed to provide the second conductivity type to the third region, and then spacers are provided on both sides of the protrusion. Is provided, a second dopant implant is performed to ensure a gradual overdoping of the gate region. According to another embodiment, the method of the invention comprises: a) on a semiconductor substrate comprising a first region having a first conductivity type, opposite to a first conductivity type formed by two layers of insulating material. Forming a layered structure including a layer of semiconductor material having a conductivity type of b); and b) forming a main orifice in the layered structure extending over the same length as the first region; In the main orifice, an intermediate region of a semiconductor material having a first conductivity type, an energy gap smaller than the first conductivity type and the material of the first region, and a valence electron if the first conductivity type is N. There is a band discontinuity in the obi,
If the first conductivity type is P, it has an inner layer of semiconductor material capable of forming a heterojunction having a band discontinuity in the conduction band, and also has the first conductivity type located above this intermediate region. Forming a second region; d) exposing a portion of the upper surface of the semiconductor layer of the stacked structure that is outside the channel region and spaced from it; e) the first region and the first region Forming metallization on at least a portion of the second region and at least a portion of the exposed portion of the semiconductor layer of the stacked structure.

In the present invention, it is particularly effective to overdope the first and second regions and the semiconductor layer of the stacked structure so as to ensure better electrical contact with various metallizations. It is particularly desirable if the semiconductor structure is formed on the base. According to one embodiment of the method of the present invention, the step of forming the intermediate region, the interior and the second region comprises a first deposition step of the first semiconductor layer by epitaxy to form the lower part of the intermediate region, This is followed by a second deposition step of the inner layer by epitaxy, followed by a third deposition step by epitaxy forming the intermediate region and the second region. These depositions by epitaxy are preferably carried out by selective epitaxy in the main orifice. The face on top of the laminated semiconductor layer can be exposed by an etching process such as a reactive ion etching operation. To ensure access to the first region where the drain region can be formed, the semiconductor layer deposited on the first insulating layer in contact with the substrate is removed from the portion where the main orifice is formed. Only a portion in a predetermined auxiliary area at a distance is removed; then, in this auxiliary area, a second insulating layer of laminated structure is applied,
An auxiliary orifice is formed extending over the first region of the substrate, and a contact region having the same doping as that of the first region is formed in the auxiliary orifice. Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the accompanying drawings.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to a vertical N-channel JFET
Although illustrated by the examples of transistor structures and fabrication methods, the invention is of course applicable to P-channel JFET transistors by making all the dopant types described below of opposite nature. Is. In FIG. 1, reference numeral 1 indicates a solid substrate of silicon doped according to the P conductivity type (electrical conduction is performed by holes). Implanted in this substrate is a first region 2 of opposite conductivity type, ie N conductivity type (electrical conduction by electrons). This first region is overdoped with N ⁺⁺ , for example with an electron concentration of the order of 10 ²⁰ cm ⁻³ , compared to the region 7 of N-type silicon capable of forming the channel of a junction transistor. The electron concentration in the N-doped region is of the order of 10 ¹⁷ cm ^-3 . On top of this intermediate region 7 (referred to as the channel region) is provided a second region 8 which is also of N conductivity type and which is overdoped relative to the channel region, on which a metallization 9 is provided. It is provided.

Regions 7 and 8 of the JFET transistor are
The conductive type opposite to the channel region (ie, P in this case) with a thickness of 1000-2000 A (angstrom) formed by overdoped polycrystalline silicon.
Located (at least partially) within a main orifice 6 formed in a laminated structure including a semiconductor layer 4 having a shape.
On the lower side of the semiconductor layer 4, a first layer that is substantially parallel to the upper surface of the substrate 1 and extends in the same range as the substrate 1 is formed.
The insulating layer 3 is provided outside the lower portion of the channel region 7. The first insulating layer is formed of, for example, silicon dioxide and has a thickness on the order of 0.5 to 0.7 μm. Inside the intermediate region 7, a layer 23 made of a silicon / germanium alloy Si _1-x Ge _x (eg x = 0.5) extends between the ^overdoped P ⁺⁺ semiconductor layers 4. . This layer 23 is a thin layer, typically having a thickness on the order of 2,30 angstroms. This semiconductor layer is N-type doped like the intermediate region 7 called the channel region.

In general, the choice of these semiconductor materials is such that between this inner layer 23 and the so-called channel region 7 an N-
In the case of a channel vertical JFET transistor, this was done to obtain a heterojunction with an energy band diagram exhibiting band discontinuities in the valence band. The energy band diagram obtained in the vertical direction is shown in FIG. The symbol Ff indicates the Fermi level, and the symbol Eg1 indicates the energy gap between the low level Ec of the conduction band BC of silicon and the high level Ev of the valence band BV of silicon. Symbol E
g2 represents the energy gap of the silicon / germanium alloy used. Although these two materials have almost the same conduction band, there is a difference in energy gap, and this difference Eg2-Eg1 is approximately 0.37 eV in the case of Si _1-x Ge _x (x = 0.5) alloy. be equivalent to. As a result, a discontinuity in the valence band equal to approximately 0.37 eV is obtained in the heterojunction region. Transistor is P-
In the case of a channel JFET, it is effective to select a pair of semiconductor materials whose energy band diagram shows band discontinuities in the conduction band.

Corresponding to the energy band diagram obtained in the vertical direction, the energy band diagram along the horizontal direction shown in FIG. 3 shows a heterojunction between the semiconductor region 4 and the inner layer 23.
It has been shown that in the valence band, it has a potential barrier height that is h lower than that normally present between P ⁺⁺ N-type silicon junctions. The effect of these energy band diagrams will be described in more detail below in the context of bipolar operation of JFET transistors. Of course, other semiconductor material combinations can be used to obtain such a heterojunction. As a material for forming the inner layer 23, Group 3-5
A group material, that is, a material such as an alloy of gallium arsenide, containing equal amounts of an element of group 3 and an element of group 5 of the Mendeleev's periodic table can be used. In that case, for the material forming the semiconductor region 4 and the intermediate channel region 7, for example, a ternary alloy of this Group 3-5 group material such as a GaAlAs alloy can be used.

Part of the channel region 7 and the second region 8
An insulating spacer 5, which is also formed of, for example, silicon dioxide, is provided around the upper protrusion of the above-described structure in which the is provided. These spacers are also spacers 5.
A metallization 10 extending over the same area has the special function of separating the region 4 and the second region 8 provided thereon. An auxiliary orifice 11 is formed in an auxiliary area of the transistor located at a constant distance from the area where the main orifice 6 is located. This auxiliary orifice is filled with overdoped N-type silicon, which contacts the buried region (first region) 2 at the bottom and the region 12 with the metallization 13 at the top. Form. As is apparent from the figure, the end portion of the semiconductor layer 4 is located at a position separated from the region 12 of the opposite conductivity type provided in the orifice 11 by a certain distance. When this semiconductor structure is used as a junction field effect transistor, the semiconductor layer 4 constitutes a gate region with a gate contact (metallization) 10 and the overdoped region 8 comprises a source with a source contact (metallization) 9. The part of the region 2 which forms the region and lies below the channel region 7 forms the drain region of the transistor which is connected to the drain contact (metallization) 13 by the region 12 provided in the auxiliary orifice 11.

The diameter of the orifice 6 is made smaller than about 1 μm, which in this embodiment ensures that the transistor is blocked in relation to the doping used (transistor is normally off). , A significant overlap of the space charge region of the gate / source junction can be obtained when the gate / source bias voltage is zero. Of course, one skilled in the art will be able to adjust the diameter of the orifice and its different values as a function of doping so that the blocking condition is ensured when V _GS is zero. Is easy to understand. Furthermore, for certain applications it is possible to envisage the production of normally-on transistors. In that case, it will be apparent to those skilled in the art how to adjust the diameter of the orifice 6. Such a transistor can also be used in bipolar operation. In that case, the drain, source and gate regions of the field effect transistor respectively form the collector, emitter and base regions of the bipolar transistor. Needless to say, this N-channel JFE
To use the T-transistor in bipolar operation mode, forward bias the gate region with respect to the source region,
That is, it is necessary to provide a gate / source voltage higher than about 0.7 volt.

In the bipolar mode of operation, the energy band diagrams shown in FIGS. 2 and 3 have essentially two consequences: Minority carriers from the gate (base) region (in this case holes). ) Is concentrated in the inner layer 23 due to the lower barrier height. The injection efficiency into this layer is multiplied by a coefficient that is an exponential function of the ratio of the energy difference ΔeV at the energy gap discontinuity to the product of the Boltzmann constant and temperature. This coefficient is Si _1-x at a temperature of 300 ° K.
For a Ge _x (x = 0.5) alloy, on the order of 10 ⁶ for implantation into the surrounding channel region. Minority carriers (holes) injected into the layer 23 are kept confined therein by a potential barrier due to adjacent silicon caused by band discontinuities in the valence band (in this example).

Thus, this heterostructure in the channel region makes it possible to accurately control the base width of the transistor in the bipolar operation mode. This was not possible with conventional vertical JFET transistors. In addition, this inner layer is doped in the same way as the middle channel region,
The out-diffusion problem that occurs when the doping is inhomogeneous and tends to widen this electrical base can be avoided. In this way, a bipolar transistor having a very thin base, on the order of 2,30 angstroms, can be obtained, which can significantly increase the speed of movement in the base and have excellent dynamic performance characteristics. It becomes possible. Since the transistor of this embodiment is formed on an integral P-type substrate, it is possible to separate several transistors of the same kind, which are especially formed on the same P-type silicon chip, from one another. . Of course, if desired, the transistor could be made from an integral N-type silicon substrate with overdoped region 2 implanted.

Further, in this embodiment, the drain, source and gate regions are overdoped to provide better electrical contact between the metal and the silicon used as the base semiconductor. However, when using a semiconductor material capable of ensuring sufficient direct electrical contact with the metallization,
It is also possible to omit overdoping of these areas. Such a semiconductor material is selected from Group 3-5 type materials. Generally, the width of the first insulating layer 3 located below the gate outside the region of the channel area is determined by the space charge of the PN junction between the gate area and the substrate in the conventional vertical JFET transistor. It should be equal to the width of the area. The gate / substrate parasitic capacitance is effectively reduced by the low dielectric constant of the insulator. Therefore, the minimum thickness of the insulating layer is
Thicknesses on the order of 0.2 μm are commonly used. The maximum value of this thickness is generally less than 1 μm so that the vertical resistance for accessing the drain or collector does not become excessive.

Next, a method for manufacturing the transistor of FIG. 1 will be described in more detail with reference to FIGS. The first step of this method is to provide a substrate 1 (FIG. 4) implanted with an overdoped N-type region 2 with a first insulator layer 15 and a conductivity type opposite to the region 2 above. This is a step of growing the laminated structure 14 including the semiconductor layer 16 and the second insulating layer 17 formed thereon. In practice, first an insulator layer 15 (silicon dioxide in this example) is deposited on the substrate 1 by conventional methods. Next, polycrystalline silicon overdoped to give the P conductivity is deposited, after which a second insulating layer 17, also composed of silicon dioxide, is deposited on this polycrystalline silicon. If it is desired to provide a drain contact on the front side of the transistor, a part of the semiconductor layer 16 is removed in the auxiliary area 22 by reactive ion etching, for example, before depositing the second insulator layer 17. .

Next, the main orifice 6 is formed in the laminated structure 14 by, for example, reactive ion etching (FIG. 5), and if possible, the auxiliary orifice 11 is formed in the auxiliary area 22 without the polycrystalline silicon 16. These orifices extend within the overdoped region 2. It is noted here that the maximum thickness of 1 μm adopted so that the vertical resistance to access to the drain is not too high is well compatible with the prior art formation of the orifice 6 having a submicron diameter. . The next step is to form the channel region 7, the inner layer 23 and the region 8 in the orifice 6. To do so, N-type silicon is grown in the orifice 6 by selective epitaxy until it reaches the level of the semiconductor layer 16, and then the silicon / germanium layer 2 is deposited.
Grow to form 3. N-type silicon is deposited on this layer until it reaches the upper surface of the layered structure, and then ion implantation of, for example, phosphorus or arsenic is performed in order to overdope the region 8. Selective epitaxy is performed even in the auxiliary orifice 11, and then the region 12 is obtained by ion implantation of phosphorus.

The next step (shown in FIG. 7) is to expose the top surface of the semiconductor layer 4 of the laminated structure over a certain distance from this region around the channel region 7 and provide spacers 5 of selected thickness. Is to be done.
The remaining portion of the laminated structure located in the auxiliary area of the auxiliary orifice 11 is preferably flush with the surface including the upper surface of the semiconductor layer 4. The final step of the method of this example is
To form a silicide layer on the semiconductor silicon area (TiSi ₂ ), metallizations 9, 10 and 13 are formed by known techniques of the salicide (self-aligned silicide) type including the deposition of a metal layer (eg titanium). It is to provide. Here, the transistor orifices 6 and 11
Although selective epitaxy was used to form the semiconductor region inside, it is also possible to perform simple epitaxy on the entire laminated structure with these orifices and then perform an etching step to remove excess semiconductor deposits. Will.

Similarly, it is desirable to perform the operation of forming spacers by etching after the step of selective epitaxy in the orifice 6. However, the spacer 5 is first formed, and then the selective epitaxy in the orifice 6 is performed. It would be possible. Although the present invention fully exerts its advantages in the above-described embodiment, depending on the application, it may be better to use the one in which the substrate is arranged on the insulator instead of the integral substrate.
It has been demonstrated to be even more effective in minimizing parasitic capacitance between substrates or between collector / substrate. A structure in which a substrate is provided on such an insulator 18 is schematically shown in FIG. In this structure, an insulating layer 20 of silicon dioxide is provided on an underlayer region 19 of silicon on which another silicon of P or N type serving as the substrate 1 shown in FIGS. 1 and 4 to 7 is provided. A layer 21 is provided. Such a substrate is known to those skilled in the art by the name of SOI (Silicon On Insulator).

Hereinafter, referring to FIG. 9, it is possible to apply CMOS manufacturing technology (complementary insulated gate field effect transistor is formed on the same chip) or BiCM0S (CMOS with bipolar transistor added). Examples of the transistor of the present invention will be described below. Overdoped drain region 25 at the bottom
In the N-type silicon substrate 24 having, there is provided a protrusion whose side surface is covered with the insulating spacer 33. This protrusion has, at its top, a region 29 on which a source or an emitter (in this embodiment N ⁺⁺ overdoped polycrystalline silicon) can be formed.
With a metallization 30 covering. This area 29
Under, there are actually over-doped N-type silicon layer 28 in the N ⁺⁺ obtained during high temperature diffusion phase of the structure. This overdoped layer 28
Underneath, a layer 27 of N-type silicon is provided on an inner layer 26 formed of a silicon / germanium alloy.

This inner layer 26 extends between the P-type gate regions 31 implanted in the substrate 24.
Metallization 32 is provided on these areas 31. The drain contact 35, which is formed of N ^{+ +} overdoped silicon and is covered by the metallization 36, has a conventional LOCO structure.
S) method (“Local oxidation of silicon (Local oxi
The gate region 31 is separated by an insulating region (e.g. silicon dioxide) 34 implanted by means of a "diffusion of silicon)". A method of forming such a structure, basically in the context of forming inner layer 26, is illustrated in FIGS. After depositing a surface layer of silicon / germanium on the semiconductor substrate 24 of N-type silicon whose lower region is overdoped or, in some cases, on the P-type semiconductor substrate in which an N-type well is formed, the area 37 A portion of this surface layer is removed within to expose the corresponding portion of the substrate, thereby defining the boundary of the inner layer 26 that will be formed later.

Next, on the structure thus obtained,
A layered structure is deposited that includes a layer 27 of N-type silicon overlying a layer 29 of N-type polycrystalline silicon that is overdoped to be N ^{++ type} . Then, etching is performed in areas located on both sides of the inner layer 26 so that a part of the laminated structure thus formed is formed so as to form the protrusion of the heterojunction transistor (see FIG. 1).
Remove over the area near the top of 1).

Next, on both sides of this protrusion, a first implant of the selected dopants is carried out, giving a P-type conductivity to the regions implanted with these dopants. After that, spacers 33 that contact the side surfaces of the protrusions are formed by, for example, depositing silicon dioxide, and then anisotropic etching is performed. After that, a second time of implanting the dopant is performed on both sides of the protrusion where the spacer is formed.
The gate region is progressively (P ⁺ ,
P ⁺⁺ ) overdoping. Those skilled in the art will understand that the above-mentioned transistor structure and the manufacturing method thereof are CM
Since at least part of the same masking used in the fabrication of OS transistors can be used, C
It can be easily understood that it can be applied to the manufacturing technology of the MOS type transistor.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a JFET transistor according to the present invention.

FIG. 2 shows two energy band diagrams, respectively, along two orthogonal directions associated with a terror junction occurring in a transistor.

FIG. 3 shows two energy band diagrams respectively along two orthogonal directions associated with a terror junction occurring in a transistor.

FIG. 4 is a schematic cross-sectional view showing various steps of a method for manufacturing a transistor according to the present invention.

FIG. 5 is a schematic cross-sectional view showing various steps of a method of manufacturing a transistor according to the present invention.

FIG. 6 is a schematic cross-sectional view showing various steps of a method for manufacturing a transistor according to the present invention.

FIG. 7 is a schematic cross-sectional view showing various steps of a method for manufacturing a transistor according to the present invention.

FIG. 8 is a schematic cross-sectional view showing another example of a substrate used for manufacturing another type of JFET transistor of the manufacturing method of the present invention.

FIG. 9 is a schematic sectional view showing another embodiment of the JFET transistor according to the present invention.

FIG. 10 is a schematic cross-sectional view showing various steps of another embodiment of the method for manufacturing a transistor according to the present invention.

FIG. 11 is a schematic cross-sectional view illustrating various steps of another embodiment of the method for manufacturing a transistor according to the present invention.

FIG. 12 is a schematic cross-sectional view showing various steps of another embodiment of the method for manufacturing a transistor according to the present invention.

[Explanation of symbols]

 1 Substrate 2 First Region 3, 20 Insulating Layer 4 Semiconductor Region 5, 33 Insulating Spacer 6 Main Orifice 7 Intermediate Region (Channel Region) 8 Second Region 9, 30, 32, 36 Metallization 10 Gate Contact (Metals) 11) Auxiliary orifice 12 Region provided in the auxiliary orifice 11 13 Drain contact (metallization) 14 Laminated structure 15 First insulator layer 16 Semiconductor layer 17 Second insulator layer 18 Insulator 19 Lower layer region 21, 29 Silicon layer 22 Auxiliary area 23, 26 Inner layer 24 N-type silicon substrate 25 Drain region 27 N-type silicon layer 28 Overdoped layer 31 P-type gate region 34 Insulation region

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 21/337 29/808 9171-4M H01L 29/80 C

Claims (21)

[Claims] 1. An energy gap (Eg2) smaller than the material forming the channel region and the gate region extending in the channel region (7) between the gate regions (4, 31).
And a semiconductor structure including a semiconductor inner layer (23, 26) formed of a semiconductor material having the same conductivity type (N) as the channel region, and a heterojunction formed between the inner layer and the channel region, A vertical junction field effect transistor characterized by exhibiting a band discontinuity in the valence band for an N-type channel and exhibiting a band discontinuity in the conduction band for a P-type channel. 2. Transistor according to claim 1, characterized in that the thickness of the inner semiconductor layers (23, 26) is of the order of 2,30 Å. 3. The transistor according to claim 1, wherein the material forming the gate region and the channel region is silicon, and the material forming the inner layer is a silicon / germanium alloy. 4. The material forming the inner layer is a Group 3-5 group material, and the material forming the gate region and the channel region is a ternary alloy of the Group 3-5 group material. The transistor according to any one of claims 1 to 3. 5. The semiconductor structure is: an intermediate region (7) capable of forming a channel region having a first conductivity type (N), also having a first conductivity type (N ⁺⁺ ). An intermediate region provided on top of the first region (1) capable of forming a drain region in the substrate; a part of the channel region (7) and also of the first conductivity type (N ^++). And a protrusion incorporating a second region (8) provided above the channel region capable of forming a source region having :) disposed on both sides of a part of the channel region (7); At the same time, it is possible to form a gate region having an opposite conductivity type (P ⁺⁺ ) separated from the second region (8) by an insulating isolation layer (5) arranged around the protrusion. A third region (4); and the inner layer is a gate Transistor according to any one of claims 1 to 4, characterized in that the spread in the intermediate region between the band. 6. The semiconductor structure according to claim 1, further comprising an insulating layer (3) disposed outside the channel region between the gate region and the substrate. Transistor. 7. The transistor of claim 6, wherein the gate region comprises a layer substantially parallel to the substrate and separated from the substrate by the insulating layer. 8. The insulating layer (3) has a thickness which is at least equal to the width of the space charge region of a P-N junction formed of the basic semiconductor material of the field effect transistor. Or the transistor according to 7. 9. Insulation layer (3) according to claim 6, characterized in that it has a thickness of the order of about 0.2 μm to 0.5 μm, preferably about 1 μm. The described transistor. 10. The channel, source and drain regions comprise single crystal silicon, the insulating layer comprises silicon dioxide and the gate region comprises polycrystalline silicon. The transistor according to item. 11. The transistor according to claim 1, wherein the drain (2), source (8) and gate (4) regions are overdoped. 12. The substrate is an insulator (18)
A transistor according to any one of the preceding claims, characterized in that it is a substrate arranged above. 13. The collector of a bipolar transistor, wherein the drain, source and gate regions respectively correspond to each other,
13. Transistor according to any one of claims 1 to 12, for bipolar operation mode, characterized in that it comprises an emitter and a base region. 14. A method of forming a semiconductor structure capable of forming a field effect or bipolar junction transistor: a) a semiconductor substrate (1) comprising a first region (2) having a first conductivity type. , 18) forming a laminated structure (14) comprising a layer (16) of semiconductor material having a conductivity type opposite to the first conductivity type formed by two layers of insulating material (15, 17); b) forming in this laminated structure a main orifice (6) extending over a range of the same length as the first region (2); c) in this main orifice (6) a first conductivity type. Having a smaller energy gap than the material of the intermediate region (7), the first conductivity type (N), and the intermediate region (7) of a semiconductor material having N and having a band in the valence band when the first conductivity type is N. There are discontinuities, An inner layer (23) of semiconductor material capable of forming a heterojunction having a band discontinuity in the conduction band when the first conductivity type is P, and also the first conductivity located above this intermediate region. Forming a second region (8) having a shape; and d) covering a portion of the upper surface of the semiconductor layer (16) of the stacked structure (14) over a range of a certain distance around the intermediate region (7). E) exposing at least a portion of the first region (2) and the second region (8) and at least a portion of the exposed portion of the semiconductor layer of the laminated structure (14) on the upper surface of the meta. Forming an isolation (9, 10, 13). 15. Step c) comprises a first deposition by epitaxy to form the bottom of the intermediate region, followed by a second deposition by epitaxy to form the inner layer, and the intermediate region and the second. 15. Method according to claim 14, characterized in that it comprises a third deposition by epitaxy to form the upper part of the region (8). 16. The method of claim 15, wherein the epitaxy deposition is selective epitaxy deposition in the main orifice. 17. A method according to any one of claims 14 to 16, characterized in that the step of forming the main orifice (6) and the step d) comprise an etching operation. 18. In said step a), said semiconductor layer (16) is deposited on a first insulating layer (15), then a part of this semiconductor layer (16) covers said main orifice (6). Removed from within an auxiliary area at a certain distance from the area to be formed and then applied with a second insulating layer (17), in the layered structure the first region (2) An auxiliary orifice (11) is formed in the auxiliary area extending over the area of the auxiliary orifice (11), which is preferably an overdoped region having the same conductivity type as the first region (2). 18. Metallization is performed (13) on the upper surface of the semiconductor region (12) in which the (12) is formed and in the auxiliary orifice (11), according to any one of claims 14 to 17. The method of mounting. 19. A method of forming a semiconductor structure capable of forming a field effect or bipolar junction transistor: a / a first region (2) having a first conductivity type (eg N).
5) having a first conductivity type (N) and a smaller energy gap than the material of the first region (25) on the semiconductor substrate (24) including the first conductivity type N. Depositing (evaporating) a surface layer of a semiconductor material capable of forming a heterojunction containing a band discontinuity in the conduction band when the first conductivity type is P, in the case of valence band; b. / Removing a portion of this surface to expose a corresponding portion of the substrate, thereby demarcating a layer known as the inner layer (26); c / on the structure thus obtained, Depositing a stack structure comprising another layer (27) of the same semiconductor material as the material forming said first region (25) and then also having a first conductivity type (N ⁺⁺ ). Upper layer made of other semiconductor material (29 A step of depositing; d / the area located on either side of the inner layer (26) (37)
Removing a part of the laminated structure over a range near the upper part of the inner layer (26) so as to form a protrusion having an upper part of the upper layer forming the second region (29). E / Implanting, on both sides of the protrusion in the substrate, a third region (31) contacting the inner layer (26) and having a conductivity type (P-type) opposite to the first conductivity type, and Forming an insulating spacer in contact with a side surface of the protrusion; f / metallization (30) on at least a portion of the first and second regions and at least a portion of the exposed semiconductor layer of the stacked structure. , 32, 36). 20. The method of claim 19, wherein the material forming the second region is overdoped polycrystalline silicon. 21. In step e /, spacers are formed after the first implant with the selected dopant, and then selected to achieve a gradual overdoping of the third region. 21. The method according to claim 19 or 20, characterized in that the second implant is performed with a different dopant.