JPH07283406A - Horizontal type semiconductor device - Google Patents

Abstract

PURPOSE:To reduce ion resistance due to conductivity modulation by providing a semiconductor area of a second conductivity type for carrier implantation on one major surface of a first semiconductor area with an interval from a second and fourth semiconductor areas and arranging a carrier implantation electrode on the surface of the semiconductor area for carrier implantation with contact to the surface. CONSTITUTION:A high operating voltage is applied between a drain electrode 10 and a source electrode 11, and a voltage which exceeds the diffusion potential at a pn junction part between a P-type carrier implantation area 5 and an N-type base area 1 and a pn junction part between a P-type buried area 7 and an N-type base area 7 is applied to a carrier implantation electrode 9. At that time, since carriers are injected to the N-type base area 1 from the P-type carrier injection area 5 and the P-type buried area 7, the conductivity of the N-type base area 1 is modulated, and when the horizontal semiconductor device is turned on, the on resistance of the N-type base area 1 and the N-type drain electrode 4, namely, drain resistance, is remarkably reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-driven lateral semiconductor device, and more particularly to a voltage-driven lateral semiconductor device in which internal power loss during conduction is reduced by reducing on-resistance during conduction. Regarding

[0002]

2. Description of the Related Art Generally, a voltage-driven lateral semiconductor device is provided in a single integrated circuit in which a plurality of unit elements, for example, a MOSFET (MOS field effect transistor), an IGBT (insulated gate bipolar transistor), or the like is used as a unit element. Integrated into a single MOSFET or IG
It functions as a BT, and when various inverters, power supply devices, power amplifiers, oscillators, analog switches, etc. are configured, one or more integrated circuits functioning as the MOSFETs and IGBTs are used. There is.

Such a voltage-driven lateral semiconductor device has characteristics that power loss during operation is extremely small and good control is possible as compared with a current-driven semiconductor device such as a bipolar transistor. In particular, such characteristics are important when controlling high voltage or high power.

FIG. 8 (a) is a cross-sectional view showing an example of a known MOSFET typical as a voltage-driven lateral semiconductor device, and FIG. 8 (b) is also a typical voltage-driven lateral semiconductor device. FIG. 1 is a cross-sectional configuration diagram showing an example of a known IGBT, which is “IEEE IEEEDM”.
Technical Digest "B.I. J. Bal
iga et al., pp. 264-267 (1982).

As shown in FIG. 8A, a known MO
The SFET is configured in an island shape inside the polycrystalline silicon supporting substrate 55 with an insulating separation film 57 interposed therebetween, and has an n-type low impurity concentration base region (n−) 51, the base region 51 and the insulating separation film 57. And an n-type high-impurity-concentration buried region 56 interposed between and. On each part of one main surface of the base region 51, a p-type well region 52 and an n-type high impurity concentration drain region 54 are selectively formed so as to be separated from each other, and an insulating film 58 is arranged and formed. Two n-type source regions 53 are selectively formed on the surface of the well region 52, and the drain region 54 is arranged adjacent to one end of the buried region 56. A drain electrode 59 is arranged in contact with the surface of the drain region 54, and a source electrode 60 is arranged in contact with the surfaces of the two source regions 53. 1 of base area 51
A gate electrode 61 is arranged on the main surface, the surface of the well region 52 and the surface of the source region 53 with an insulating film (not shown) interposed therebetween.

Further, as shown in FIG. 8 (b), the known IGBT is also constructed in an island shape inside the polycrystalline silicon supporting substrate 55 with an insulating separation film 57 interposed therebetween.
It has an n-type low impurity concentration base region (n−) 51 and an n-type high impurity concentration buried region 56 interposed between the base region 51 and the insulating separation film 57. Base area 5
On each part of one main surface of 1, the p-type well region 52 and the n-type high impurity concentration buffer region 62 are selectively formed so as to be separated from each other, and the insulating film 58 is arranged and formed. Two n-type source regions 53 are selectively formed on the surface of the well region 52, a p-type carrier injection region 63 is formed on the surface of the drain region 54, and the drain region 54 is adjacent to one end of the buried region 56. Will be placed. A collector electrode 64 is disposed in contact with the surface of the carrier injection region 63,
An emitter electrode 65 is arranged in contact with the surfaces of the two source regions 53. A gate electrode 61 is arranged on a portion extending over one main surface of base region 51, the surface of well region 52, and the surface of source region 53 with an insulating film (not shown) interposed.

In the above structure, the known MOTFE is known.
The operation of T is, as already known, the drain electrode 5
When a control voltage (turn-on voltage) higher than the voltage of the source electrode 60 is supplied to the gate electrode 61 with a predetermined operating voltage applied between the gate electrode 61 and the source electrode 60, the MOTFE
T is turned on, and a predetermined conduction current flows between the drain electrode 59 and the source electrode 60. On the other hand, when the conduction current is flowing, the source electrode 6 is added to the gate electrode 61.
When a control voltage (turn-off voltage) lower than 0 is supplied, the MOTFET is turned off and the current flow between the drain electrode 59 and the source electrode 60 is cut off.

In the operation of the known IGBT, as already known, the voltage of the emitter electrode 65 is applied to the gate electrode 61 with a predetermined operating voltage applied between the collector electrode 64 and the emitter electrode 65. When a control voltage (turn-on voltage) higher than the above is supplied, the IGBT is turned on and the collector electrode 64 and the emitter electrode 65 are turned on.
A predetermined conduction current flows between them. On the other hand, when a control voltage (turn-off voltage) lower than the voltage of the emitter electrode 65 is supplied to the gate electrode 61 while the conduction current is flowing, the IGBT is turned off, and the IGBT between the collector electrode 64 and the emitter electrode 65 is turned off. The current flow is cut off.

[0009]

DISCLOSURE OF THE INVENTION The known MOSFE
At T, in order to be able to control a high operating voltage, it is necessary to increase the thickness of the base region 51 and reduce its impurity concentration. However, if the impurity concentration of the base region 51 is reduced and the thickness thereof is increased, the MOSFET
Has a problem that the ON resistance of the base region 51 becomes high and the power loss of this portion, that is, the power loss of the MOSFET becomes extremely large.

The known IGBT has a carrier injection region 6 in the drain region 54 of the known MOSFET.
3 has a structure in which the carrier is injected into the base region 51 from the carrier injection region 63 and the conductivity of the base region 51 is modulated when the IGBT is in a conductive state. Therefore, the on-resistance of the base region 51 is reduced to about 1/4 of the on-resistance of the MOSFET. On the other hand, the IGBT is n
By a pn junction formed between the p-type buffer region 62 and the p-type carrier injection region 63.
Since there is a voltage drop of 8V, the collector voltage is 0V
A conduction current cannot flow in the vicinity. Therefore, in the IGBT, even if the conductivity is sufficiently increased by modulating the conductivity of the base region 51, the power loss due to the voltage drop cannot reduce the power loss of the IGBT below a certain value. There is.

Therefore, in order to eliminate the problem as seen in the IGBT, the conductivity of the base region 51 is modulated without causing the power loss due to the voltage drop occurring at the pn junction. The element is MICFET (M
inority Carrier Injection
Controlled Field-Effect T
It has already been developed as a transmitter.

FIG. 9 is a cross-sectional view showing an example of such a known IGBT, which is "IEEE Trans. El.
electron Device "Vol. 39 (199
2) B. J. Baliga et al., Pp 1954-19.
59.

As shown in FIG. 9, this known MIC
The FET includes an n-type low impurity concentration base region (n−) 51 and an n-type high impurity concentration buffer region (n +) 62 which is arranged on one main surface of the base region 51 so as to be joined to the surface of the buffer region 62. Is disposed in contact with the drain electrode 64. In a part of the other main surface of the base region 51, a p-type floating region 66 is selectively formed on the surface side and a p-type high impurity concentration region (p +) 67 is selectively formed on the inner side, and an n-type source region 53 is formed in the floating region 66. Are selectively formed. A source electrode 65 is arranged in contact with the surface of the source region 53, and a floating electrode 68 is arranged in contact with each surface of the source region 53 and the floating region 66. The other main surface of the base region 51 and the floating region 66
A gate electrode 61 is arranged on a portion extending from the surface of the source region 53 to the surface of the source region 53 via an insulating film (not shown).

The basic operation of this MICFET is almost the same as that of the above-mentioned MOSFET and IGBT, and it is already known. Therefore, the explanation of this basic operation is omitted.

By the way, in the MICFET, in order to cause the conductivity modulation by the injection of carriers,
It is necessary to form the p-type high impurity concentration region 67 inside the floating region 66. However, not only is it difficult to form the p-type high impurity concentration region 67, but the pinch resistance increases due to the arrangement of the p-type high impurity concentration region 67, so that the on-resistance of the base region 51 is high when the MICFET is in the conductive state. Grows larger. Also, this MICF
When the base region 51 is thick, ET has a conductivity modulation only in the vicinity of the floating region 66, so that there is a limit to the reduction of the on-resistance, and the p-type high impurity concentration region 67 exists. By the base region 51, p
There is a new problem that the hfe of the parasitic transistor due to the high impurity concentration region 67 of the type and the source electrode 65 becomes large, and the MICFET easily latches up.

The present invention eliminates the above-mentioned problems, and an object thereof is to enable reduction of on-resistance due to modulation of conductivity and to eliminate voltage drop due to a pn junction to make power loss extremely small. Another object of the present invention is to provide a lateral semiconductor device that is hard to latch up.

[0017]

In order to achieve the above object, the present invention provides a first semiconductor region of a first conductivity type arranged in a substrate and a selective arrangement on one main surface of the first semiconductor region. The second semiconductor region of the second conductivity type, the third semiconductor region of the first conductivity type selectively arranged on the surface of the second semiconductor region, and the second semiconductor on one main surface of the first semiconductor region. A fourth semiconductor region of the first conductivity type spaced apart from the region; a buried semiconductor region disposed between the first semiconductor region and the substrate; a main surface of the first semiconductor region; A control electrode disposed over the respective surfaces of the second semiconductor region and the third semiconductor region via an insulating film, and a first main electrode disposed in contact with the respective surfaces of the second semiconductor region and the third semiconductor region. , A second main body arranged in contact with the surface of the fourth semiconductor region In a lateral semiconductor device having a pole, a second conductivity type carrier injection semiconductor region spaced apart from the second and fourth semiconductor regions is provided on one main surface of the first semiconductor region, A first means is provided in which a carrier injection electrode is arranged in contact with the surface of the carrier injection semiconductor region.

Further, in order to achieve the above object, the present invention provides a first semiconductor region of a first conductivity type disposed in a substrate and a second semiconductor region selectively disposed on one main surface of the first semiconductor region. A second semiconductor region of a conductivity type, a third semiconductor region of a first conductivity type selectively arranged on the surface of the second semiconductor region, and one main surface of the first semiconductor region with respect to the second semiconductor region. A first conductive type fourth semiconductor region spaced apart from each other, a buried semiconductor region disposed between the first semiconductor region and the substrate, one main surface of the first semiconductor region, and the second semiconductor region. And a control electrode arranged over each surface of the third semiconductor region via an insulating film, a first main electrode arranged in contact with each surface of the second semiconductor region and the third semiconductor region, and the fourth electrode. A second main electrode arranged in contact with the surface of the semiconductor region In the lateral semiconductor device, the fifth semiconductor region of the second conductivity type is disposed on one main surface of the first semiconductor region and is spaced apart from the second and fourth semiconductor regions, and is also spaced apart from each other. And a carrier injection semiconductor region, a third main electrode is arranged on the surface of the fifth semiconductor region in contact with a carrier injection electrode on the surface of the carrier injection semiconductor region, and the control electrode is formed on the fifth semiconductor region. And a second means that is extendedly disposed on one main surface of the first semiconductor region between the carrier injection semiconductor region and an insulating film.

[0019]

According to the first means, the n of the lateral semiconductor device is
On one main surface of the type base region (first semiconductor region), a p-type well region (second semiconductor region) and an n-type drain region (fourth semiconductor region) are formed.
A carrier injection region (carrier injection semiconductor region) having a high p-type impurity concentration that is spaced apart from the semiconductor region, and a carrier injection electrode is placed in contact with the surface of the carrier injection region. A voltage exceeding the diffusion potential of each pn junction between the injection region and the n-type base region and between the buried region (buried semiconductor region) and the n-type base region is applied, and n is applied from the carrier injection region.
Since carriers (for example, holes) are effectively injected into the type base region, the on-resistance of the n-type base region can be significantly reduced when this lateral semiconductor device is in the on state, and internal power loss can be reduced. It is possible to obtain a lateral semiconductor device having a very small value and causing no latch-up. Furthermore, since this lateral semiconductor device does not have a pn junction portion that causes a voltage drop inside unlike the known IGBT, it becomes possible to operate even if the collector voltage drops to around 0V. .

According to the second means, the p-type well region (second semiconductor region) and the n-type drain region (second semiconductor region) are formed on one main surface of the n-type base region (first semiconductor region) of the lateral semiconductor device. A p-type second source region (fifth semiconductor region) and a p-type high-impurity-concentration carrier injection region, which are spaced apart from each other with respect to the fourth semiconductor region). The second source electrode (third main electrode) is arranged in contact with the surface of the source region, the carrier injection electrode is arranged in contact with the surface of the carrier injection region (carrier injection semiconductor region), and the gate electrode (control electrode) is formed into the p-type second electrode. The carrier injection electrode and the n-type base region are extendedly arranged on one main surface of the n-type base region between the source region and the carrier injection region via an insulating film, and a predetermined voltage is applied to the carrier injection electrode. Between and A voltage exceeding the diffusion potential of each pn junction between the free region (buried semiconductor region) and the n-type base region is applied to effectively generate carriers (for example, holes) from the carrier injection region to the n-type base region. Since a voltage for injecting and for extracting carriers (for example, holes) is applied to the second source electrode, the on-resistance of the n-type base region is significantly reduced when this lateral semiconductor device is in the on state. Therefore, it is possible to obtain a lateral semiconductor device in which internal power loss is extremely small and latch-up does not occur. Further, in this lateral semiconductor device, internal carriers can be quickly extracted at the time of turn-off, so that high-speed switching is possible even at the time of driving a large current.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1A and 1B are configuration diagrams showing the configuration of a first embodiment of a lateral semiconductor device according to the present invention, wherein FIG. 1A is a top view and FIG. 1B is its A- line. FIG. 11 is a cross-sectional view taken along the line A ′, showing an example in which a dielectric isolation film is used in a polycrystalline silicon support substrate.

In FIG. 1, 1 is an n-type low impurity concentration base region (first semiconductor region), 2 is a p-type well region (second semiconductor region).
Semiconductor region), 3 is an n-type source region (third semiconductor region), 4 is an n-type high impurity concentration drain region (fourth semiconductor region), 5 is a p-type high impurity concentration carrier injection region (carrier injection semiconductor region) , 6 is a polycrystalline silicon support substrate, 7 is a p-type high impurity concentration embedded region (embedded semiconductor region), 8 is a dielectric isolation film (isolation insulating film), 9 is an insulating film,
Reference numeral 10 is a drain electrode, 11 is a source electrode, 12 is a gate electrode, and 13 is a carrier injection electrode.

The lateral semiconductor device of this embodiment is formed in an island shape inside the polycrystalline silicon supporting substrate 6 with the insulating separation film 8 interposed therebetween, and the exposed portion of this island portion has a substantially rectangular shape. The cross section of the portion embedded in the silicon support substrate 6 is substantially trapezoidal. The lateral semiconductor device has a relatively thick n-type base region 1 and a p-type buried region interposed between the insulating separation film 7 and the remaining surface of the n-type base region 1 except for one main surface. Area 7. On one main surface of n-type base region 1, p-type well region 2 and n-type drain region 4 are selectively formed separately from each other, and p-type carrier injection region 5 is formed on n-type base region 1.
The insulating film 9 is selectively formed so as to extend along the three peripheral portions of the above, and the insulating film 9 is also formed along the remaining one peripheral portion of the n-type base region 1. The surface of the p-type well region 2 has two n
The mold source region 3 is separated and selectively formed. The n-type drain region 4 is arranged adjacent to the insulating film 9, and the p-type carrier injection region 5 is arranged in contact with one exposed end of the p-type buried region 7. One end of the drain electrode 10 is arranged in contact with the surface of the drain region 4, and the other end of the drain electrode 10 is arranged so as to extend on the insulating film 9. Two n-type source regions 3
The central portion of the source electrode 12 is disposed in contact with the surface of the source electrode 12, and a part of the source electrode 12 is disposed so as to extend above the p-type carrier injection region 5. The gate electrode 12 is one of the n-type base regions 1.
The carrier injection electrode 13 is arranged in a portion extending from the main surface to the surface of the source region 3 through the surface of the p-type well region 2 via an insulating film (not shown).
And the exposed end of the p-type buried region 7 are arranged in contact with each other. The insulating film 9 is selected to have a film thickness that can withstand the voltage between the drain electrode 10 and the p-type buried region 7 when the lateral semiconductor device is in the off state. When a large output current is desired to be obtained, a plurality of lateral semiconductor devices shown in the figure are arranged in parallel and are connected in parallel for use. When manufacturing a horizontal semiconductor device of this parallel arrangement,
There is no need to use a complicated plane pattern, and no special manufacturing process or photomask is required.

The lateral semiconductor device of this embodiment having the above-described structure operates as follows.

A high operating voltage is applied between the drain electrode 10 and the source electrode 11 (generally, the source electrode 11 is at the ground potential), and the p-type carrier injection region 5 and the n-type base region are added to the carrier injection electrode 9. 1 and p-type buried region 7
A voltage exceeding the diffusion potential of each pn junction between the n-type base region 1 and the n-type base region 1, for example, a voltage of 0.7 to 1.0 V is applied. At this time, when a control voltage higher than that of the source electrode 11 is supplied to the gate electrode 12, an n-type channel is formed on the surface of the p-type well region 2 below the gate electrode 12,
After carriers (electrons in this case) flow from the source electrode 11 into the n-type base region 1 through the n-type channel, the carriers (electrons) reach the drain electrode 10 from the n-type drain electrode 4 and the lateral semiconductor The device conducts and turns on. The operation up to now is based on the known n-type MOSFE.
Although the operation is exactly the same as that of T, in the lateral semiconductor device of the present embodiment, carriers (holes in this case) are n from the p-type carrier injection region 5 and the p-type buried region 7.
Since the conductivity is modulated in the n-type base region 1 because it is injected into the n-type base region 1, the on-resistance of the n-type base region 1 and the n-type drain electrode 4 when the lateral semiconductor device is in the on state, that is, The drain resistance is significantly reduced.

In this case, in the lateral semiconductor device of this embodiment, the resistance generated between the main electrodes, that is, the drain electrode 10
The main resistances generated between the source electrode 11 and the source electrode 11 are the channel resistance, the pinch resistance, and the conductivity-modulated drain resistance. However, the lateral semiconductor device of this embodiment has the n-type base region 1
Carriers (holes in this case) are evenly injected into the n-type base region 1 from the p-type buried region 7 arranged so as to surround the n-type base region 1. Therefore, the n-type base region 1 has an effective conductivity over almost the entire region. The modulation is performed and the drain resistance is significantly reduced compared to the drain resistance of known MOSFETs. Further, unlike the known MICFET, the lateral semiconductor device of the present embodiment does not require the p-type high impurity concentration region formed in the deep portion, so that the pinch resistance also becomes small. Further, the lateral semiconductor device of this embodiment is
Unlike known IGBTs, since there is no voltage drop due to the pn junction in the main current path, operation at low operating voltage is also possible and internal power loss can be made extremely small.

Next, FIGS. 2A and 2B are configuration diagrams showing the configuration of a second embodiment of the lateral semiconductor device according to the present invention, wherein FIG. 2A is a top view and FIG. FIG. 11 is a transverse cross-sectional view taken along the line AA ′, showing an example in which a dielectric isolation film is used in a polycrystalline silicon support substrate.

In FIG. 2, reference numeral 7a denotes an n-type high impurity concentration buried region (buried semiconductor region).
The same components as the components shown in FIG.

The difference in structure between the second embodiment and the first embodiment is that the first embodiment is a p-type high impurity concentration buried region 7, whereas the second embodiment is an n-type. In the first embodiment, the n-type drain region 4 is separated from other regions in that it is the high impurity concentration buried region 7a, whereas in the second embodiment, the n-type drain region 4 is n-type high. In the first embodiment, the p-type carrier injection region 5 is arranged in contact with one exposed end of the p-type high impurity concentration buried region 7 in that it is arranged in contact with one exposed end of the impurity-concentration buried region 7a. On the other hand, in the second embodiment, the p-type carrier injection region 5 is arranged separately from other regions, and the configuration of some electrodes is slightly changed due to the difference in configuration. However, in addition to the above, the difference in configuration between the second embodiment and the first embodiment No.

Since the operation of the second embodiment is almost the same as the operation of the first embodiment described above, the description of the operation of the second embodiment will be omitted.

In this case, in the lateral semiconductor device of the second embodiment, carriers (holes in this case) are injected into the n-type base region 1 on one main surface of the n-type base region 1. n only in the p-type carrier injection region 5,
There is no carrier injection from the n-type high impurity concentration buried region 7a provided around the type base region 1, and the conductivity of the n-type base region 1 is not modulated to the same extent as in the first embodiment. However, when a known high breakdown voltage MOSFET, IGBT or the like is formed at the same time as this lateral semiconductor device, the n-type high impurity concentration buried region can be formed of the same as those, so that the dielectric isolation film 8 can be manufactured first. There is an advantage that it is easier than the first embodiment.

Next, FIGS. 3A and 3B are configuration diagrams showing the configuration of a third embodiment of the lateral semiconductor device according to the present invention, where FIG. 3A is a top view and FIG. FIG. 11 is a cross-sectional view taken along the line AA ′, showing an example in which a dielectric isolation film is used in a polycrystalline silicon support substrate.

In FIG. 3, 7-1 is a partially arranged p-type high impurity concentration buried region (first buried semiconductor region), and 7-2 is a partially arranged n-type high impurity concentration buried region (second buried region). 1 is a buried semiconductor region, and FIG.
The same components as the components shown in FIG.

The difference between the structures of the third embodiment and the first embodiment is that the first embodiment is provided with only the p-type high impurity concentration buried region 7, whereas the third embodiment is different. The example is provided with a partially arranged p-type high impurity concentration buried region 7-1 and a partially arranged n-type high impurity concentration buried region 7-2, and the first embodiment is an n-type drain region. 4 is separated from the other regions, the n-type drain region 4 is arranged in contact with one exposed end of the partial n-type high impurity concentration buried region 7-2 in the third embodiment. Points,
In addition, there is no difference in structure between the third embodiment and the first embodiment except that the structure of some electrodes is slightly changed due to the difference in those structures. .

Since the operation of the third embodiment is almost the same as the operation of the first embodiment, the description of the operation of the third embodiment will be omitted.

In this case, in the lateral semiconductor device of the third embodiment, the partially arranged p-type high impurity concentration buried region 7-
1 or a partially arranged n-type high impurity concentration buried region 7-
2. In addition, the manufacturing process of the dielectric isolation film 8 becomes slightly complicated, but since carriers (holes) are injected into the n-type base region 1 from the bottom of the island-shaped part, the n-type base region is also injected. No. 1 effectively modulates the conductivity, and further, it is not necessary to provide a thick insulating film 9 (see FIGS. 1 and 2) which is expensive to manufacture. Therefore, as a whole,
There is an advantage that the lateral semiconductor device can be manufactured at low cost.

Next, FIGS. 4A and 4B are configuration diagrams showing the configuration of a fourth embodiment of the lateral semiconductor device according to the present invention, wherein FIG. 4A is a top view and FIG. FIG. 11 is a transverse cross-sectional view taken along the line AA ′, showing an example in which a dielectric isolation film is used in a polycrystalline silicon support substrate.

In FIG. 4, 14 is a p-type second source region (fifth semiconductor region), 15 is a second source electrode (third main electrode), 16 is a p-type low impurity concentration region, and in addition, FIG. The same components as those shown in are designated by the same reference numerals.

The lateral semiconductor device of this embodiment is also constructed in the inside of the polycrystalline silicon supporting substrate 6 in an island shape with the insulating separation film 8 interposed therebetween, and the exposed portion of this island portion has a substantially rectangular shape. The cross-sectional shape of the portion embedded in the support substrate 6 is substantially trapezoidal. This lateral semiconductor device has an n-type base region 1 and a p-type buried region 7 interposed between the insulating separation film 7 and the remaining surface of the n-type base region 1 except for one main surface. Prepare n-type base region 1
P-type well region 2, n-type drain region 4, p-type carrier injection region 5, and p-type second source region 14 are selectively formed on one main surface of each of the p-type well regions 2.
A p-type low impurity concentration region 16 is formed between the type carrier injection region 5 and the p-type second source region 14. The p-type carrier injection region 5 has n on one main surface of the n-type base region 1.
Formed along the three peripheral edges of the mold base region 1,
Similarly, insulating film 9 is formed on one main surface of n-type base region 1 along the remaining one peripheral edge of n-type base region 1. An n-type source region 3 is selectively formed on the surface of the p-type well region 2. The n-type drain region 4 is arranged adjacent to the insulating film 9, and the p-type carrier injection region 5 is arranged in contact with one exposed end of the p-type buried region 7. One end of the drain electrode 10 is arranged in contact with the surface of the drain region 4, and the other end of the drain electrode 10 is arranged so as to extend on the insulating film 9. The source electrode 12 is formed on the surface of the n-type source region 3.
Are arranged in contact with each other, and an end portion of the source electrode 12 is extendedly arranged above the p-type carrier injection region 5. The gate electrode 12 is
n from the surface of the p-type second source region 14 through the one main surface of the n-type base region 1 and the surface of the p-type well region 2, respectively.
Insulating film (not shown) on the surface of the mold source region 3
And the p-type second source region 14
From the surface to the surface of the p-type low impurity concentration region 16 to the surface of the p-type carrier injection region 5 via an insulating film (not shown). The carrier injection electrode 13 is arranged in contact with the surface of the p-type carrier injection region 5 and the exposed end of the p-type buried region 7, respectively, and the second source electrode 15 is arranged in contact with the surface of the p-type second source region 14. In this case, p-type carrier injection region 5 and p-type low impurity concentration region 1
6, the portion composed of the p-type second source region 14 constitutes a depletion type pMOSFET.

In the above structure, the lateral semiconductor device of this embodiment operates as follows.

A high operating voltage is applied between the drain electrode 10 and the source electrode 11 (generally, the source electrode 11 is at the ground potential), and the p-type carrier injection region 5 and the n-type base region are added to the carrier injection electrode 9. 1 and p-type buried region 7
A voltage exceeding the diffusion potential of each pn junction between the n-type base region 1 and the n-type base region 1, for example, a voltage of 0.7 to 1.0 V is applied to the second source electrode 15 and the carrier injection electrode 9. Source voltage 1 lower than the supplied voltage
A voltage equal to or slightly higher than the voltage supplied to 1 is applied. At this time, if a control voltage higher than that of the source electrode 11 is supplied to the gate electrode 12, the gate electrode 12
An n-type channel is formed on the surface of the p-type well region 2 below the electrodes, and carriers (electrons in this case) are source electrodes 11
To the n-type base region 1 via the n-type channel, and then the carriers (electrons) reach the drain electrode 10 via the n-type drain electrode 4, and the lateral semiconductor device is turned on and turned on. At the same time, the gate electrode 1
By the control voltage supplied to 2, the conductivity type of the p-type low impurity concentration region 16 is inverted, the p-type channel disappears to become an n-type channel, and carriers (holes in this case) become p-type.
It is injected into the n-type base region 1 from the type carrier injection region 5 and the p-type buried region 7.

On the other hand, when the control voltage lower than that of the source electrode 11 is supplied to the gate electrode 12 while the lateral semiconductor device is in the ON state, the n-type channel formed on the surface of the p-type well region 2 disappears. Then, the lateral semiconductor device is turned off, the n-type channel formed in the p-type low impurity concentration region 16 disappears, and the injection of carriers (holes) into the n-type base region 1 is stopped. Further, when the lateral semiconductor device is turned off, carriers (holes) in the p-type carrier injection region 5 are effectively extracted from the second source electrode 15 through the p-type low impurity concentration region 16 and the p-type second source region 14. Will be

As described above, in this embodiment, when the lateral semiconductor device is in the ON state, carriers (holes) are n
When injected into the mold base region 1 and when the lateral semiconductor device is turned off, most of the carriers (holes) are extracted from the second source layer 15, so that the carriers are larger than those in the first to third embodiments. There is an advantage that the conductivity can be modulated and a high speed switching operation can be performed.

Next, FIG. 5 is a constitutional view showing the constitution of a fifth embodiment of the lateral semiconductor device according to the present invention, which is (a).
Is a top view, (b) is a cross-sectional view taken along the line AA ′,
It shows an example in which a dielectric isolation film is used in a polycrystalline silicon supporting substrate.

In FIG. 5, the same components as those shown in FIGS. 2 and 4 are designated by the same reference numerals.

The difference between the structure of the fifth embodiment and that of the fourth embodiment is that the fourth embodiment is a p-type high impurity concentration buried region 7, whereas the fifth embodiment is an n-type. In the fourth embodiment, the n-type drain region 4 is separated from other regions in that it is the high impurity concentration buried region 7a, whereas in the fifth embodiment, the n-type drain region 4 is n-type high. In the fourth embodiment, the p-type carrier injection region 5 is arranged in contact with one exposed end of the p-type high impurity concentration buried region 7 in that it is arranged in contact with one exposed end of the impurity-concentration buried region 7a. On the other hand, in the second embodiment, the p-type carrier injection region 5 is separated from one exposed end of the corresponding n-type high-impurity concentration buried region 7a, and the difference in their configurations. As a result, only some of the electrode configurations have been changed, There is no difference in configuration between the fifth embodiment and the fourth embodiment.

Since the operation of the fifth embodiment is almost the same as the operation of the fourth embodiment, the description of the operation of the fifth embodiment will be omitted.

In this case, in the lateral semiconductor device of the fifth embodiment, as in the second embodiment, the injection of carriers (holes in this case) into the n-type base region 1 is performed.
1 only in the p-type carrier injection region 5 provided on the main surface thereof, and carriers are not injected from the n-type high impurity concentration buried region 7a provided around the n-type base region 1. , N-type base region 1 cannot modulate the conductivity to the same extent as in the fourth embodiment, but when a known high breakdown voltage MOSFET, IGBT or the like is formed simultaneously with this lateral semiconductor device, Since the high-impurity-concentration buried region can be formed of the same material as those, there is an advantage that the dielectric isolation film 8 is much easier to manufacture than the fourth embodiment.

Next, FIG. 6 is a constitutional view showing the constitution of a sixth embodiment of the lateral semiconductor device according to the present invention, which is (a).
Is a top view, (b) is a cross-sectional view taken along the line AA ′,
It shows an example in which a dielectric isolation film is used in a polycrystalline silicon supporting substrate.

In FIG. 6, the same components as those shown in FIGS. 3 and 4 are designated by the same reference numerals.

The difference between the sixth embodiment and the fourth embodiment is that the fourth embodiment has only the p-type high impurity concentration buried region 7, whereas the sixth embodiment has the sixth embodiment. The example is provided with a partially arranged p-type high impurity concentration buried region 7-1 and a partially arranged n-type high impurity concentration buried region 7-2, and the fourth embodiment is an n-type. Drain region 4
Is separated from other regions, the sixth embodiment contacts one exposed end of the n-type high impurity concentration buried region 7-2 in which the n-type drain region 4 is partially arranged. The difference is that they are arranged and that the configuration of some of the electrodes is slightly changed due to the difference in their configurations. In addition, between the sixth embodiment and the fourth embodiment, There is no structural difference.

Since the operation of the sixth embodiment is almost the same as the operation of the above-mentioned fourth embodiment, the description of the operation of the sixth embodiment will be omitted.

In this case, in the lateral semiconductor device of the sixth embodiment, as in the case of the third embodiment, the partially arranged p-type high impurity concentration buried region 7-1 and the partially arranged region are arranged. Although the manufacturing process of the n-type high impurity concentration buried region 7-2 and the dielectric isolation film 8 is slightly complicated, the injection of carriers (holes) into the n-type base region 1 is at the bottom of the island-shaped portion. Since the conductivity is effectively modulated in the n-type base region 1, and it is not necessary to provide the thick insulating film 9 (see FIGS. 1 and 2) which is expensive to manufacture at the time of manufacturing, It has an advantage that a horizontal semiconductor device can be manufactured comprehensively at low cost.

In each of the above-mentioned embodiments, the lateral semiconductor device has been described by using the dielectric isolation film 8 in the polycrystalline silicon supporting substrate 6, but the lateral semiconductor device of the present invention is not limited to this. The present invention is not limited to such a configuration example, but similar buried regions 7 and 7 are formed at the bottom of the lateral semiconductor device.
a, 7-1, and 7-2 and the same carrier injection region 5 on the surface thereof may be used, and other configurations may be used. The effect is almost the same.

Further, FIG. 7 is a circuit configuration diagram showing an example of a configuration of a high-power three-phase inverter circuit using the voltage-driven lateral semiconductor device according to the present invention.

In FIG. 7, 17 is a voltage-driven lateral semiconductor device, 18 is a freewheel diode, 19 is a first drive circuit, 20 is a second drive circuit, 21 is a three-phase motor,
22 is a power supply.

This three-phase inverter circuit is provided with three branch circuits in which two voltage-driven lateral semiconductor devices 17 are connected in series, and these three branch circuits are connected in parallel to the power supply 21. A freewheel diode 18 is connected in parallel to each voltage-driven lateral semiconductor device 17. Each voltage-driven lateral semiconductor device 17 has its gate electrode connected to a first drive circuit 19 for supplying a control voltage, and its carrier injection electrode for a second drive circuit 20 for supplying a predetermined voltage as described above.
Or (in the case of using the lateral semiconductor device of the first to third embodiments), or the carrier injection electrode 13 and the second source electrode 15 respectively supply the above-mentioned predetermined voltages separately. Connected to the drive circuit 20 (when the lateral semiconductor device of the fourth to sixth embodiments is used).
The connection points of the two voltage-driven lateral semiconductor devices 17 connected in series are connected to the input terminals of the three-phase motor 21, respectively.

In the above structure, the first drive circuit 19
Since the voltage-controlled lateral semiconductor device 17 is driven by the control voltage, the circuit configuration is much simpler than in the case of driving a three-phase inverter circuit including current-driven switching elements such as transistors. Become. In addition, the carrier injection electrode 1 of the voltage-controlled lateral semiconductor device 17
3 or carrier injection electrode 13 and second source electrode 15
The second drive circuits 20 respectively connected to the first and second drive circuits 20 are not directly related to the switching operation of the voltage-controlled lateral semiconductor device 17, so that the circuit configuration is also simple. And
Since the three-phase inverter circuit of this example uses the voltage-controlled lateral semiconductor device 17 according to this example, there is an advantage that power loss can be significantly reduced as compared with a known inverter circuit.

[0060]

As described above, according to the present invention, a semiconductor region for carrier injection, which is arranged on one main surface of the first semiconductor region 1 and is separated from the second semiconductor region 2 and the fourth semiconductor region 4. 5, the carrier injection electrode 13 is placed in contact with the surface of the carrier injection semiconductor region 5, and the carrier injection electrode 13 is provided between the carrier injection semiconductor region 5 and the first semiconductor region 1 and the embedded semiconductor region 7. Since a voltage exceeding the diffusion potential of each pn junction between the first semiconductor region 1 and the first semiconductor region 1 is applied, carriers are effectively injected from the carrier injection semiconductor region 5 into the first semiconductor region 1. When the lateral semiconductor device is in the ON state, the ON resistance of the first semiconductor region 1 can be significantly reduced, the internal power loss is extremely small, and a lateral semiconductor device that does not latch up can be obtained. There is an effect that. Furthermore, since this lateral semiconductor device does not have a pn junction that causes a voltage drop inside unlike the known IGBT, it can be operated even if the collector voltage drops to around 0V. There is also an effect.

Further, according to the present invention, the first semiconductor region 1
The fifth semiconductor region 14 and the carrier injecting semiconductor region 5, which are spaced apart from the second semiconductor region 2 and the fourth semiconductor region 4 and are also spaced apart from each other, are provided on one main surface of A third main electrode 15 on the surface of the semiconductor region 14,
A carrier injection electrode 13 is arranged in contact with the surface of the carrier injection semiconductor region 5, and a control electrode 12 is provided on one main surface of the first semiconductor region 1 between the fifth semiconductor region 14 and the carrier injection semiconductor region 5. The carrier injection electrode 13 is extendedly arranged via an insulating film, a predetermined voltage is applied to the carrier injection electrode 13, and the space between the carrier injection semiconductor region 5 and the first semiconductor region 1 and between the buried semiconductor region 7 and the first semiconductor region 1 are set. In order to apply a voltage exceeding the diffusion potential of each pn junction between them to effectively inject carriers from the carrier injecting semiconductor region 5 into the n-type base region and to extract the carriers to the third main electrode 15. Since the horizontal semiconductor device is in the ON state, the ON resistance of the first semiconductor region 1 can be significantly reduced, and the internal power loss is extremely small. There is an effect that lateral semiconductor device can be obtained without the Tchiappu. Further, in this lateral semiconductor device, since internal carriers can be quickly extracted at the time of turn-off, there is an effect that high-speed switching is possible even at the time of driving a large current.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a first embodiment of a lateral semiconductor device according to the present invention.

FIG. 2 is a configuration diagram showing a configuration of a second embodiment of a lateral semiconductor device according to the present invention.

FIG. 3 is a configuration diagram showing a configuration of a third embodiment of a lateral semiconductor device according to the present invention.

FIG. 4 is a configuration diagram showing a configuration of a fourth embodiment of a lateral semiconductor device according to the present invention.

FIG. 5 is a configuration diagram showing a configuration of a fifth embodiment of a lateral semiconductor device according to the present invention.

FIG. 6 is a configuration diagram showing a configuration of a sixth embodiment of a lateral semiconductor device according to the present invention.

FIG. 7 is a circuit configuration diagram showing an example of a configuration of a high-power three-phase inverter circuit using the lateral semiconductor device according to the present invention.

FIG. 8 is a cross-sectional configuration diagram showing an example of a known MOSFET and a known IGBT.

FIG. 9 is a cross-sectional configuration diagram showing an example of a known MICFET.

[Explanation of symbols]

1 n-type low impurity concentration base region (first semiconductor region) 2 p-type well region (second semiconductor region) 3 n-type source region (third semiconductor region) 4 n-type high impurity concentration drain region (fourth semiconductor region) 5 p-type high impurity concentration carrier injection region (carrier injection semiconductor region) 6 polycrystalline silicon support substrate 7 p-type high impurity concentration buried region (buried semiconductor region) 7a n-type high impurity concentration buried region (buried semiconductor region) 7- 1 Partially arranged p-type high impurity concentration buried region (first buried semiconductor region) 7-2 Partially arranged n-type high impurity concentration buried region (second buried semiconductor region) 8 Dielectric Body separation film (separation insulating film) 9 Insulating film 10 Drain electrode 11 Source electrode 12 Gate electrode 13 Carrier injection electrode 14 P-type second source region (fifth semiconductor region) 15 Second Over the source electrode (third main electrode) 16 p-type low impurity concentration region 17 voltage driving lateral semiconductor device 18 freewheeling diode 19 first driving circuit 20 and the second driving circuit 21 3-phase motor 22 power supply

Claims (8)

[Claims] 1. A first conductive type first semiconductor region arranged in a substrate, a second conductive type second semiconductor region selectively arranged on one main surface of the first semiconductor region, and the second semiconductor region. A third semiconductor region of the first conductivity type selectively arranged on the surface of the semiconductor region, and a fourth semiconductor of the first conductivity type separated from the second semiconductor region on one main surface of the first semiconductor region. Region, a semiconductor buried region arranged between the first semiconductor region and the substrate, an insulating film over one main surface of the first semiconductor region and each surface of the second semiconductor region and the third semiconductor region. A control electrode disposed via the first main electrode disposed in contact with each surface of the second semiconductor region and the third semiconductor region, and a second main electrode disposed in contact with the surface of the fourth semiconductor region. A lateral semiconductor device including an electrode, wherein the first semiconductor A second conductivity type semiconductor region for carrier injection, which is spaced apart from the second and fourth semiconductor regions, is provided on one main surface of the region, and a carrier injection electrode is arranged in contact with the surface of the semiconductor region for carrier injection. A lateral semiconductor device characterized by the above. 2. The lateral type according to claim 1, wherein the semiconductor buried region is of a second conductivity type, and an end portion of the buried semiconductor region and the carrier injection semiconductor region are arranged in contact with each other. Semiconductor device. 3. The embedded semiconductor region is of a first conductivity type and has an end portion of the embedded semiconductor region and the fourth embedded semiconductor region.
The semiconductor region is arranged in contact with the semiconductor region.
The lateral semiconductor device described. 4. The buried semiconductor region includes a first buried semiconductor region of a first conductivity type and a second buried semiconductor region of a second conductivity type, and an end portion of the first buried semiconductor region and the fourth semiconductor region. And the second contact
The lateral semiconductor device according to claim 1, wherein an end of the buried semiconductor region and the carrier injection semiconductor region are arranged in contact with each other. 5. A first conductivity type first semiconductor region arranged in a substrate, a second conductivity type second semiconductor region selectively arranged on one main surface of the first semiconductor region, and the second region. A third semiconductor region of the first conductivity type selectively arranged on the surface of the semiconductor region, and a fourth semiconductor of the first conductivity type separated from the second semiconductor region on one main surface of the first semiconductor region. Region, an embedded semiconductor region arranged between the first semiconductor region and the substrate, an insulating film over one main surface of the first semiconductor region and each surface of the second semiconductor region and the third semiconductor region A control electrode disposed via the first main electrode disposed in contact with each surface of the second semiconductor region and the third semiconductor region, and a second main electrode disposed in contact with the surface of the fourth semiconductor region. A lateral semiconductor device including an electrode, wherein the first semiconductor A second conductive type fifth semiconductor region and a carrier injecting semiconductor region which are spaced apart from the second and fourth semiconductor regions and are also spaced apart from each other on one main surface of the region; A third main electrode is arranged in contact with the surface of the fifth semiconductor region, and a carrier injection electrode is arranged in contact with the surface of the carrier injection semiconductor region, and the control electrode is arranged between the fifth semiconductor region and the carrier injection semiconductor region. A lateral semiconductor device, which is extendedly arranged on one main surface of the first semiconductor region via an insulating film. 6. The lateral type according to claim 5, wherein the buried semiconductor region is of a second conductivity type, and an end portion of the buried semiconductor region and the carrier injection semiconductor region are arranged in contact with each other. Semiconductor device. 7. The buried semiconductor region is of a first conductivity type and has an end portion of the buried semiconductor region and the fourth conductive type.
6. The semiconductor region is arranged in contact with the semiconductor region.
The lateral semiconductor device described. 8. The buried semiconductor region is composed of a first buried semiconductor region of a first conductivity type and a second buried semiconductor region of a second conductivity type, and an end portion of the first buried semiconductor region. 6. The lateral semiconductor device according to claim 5, wherein the fourth semiconductor region is placed in contact with the end of the second embedded semiconductor region and the carrier injection semiconductor region is placed in contact with each other.