JPH07281995A - Data transfer system - Google Patents

Abstract

PURPOSE:To improve the throughput of a bus by accelerating system bus access. CONSTITUTION:This system is composed of a CPU bus 101 connected to a CPU 1, plural system buses 1-102 and 2-103, system bus control part 2 for controlling the system buses, and data buffers 3 and 4 corresponding to the respective system buses. Thus, the system bus access is accelerated and the throughput of the bus is improved.

Description

Detailed Description of the Invention

[0001]

[Industrial application] Computer equipment

[0002]

2. Description of the Related Art Conventionally, as shown in Japanese Patent Laid-Open No. 57-60436, the throughput of the bus has been improved by using a buffer for one system bus.

[0003]

The system bus is very slow compared to the processing power of the CPU. Therefore, during the access to the system bus, the CPU and the CPU bus have many waiting states, which is very wasteful.

The problem to be solved by the present invention is to eliminate this waste and improve the throughput of the bus.

[0005]

[Means for Solving the Problems] A system bus is multi-wired and a data buffer for each system bus is provided.
At the time of writing data, the CPU bus is released when the writing to the data buffer is completed.

[0006]

According to the present invention, the throughput of the bus can be improved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a circuit diagram when the CPU bus is 32 bits and the system bus is 16 bits. The system bus 1 (1
02), and the lower part of the data bus is the system bus 2
Allocate to (103). For example, system bus 1 (10
The device connected to 2) is the system device 1
(5) When the devices connected to the system bus 2 (103) are named system devices 2 (6), the mapping of these devices is as shown in FIG.

From CPU (1) to system device 1
When writing to (5), system bus controller (2)
When the data is latched in the data buffer (3), the system bus control unit (2) notifies the CPU (1) of the end of the cycle. While the data buffer 1 (3) is writing data to the system device 1 (5), the CPU bus (1
01) and the system bus 2 (103) are empty,
CPU (1) writes / writes to system device 2 (6)
Read is possible.

Also, a 32-bit system device 3
(7) is system bus 1 (102) and system bus 2
(103) and the two system buses are controlled in common at this time.

[0011]

According to the present invention, the bus throughput due to the system bus access is improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration example of the present invention.

FIG. 2 is an address mapping diagram.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... System bus control part, 3 ... Data buffer 1, 4 ... Data buffer 2, 5 ... System device 1, 6 ... System device 2, 7 ... System device 3, 11 ... Memory map, 101 ... CPU bus , 102 ... System bus 1, 103 ... System bus 2.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Kazuhiro Kojima 3-10-22 Sakae, Naka-ku, Nagoya-shi, Aichi Prefecture Nihon Chubu Software Co., Ltd. (72) Inventor Mihoko Kudo 10-10 Sakae, Naka-ku, Nagoya-shi, Aichi No. 22 Hirata Chubu Software Co., Ltd. (72) Inventor Yasuo Hirata No. 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Stock Company Hitachi Office Systems Division (72) Inventor Seiji Hayashi No. 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Stock company Hitachi Asahi Electronics

Claims (1)

[Claims] 1. A computer system having three CPU buses.
If the system device is 2 bits and there are two types of 32 bits and 16 bits, set the system bus to 1
By dividing the bus into two 6-bit buses and providing a buffer for each bus, 16-bit devices addressed to connect to one system bus and addressed to connect to the other system bus When writing to a 16-bit device,
It controls so that it operates independently on the two divided system buses, and the 32-bit system bus has two 1's.
A method that enables connection across a 6-bit system bus.