JPH07281954A - Fast pc system - Google Patents

Abstract

PURPOSE:To ensure the fast operation of an OS program in a PC system. CONSTITUTION:A kernel memory 1 is placed at a position closer to an MPU than a cache memory 7 and a main memory 11, and an OS program is loaded into the memory 1. Thus the access overhead caused to a hard disk and the memory 11 by the cache mistakes and a virtual memory mechanism can be eliminated. Then the OS program can be carried out at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of constructing and using an MPU and a memory in a PC system, and more particularly to memory access from an OS. It also relates to the cache controller LSI.

[0002]

2. Description of the Related Art Conventionally, as a method of configuring a memory of a PC system, a method for accessing a memory at high speed from an MPU has been
A configuration using a secondary cache memory is introduced.

For example, "Pr" issued by Intel (R)
"Object Guide" (ISBN 1-55512
-08-1) 2-16pp to 2-20pp has MP
An example of a PC system using U and a cache controller is described. This is called conventional technique 1.

An example of a PC system using virtual memory in the OS of the PC system is "INSIDE WINDOWS NT" (author He
len Custer, ISBN4-7561-027
7-8) 198 pp to 216 pp, and particularly deals with virtual memory. This is called Conventional Technique 2.

[0005]

In the conventional technique 1, when the program of the address desired by the OS does not exist in the cache memory controlled by the cache controller, a cache miss occurs and a program is newly added from the main memory. Had to be loaded into the cache memory, which caused overhead.

In the conventional technique 2, the virtual memory mechanism is the OS.
Is provided by. Here, part of the OS program may also be paged and moved (paged out) from the main memory to the hard disk. Therefore, when the virtual memory mechanism operates during program operation inside the OS. Since the OS internal program must be returned from the hard disk to the main memory, the operating speed of the OS may be reduced due to the processing. Further, in the conventional technique 2, it is stated that a part of the main memory is exclusively allocated to the OS, but in this case as well, the overhead due to the secondary cache may occur.

An object of the present invention is to provide a PC system,
It is to provide a method for minimizing the overhead of memory access during program operation inside the OS.

Another object of the present invention is to provide a method for configuring a memory of a PC system that achieves both a virtual memory mechanism and high speed.

Another object of the present invention is to provide a method for constructing an LSI that minimizes the overhead of memory access from the MPU.

[0010]

In order to achieve the above object, in the present invention, a memory having an access speed equal to or higher than that of a cache memory is named a kernel memory as a memory located closest to the MPU. , Address selector, and kernel address setting means.

In order to achieve the above-mentioned other objects, the memory space of the PC system is configured by using a kernel memory having a larger capacity than the MPU and the cache memory.

In order to achieve the above-mentioned other objects, the program is configured so that the OS main body of the PC system is loaded into the kernel memory.

In order to achieve the above-mentioned other objects, an address selector, a kernel address setting means, and a secondary cache controller are built in an LSI, and the LSI is configured.

[0014]

When the OS is started, the program is configured to load the OS main body into the kernel memory, and when the OS program is executed, the kernel address setting means determines that the program is in the kernel memory. Switch addresses to kernel memory instead of cache memory. As a result, the MPU can directly access the kernel memory, and since there is no cache miss, the MPU can always operate faster and with a minimum overhead than when accessing the secondary cache memory.

Further, by loading the OS main body into the kernel memory instead of loading it into the main memory, the overhead due to the paging operation by the secondary cache memory and main memory and the virtual memory mechanism is released, and the OS operates at high speed. It becomes possible.

By incorporating the address selector and the kernel address setting means in the secondary cache controller LSI, a high speed memory system with a kernel memory can be easily constructed by the secondary cache controller LSI, and a high speed PC system is provided. It becomes possible.

[0017]

Embodiments of the present invention will be described below with reference to the drawings from FIG.

In FIG. 1, 1 is a kernel memory, 2 is an address selector, 3 is an address comparing means, 4 is a kernel address setting means, 5 is an MPU, 6 is a cache controller, 7 is a cache memory, 8 is an address bus,
Reference numeral 9 is a data bus, 10 is an MPU bus, and 11 is a main memory. Further, FIG. 1 shows a PC system as a whole.

When the MPU 5 reads the data in the main memory 11, the address bus 8 reads the data stored in the cache memory 7 through the address selector 2 and the cache controller 6. Cache memory 7
When the data of the address to be read does not exist inside, the data is read from the main memory 11 to the cache memory 7. As a result, the MPU 5 can access the main memory 11 by accessing the cache memory 7. Here, when the MPU 5 reads the data of the kernel memory 1, the address bus 8 is switched to the kernel memory 1 side by the kernel address setting means 4 and the address comparison means 3, so that the MPU 5 directly connects to the kernel memory 1 Can be accessed.

Here, normally, the cache memory 7 having an access speed faster than that of the main memory 11 is used.
From the viewpoint of 5, the access speed is faster in the order of the kernel memory 1, the cache memory 7, and the main memory 11,
The minimum overhead is realized in the execution of the program placed in the kernel memory 1.

In FIG. 2, 201, 202 and 203 are flow charts for explaining the operation of the PC system shown in FIG. 1 when the power is turned on.

When the power is turned on, the PC system first reads the IPL program from the hard disk (not shown) (201). Next, the IPL program reads the OS program on the hard disk into the kernel memory 1 (2
02). Next, page protection of kernel memory 1 is performed (2
03), the contents of the kernel memory 1 are removed from the influence of the virtual memory mechanism unlike the main memory 11 of FIG. As a result, the OS program read in the kernel memory 1 can operate without the overhead of paging processing such as hard disk access by the virtual memory mechanism.

FIG. 3 is a diagram showing the address space of the MPU 5, to which the kernel memory 1 and the main memory 11 explained in FIG. 1 are allocated.

Since the kernel memory 1 is assigned to the higher order of the address and is directly connected to the address bus as seen from the MPU 5 as described above, there is no overhead in memory access. Further, the main memory 11 has an overhead due to the cache operation and the paging process by the virtual memory mechanism.

FIG. 4 shows the operation of the hard disk and kernel memory 1 not shown in FIG. 1 when the OS program is loaded.

Reference numeral 12 is a hard disk, and 14 is an OS.

By placing the OS 14 on the hard disk 12, the OS 14 is loaded into the kernel memory 1 as described with reference to FIGS. 2 and 3, and the OS program can be executed at high speed.

FIG. 5 shows another embodiment of the PC system shown in FIG. 1, and 13 is a kernel memory compatible cache controller LSI 13. Since the other components are the same as those in FIG. 1, the description thereof will be omitted.

An address selector 2, an address comparing means 3, a kernel address setting means 4, and a cache controller 6 are built in the kernel memory compatible cache controller LSI 13. As a result, MPU5
Similarly, the fastest memory access with the kernel memory 1 is possible. Further, in the present embodiment, the kernel memory 1 and the cache memory 7 can be controlled only by the kernel memory compatible cache controller LSI 13, and a high-speed PC system can be easily configured.

[0030]

As described above, according to the present invention,
A program is configured to load the OS body into the kernel memory when the OS is started, and when the OS program is executed,
The kernel address setting means determines that the program is in the kernel memory, and the address selector switches the address from the MPU to the kernel memory instead of the cache memory. As a result, the MPU can directly access the kernel memory and there is no cache miss, so the MPU is always faster than the access to the secondary cache memory with the minimum overhead.
Is operational.

Further, by loading the OS main body into the kernel memory instead of loading it into the main memory, the overhead due to the paging operation by the secondary cache memory or main memory and the virtual memory mechanism is released, and
The S program can be operated at high speed.

Further, by incorporating the address selector, the kernel address setting means and the cache controller in one LSI, a high speed memory system with a kernel memory can be easily constructed and a high speed PC system can be provided. .

[Brief description of drawings]

FIG. 1 is a high-speed PC using a kernel memory according to the present invention.
It is a block diagram which shows one Example of a system.

FIG. 2 is a flowchart showing loading of an OS into the kernel memory 1 shown in FIG.

3 is a diagram showing allocation of a kernel memory 1 and a main memory 11 in the address space of the MPU 5 shown in FIG.

FIG. 4 is a diagram showing an example of loading an OS 14 into the kernel memory 1 in the address space shown in FIG.

5 is a diagram showing another embodiment using a cache controller LSI compatible with a kernel memory in the PC system shown in FIG.

[Explanation of symbols]

1 ... Kernel memory, 2 ... Address selector, 3 ... Address comparing means, 4 ... Kernel address setting means, 5 ... M
PU, 6 ... Cache controller, 7 ... Cache memory, 8 ... Address bus, 9 ... Data bus, 10 ... MP
U bus, 11 ... Main memory, 12 ... Hard disk,
13 ... Cache controller LS for kernel memory
I, 14 ... OS.

Claims (3)

[Claims] 1. A PC equipped with an MPU, a cache controller, a cache memory, and a main memory is newly provided with a kernel memory, an address selector, and a kernel address setting means, and the OS is loaded into the kernel memory at the time of system startup, and the OS internal A high-speed PC system characterized in that only the kernel memory and the MPU are operated when the program is operated, enabling high-speed execution. 2. A cache controller, a secondary cache memory, and a main memory, which are closer to the MPU than the three parts, and M
A PC system characterized in that a kernel memory is provided at a position closest to a PU and a program execution state that operates only between the MPU and the kernel memory is realized. 3. A cache controller LSI characterized in that the address selector and kernel address setting means according to claim 1 are built in a cache controller, and a configuration using a kernel memory and a secondary cache memory can be easily realized. .