JPH07281923A - Electronic circuit using programmable logic circuit - Google Patents

Abstract

PURPOSE:To provide an electronic circuit which uses a PLD circuit that can easily change the electronic circuit without soldering a jumper wire when the electronic circuit is debugged. CONSTITUTION:A jumper pin 13 having plural pairs of pins is placed between a PLD 11 and a PLD 12, and the wiring patterns connect the output terminals of both PLD 11 and 12 to the pairs of pins of the pin 13. Then the pins of the pin 13 are used as test pins when an electronic circuit is debugged, and at the same time a jumper socket 32 is put into those paires of pins for connection between the PLD 11 and 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to connection between PLDs or PLs when designing communication equipment and electronic equipment using a plurality of programmable logics (hereinafter referred to as PLDs).
The present invention relates to an electronic circuit capable of performing a test of a single unit.

[0002]

2. Description of the Related Art PLDs currently have 300 to 5000 gates, and a desired circuit is composed of a plurality of logic circuits by a program. Pin structure (DIP, PG
From A), multi-pin with a pitch of 0.5 mm (250 pins) Q
There is even FP. When the logic circuit becomes a large-scale circuit that cannot be realized by one PLD, the circuit is divided and each divided circuit is designed by a plurality of PLDs, and each P
A method of designing a logic circuit by connecting between LDs is used. In this case, when designing using a plurality of PLDs, it is necessary to connect the terminals of each PLD or to provide a test pin to each PLD when debugging the circuit.

4 to 6 show an electronic circuit using a plurality of conventional PLD circuits. FIG. 4 shows the configuration of a general electronic circuit. Reference numerals 41 and 42 are PLDs, which are mounted on a printed circuit board (not shown). 43 and 44 are test pins, which are used for PLD 41 and P when debugging the circuit.
This is a test pin for testing the LD42, and also a PLD
41 is a jumper pin for connecting the PLD 42. 5 and 6 show an example of an electronic circuit using a plurality of PLDs, and the operation thereof will be described below.

The PLD 51, which outputs a clock signal as a test signal, extracts the clock signal to a measuring instrument such as an oscilloscope provided outside the printed circuit board by the test pin 54 to debug the circuit. Further, the PLD 52 that outputs the 3AND gate signal as a test signal extracts the 3AND gate signal to a measuring instrument such as an oscilloscope provided outside the printed board by the test pin 53 to debug the circuit.

During circuit debugging, P shown in FIG.
A design change occurs in the LD52, and the circuit of the PLD52 is shown in FIG.
The case where the PLD 61 shown in FIG. That is, the PLD 61 needs to input the output signal of the PLD 51 that outputs the clock signal as a test signal. Therefore, the jumper wire 62 is connected to the test pin 53 and the test pin 54 by soldering or the like, and the clock signal from the PLD 51 is input to the PLD 61.

As described above, even in the conventional electronic circuit using a plurality of PLD circuits, by providing the test pins on the printed circuit board in advance, the test pins of the PLDs are debugged by the circuit and the circuit is changed. Can be connected.

[0007]

However, in the electronic circuit using the above-mentioned conventional PLD circuit, when the circuit changes and the test pins are connected to each other when the circuit is debugged, the jumper wire 62 is soldered or the like. Was connected by. For this reason, particularly when the PLD circuit is composed of a multi-pin (250-pin) QFP with a pitch of 0.5 mm, the work of connecting the jumper wire 62 is very difficult, the connection state becomes unstable, and the board quality is poor. There was a problem of deterioration.

The present invention solves the above-mentioned problems of the prior art. Even when the circuit is changed during debugging of the circuit, it is not necessary to solder the jumper wire, and thus the board completeness and the board quality can be improved. Excellent PL that can be improved
An electronic circuit using a D circuit is provided.

[0009]

In order to achieve the above object, the present invention provides a plurality of PLD circuits, a jumper pin having a plurality of sets of pins arranged between these PLD circuits, and an output of the PLD circuit. A wiring pattern for connecting the terminals and the plurality of sets of pins to each other, and a jumper socket for short-circuiting the plurality of sets of pins, respectively.

[0010]

Therefore, according to the present invention, a plurality of sets of pins provided on the jumper pins are used as test pins when the circuit is debugged, and a jumper socket is inserted into the plurality of sets of pins to connect the output terminals of the PLD circuit. It is possible to easily deal with the change of the circuit at the time of debugging the circuit, and to improve the degree of completion of the board and the quality of the board.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
Will be explained together. FIG. 1 shows the configuration of the present embodiment, and FIGS. 2 and 3 are diagrams showing the operating state in the present embodiment. In FIG. 1, 11 and 12 are PLDs,
It is mounted on a printed circuit board (not shown). Reference numeral 13 is a jumper pin provided with a plurality of sets for testing or jumper connection, and is mounted on the printed board. Reference numerals 14 and 15 denote patterns provided on the printed circuit board, which connect the PLDs 11 and PLD 12 to the pin unit 13, respectively.

Next, the operation of the above embodiment will be described with reference to FIGS. In FIG. 2, the PLD 21 outputs a clock signal as a test signal,
This clock signal is output to the test pin 23 provided on the jumper pin 13. The PLD 22 outputs a 3AND gate signal as a test signal, and the 3AND gate signal is output to a test pin 24 provided on the jumper pin 13. PLD21 and PLD
When debugging the circuit of 22, the pin 23 is used to connect to a measuring instrument such as an oscilloscope provided outside the printed circuit board.
The circuit is debugged by extracting the clock signal from the LD 21. Further, the PLD 22 which outputs the 3AND gate signal as a test signal extracts the 3AND gate signal to a measuring instrument such as an oscilloscope provided outside the printed circuit board by the pin 24 to debug the circuit.

During circuit debugging, P shown in FIG.
A design change occurs in the LD22, and the circuit of the PLD22 is shown in FIG.
The case where the PLD 31 shown in FIG. That is, the PLD 31 in FIG. 3 is obtained by changing the circuit of the PLD 22, and it is necessary to input the clock signal of the PLD 21 as a test signal.
By inserting the jumper socket 32 into the pins 23 and 24, the pins 23 and 24 are short-circuited, and the PL
The output terminals of D21 and PLD31 are connected, and PLD21
The clock signal of is input to PLD 31.

Thus, according to the above embodiment, the PLD
In the design of the printed circuit board using 11 and 12,
PLDs 11 and 1 are provided with jumper pins 13 provided with a plurality of sets for testing or jumper connection
By placing the jumper socket 32 between the pins 23 and 24 without connecting the jumper wire by soldering or the like even if a design change occurs during circuit debugging, , The pin 23 and the pin 24 can be short-circuited to easily connect between the PLDs 11 and 12.

The jumper socket 32 can be easily removed from the pins 23 and 24, and the circuit can be easily changed even when the PLDs are disconnected from each other due to a design change.

[0016]

According to the present invention, as is apparent from the above-described embodiment, by providing a jumper pin having a plurality of pins for testing or jumper connection between a plurality of PLDs on a printed circuit board. Even if a design change occurs during circuit debugging, you can easily connect between PLDs by jumper sockets without connecting jumper wires by soldering, etc., so you can easily respond to circuit changes. Further, it has an effect that the substrate perfection and the substrate quality can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an electronic circuit using a PLD circuit according to an embodiment of the present invention.

FIG. 2 is a view showing an operation state in the same embodiment.

FIG. 3 is a diagram showing an operating state in the embodiment.

FIG. 4 is a block diagram of an electronic circuit using a conventional PLD circuit.

FIG. 5 is a diagram showing an operating state in the conventional example.

FIG. 6 is a diagram showing an operating state in the conventional example.

[Explanation of symbols]

 11 programmable logic (PLD) circuit 12 programmable logic (PLD) circuit 13 jumper pin 14 pattern 15 pattern 32 jumper socket

Claims (1)

[Claims] 1. A plurality of programmable logic circuits,
Jumper pins having a plurality of sets of pins arranged between these programmable logic circuits, a wiring pattern for connecting the output terminals of the programmable logic circuit and the plurality of sets of pins to each other, and jumpers for short-circuiting the plurality of sets of pins, respectively. A plurality of sets of pins are used as test pins during circuit debugging, and the jumper socket is inserted into the plurality of sets of pins to connect between output terminals of the programmable logic circuit. An electronic circuit using a programmable logic circuit.