JPH0727694B2 - Clock reproduction phase synchronization circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproduction phase synchronization circuit for reproducing a clock signal suitable for use in a rotary head type digital audio tape recorder (hereinafter referred to as R-DAT).

2. Description of the Related Art Various modulation methods in the base band have been developed for more efficient recording and reproduction of digital data. R-DA
In T, a modulation method called 8-10 conversion is used. 8
The run length of the −10 converted signal has a minimum inversion period of T
There are four types, 1T, 2T, 3T and 4T. In such a signal, a clock signal and a data signal are mixed, and it is necessary to reproduce the clock signal in order to extract the data signal. As a method of reproducing the clock signal, it is general to use a phase locked loop circuit, for example, as shown in FIG. In the figure, reference numeral 1 denotes an input terminal to which an input signal, for example, an 8-10 modulated signal is supplied, and the 8-10 modulated signal from the input terminal 1 is input to the delay circuit 201. The delay circuit 201 delays the input signal by a certain time and outputs the delayed signal. Here, the delay circuit 201 delays by half the minimum inversion synchronization T of the input signal, that is, T / 2. 202 is an exclusive OR circuit (hereinafter referred to as an EXOR circuit), which has input terminals 1 to 8
The -1 modulated signal is supplied to the input terminal of the EXOR circuit 202, whether it is through the delay circuit 201 or directly. Therefore, the output of the EXOR circuit 202 is a pulse having a constant time width which rises at the edge of the 8-10 modulation signal and falls after a constant period (T / 2). An EXOR circuit 3 operates as a phase comparison circuit. The output of the EXOR circuit 202 is supplied to one input terminal of the EXOR circuit 3, and its output is supplied to a low pass filter (hereinafter, referred to as LPF) 5. The output of LPF5 is supplied to the control input terminal of the voltage controlled oscillator 6 (hereinafter referred to as VCO) to control the oscillation frequency of VCO6. The output of VCO6 is output from the output terminal 7. At the same time, the output of VCO6 is EX
It is supplied to the other input terminal of the OR circuit 3. In this way, the phase synchronization circuit is constructed.

Now, when a signal Sa as shown in FIG. 6A is supplied to the input terminal 1, the output of the delay circuit 201 is delayed by T / 2 and is shown in FIG. 6B.
A signal Sb such as is obtained. These signals Sa and signals
Sb is supplied to the EXOR circuit 202, and the signal Sc as shown in FIG. 6C is taken out from the output terminal thereof. This signal Sc is activated by the transition point (edge) of the signal at input terminal 1 and T /
This is a signal with a pulse width of 2. The signal Sc is supplied to one input terminal of the EXOR circuit 3. Here, it is assumed that the synchronization is stable, and a signal Sd having a duty ratio of 50% as shown in FIG. 6D is obtained at the output of VCO6. This is a case where the input signal of the input terminal 1 advances exactly 90 degrees with respect to the output signal Sd of the VCO 6. This signal Sd is supplied to the other input terminal of the EXOR circuit 3, and the signal Se as shown in FIG. 6E is taken out from the output terminal of the EXOR circuit 3. This signal Se is supplied to the input terminal of the LPF5, the high frequency component is removed, and the signal Se is output from the output terminal of the LPF5. This signal is supplied to the frequency control input terminal of VCO6 and controls the oscillation frequency of VCO6. A part of the output of VCO6 is taken out from the output terminal 7, but at the same time, it is supplied to one input terminal of the EXOR circuit 3 which is a phase comparison circuit to form a phase locked loop.

Next, let us consider a state where the input signal Sa of the input terminal 1 and the output signal Sd of the VCO 6 are out of phase with each other and changed. For example, the input signal is shifted, and as a result, the output signal of the EXOR circuit 202 is shown in FIG.
Suppose that the signal has changed to Sc1. This is the case where the input signal Sa of the input terminal 1 leads the output signal Sd of the VCO 6 by 90 degrees or more. Then, the EXOR circuit 3 outputs the signal Se1 as shown in FIG. 6G. The duty ratio of the signal Se1 changes in the vicinity of the transition point of the input signal, and when focusing on the DC component, the DC level is higher than before.
The output signal obtained through LPF5 also has a high DC level and is supplied to the frequency control input terminal of VCO6. If the control voltage-oscillation frequency characteristic of the VCO 6 is positive, the oscillation frequency acts to advance the phase of the oscillation output signal Sd while trying to become higher. As a result, the phase difference between the input signal Sa of the input terminal 1 and the output signal Sd of the VCO 6 becomes relatively small due to the advance of the phase of the oscillation output signal Sd, and the balance returns to the previous state.

Next, for example, the input signal shifts in the opposite direction, resulting in the EXOR circuit 20
It is assumed that the output signal of 2 changes to the signal Sc2 as shown in FIG. 6H. This is the case where the input signal Sa of the input terminal 1 leads the output signal Sd of the VCO 6 by 90 degrees or less. Then, the EXOR circuit 3 outputs the signal Se2 as shown in FIG. This signal Se2
Focusing on the DC component of, the DC level is lower than before. Similarly, the output signal obtained through the LPF5 also has a low DC level, and acts to delay the phase of the oscillation output signal Sd in an attempt to lower the oscillation frequency.
In this way, the phase difference between the input signal Sa of the input terminal 1 and the output signal Sd of the VCO 6 becomes relatively small and returns to the previous state and balances.

In this way, the input signal Sa of input terminal 1 and the output signal of VCO6
Whichever the phase of Sd is deviated, the phase locked loop control based on the phase error information works, and the output signal Sd of the VCO 6 always acts to keep a constant phase difference with respect to the input signal Sa of the input terminal 1. The clock signal is reproduced in this way.

Problems to be Solved by the Invention In the R-DAT, the signal recorded on the tape is picked up by the rotary head at the time of reproduction, the head signal is amplified and waveform equalized, and the binary signal is supplied to the phase comparator before being supplied to the phase synchronization circuit. To do. If it complies with the R-DAT standard,
Two heads are placed facing each other in a cylinder with a diameter of 30 mm, the tape winding angle to the cylinder is 90 degrees, and every minute
It can be designed to rotate at 2000 rpm. In this case, there are two states in which the head and the tape are in contact with each other and the state in which they are not in contact with each other as the cylinder rotates, and they alternately appear every 7.5 mS during reproduction. Therefore, the head signal becomes an intermittent signal of 7.5 mS.

Further, the R-DAT can read a part of the data signal on the tape at the time of fast-forwarding or rewinding by utilizing the fact that the track on the tape is licked recording. In this case, in consideration of easiness of signal processing, it is desirable that the bit rate of the read signal is constant, and it is preferable if the bit rate can be the same as that at the time of reproduction. For that purpose, the cylinder rotation speed may be adjusted according to the tape running speed, but since the running speed is not constant due to the tape running load variation, some error always occurs. In particular, such a deviation of the bit speed is remarkable when the tape is being accelerated or decelerated.

As described above, the signal supplied to the phase locked loop circuit is an intermittent signal and has a bit rate fluctuation. In addition, the signal S / N ratio is not always good due to defects on the tape and performance deterioration due to dirt or wear on the head. Therefore, the phase synchronization circuit must have a wide coverage for bit rate fluctuations, a short synchronization pull-in time, and can reproduce an input signal.

On the other hand, in the conventional phase locked loop, the phase error information is output only during the 1T time of the input signal edge in the entire time, and at other times, it is determined by the duty ratio of the VCO6 output signal. A constant voltage source is output. Therefore, the time density of the phase error information becomes small and the loop gain of the phase locked loop is low, and the time density of the phase error information changes depending on the input signal and becomes unstable, and the jitter of the recovered clock signal becomes large. there were. In the section where the head and tape do not contact each other, a constant voltage source that determines the duty ratio of the VCO6 output signal is output throughout, but this voltage and the phase corresponding to the bit rate of the input signal intermittently supplied. If there is a gap in the error information, the free-run frequency and the input bit frequency are out of alignment, and if this difference is large, there is a problem that synchronization pull-in cannot be performed.

Means for Solving the Problems The clock recovery phase locked loop circuit of the present invention is a circuit which is activated by an edge of an input signal to generate a pulse of T / 2 (T is a minimum inversion period), and a frequency is controlled by a control signal. VC
Equipped with an O circuit, a phase comparison circuit, a low-pass filter that acts as a loop filter, and an analog gate circuit that supplies the output signal of the phase comparison circuit to the low-pass filter for the time of T / 2 pulse activated by the edge of the input signal. It is configured by.

The low-pass filter of the clock recovery phase locked loop circuit of the present invention comprises a passive filter and an impedance buffer.

Effect The present invention has the above-described configuration, and the phase error information is supplied to the LPF by the analog gate circuit only during the time when the phase error information is present, and the output of the phase locked loop is set to high impedance at other times, so that the LPF circuit in the subsequent stage is operated. Together with this, a sample hold circuit is formed and operates so as to interpolate the section having no phase error information with the immediately preceding information. As a result, the loop gain is increased, and at the same time, the phase error signal is smoothed. Further, since it is possible to similarly interpolate in the section where the head and the tape are not in contact with each other and the data is lost, the sync pull-in time is shortened and the sync pull-in range of the input bit frequency is expanded.

Embodiment An embodiment of the clock recovery phase locked loop circuit of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the basic concept of the clock recovery phase locked loop circuit of the present invention. In FIG. 1, the same parts as those in FIG. 5 are designated by the same reference numerals for simplicity. This will be described below with reference to FIG. In the figure, the difference from FIG. 5 is that four analog gate circuits are additionally inserted. The analog gate circuit is inserted between the output terminal of the phase comparison circuit 3 and the LPF 5, and the output of the T / 2 pulse generation circuit controls the analog gate circuit. FIG. 2 is a circuit diagram showing a more specific embodiment of the present invention. In FIG. 2, the same parts as those in FIGS. 1 and 5 are designated by the same reference numerals for simplicity. In FIG. 2, the LPF 5 forms a lag lead type passive filter including a resistor 501, a capacitor 502, a resistor 503, and a capacitor 504. An operational amplifier 508 operates as a voltage follower circuit. This operates as an impedance buffer that performs impedance conversion between the passive filter section and the input terminal of VCO6. The reason why the passive filter and the impedance buffer are configured is that the Miller integrator circuit cannot be used because the signal in the high frequency region is cut through and the attenuation cannot be high. The analog gate circuit 4 is inserted between the resistor 501 and the capacitor 502. This is done to prevent the influence of stray capacitance parasitic on the input terminal of the analog gate circuit 4, especially the influence of the ground capacitance. Also, the resistance 50
The voltage divider circuit composed of 5, the resistor 506 and the resistor 507 is for supplying a DC offset bias so that the signal supplied to the VCO 6 is not indefinite when the analog gate circuit is open.

Now, when the signal Sa as shown in FIG. 6A is supplied to the input terminal 1, Sb, Sc, Sd and Se in FIG. 6 become the same as in the conventional example. T / 2
Since the signal Se is phase error information when the pulse signal Sc is high, this is supplied to the LPF 5. When the T / 2 pulse signal Sc is low, the gate is opened to have a high impedance, so that it holds almost all the charges charged in the capacitor 502 and the like forming the filter and functions as a hold circuit. FIG. 3 is a signal waveform diagram of the head accompanying the rotation of the R-DAT cylinder, and FIG. 4 is a conceptual diagram showing the oscillation frequency of the VCO, and the time axis is the same. 4a, 4b and 4c respectively show the higher input signal bit frequency,
It shows the oscillation frequency and the synchronization state of the VCO when it is shifted to the center and the lower side. The solid line represents the characteristics of the embodiment of the present invention, and the dotted line is that of the conventional example. When the input signal bit frequency deviates from the center, the free run frequency maintains the previous state in the head signal missing section, so that the synchronization pull-in time at the beginning of the next signal section is significantly higher than the conventional example. You can see that it is getting faster.

EFFECTS OF THE INVENTION The clock recovery phase locked loop circuit of the present invention is activated by an edge of an input signal, generates a T / 2 pulse, a VCO circuit, a phase comparison circuit, a low pulse filter, and is activated by an edge of an input signal. Since the analog gate circuit that supplies the output signal of the phase comparison circuit to the low-pass filter for the time of T / 2 pulse is provided, the phase error information is output only at the time when there is phase error information by the analog gate circuit.
It can be supplied to the LPF, and at other times, the output of the phase locked loop is set to high impedance to form a sample hold circuit together with the LPF circuit in the subsequent stage, and the section without phase error information is interpolated with the immediately preceding information. Can be done. This produces an effect of increasing the loop gain and smoothing the phase error signal to stabilize the operation. Further, since the immediately preceding information is held by interpolating even in the section where the head and the tape are not in contact with each other, the sync pull-in time can be shortened and the coverage of the input signal bit rate can be expanded.

Further, by configuring the low-pass filter of the clock recovery phase locked loop circuit of the present invention with a passive filter and an impedance buffer, a high frequency band can be obtained and the attenuation can be made sufficiently high to reduce the output jitter and stabilize the operation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the basic concept of a clock recovery phase locked loop circuit of the present invention, FIG. 2 is a circuit diagram showing a more specific embodiment of the present invention, and FIG. FIG. 4 is a conceptual diagram showing the VCO oscillation frequency, FIG. 5 is a block diagram showing the configuration of a conventional example, and FIG. 6 is a clock recovery of the conventional example. It is a timing waveform diagram of a phase synchronization circuit. 2 ... T / 2 pulse generation circuit, 3 ... phase comparison circuit, 4 ...
... Analog gate circuit, 5 ... Low-pass filter, 6 ...
… VCO circuit, 508… operational amplifier.

Claims (2)

[Claims] 1. T / 2 activated by an edge of an input signal
A circuit that generates a pulse of (T is the minimum inversion period), a VCO circuit whose frequency is controlled by a control signal, a phase comparison circuit, a low-pass filter that acts as a loop filter, and T that is activated by the edge of the input signal. A clock recovery phase synchronization circuit characterized by comprising an analog gate circuit that supplies the output signal of the phase comparison circuit to a low-pass filter only for the time of / 2 pulse. 2. The clock recovery phase locked loop circuit according to claim 1, wherein the low pass filter comprises a passive filter and an impedance buffer.