JPH07273430A - Manufacture of electric wiring board - Google Patents

Manufacture of electric wiring board

Info

Publication number
JPH07273430A
JPH07273430A JP6308394A JP6308394A JPH07273430A JP H07273430 A JPH07273430 A JP H07273430A JP 6308394 A JP6308394 A JP 6308394A JP 6308394 A JP6308394 A JP 6308394A JP H07273430 A JPH07273430 A JP H07273430A
Authority
JP
Japan
Prior art keywords
short
circuit
wiring
manufacturing
electric wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6308394A
Other languages
Japanese (ja)
Inventor
Osamu Takamatsu
修 高松
Nobuaki Oguri
宣明 大栗
Masato Niibe
正人 新部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP6308394A priority Critical patent/JPH07273430A/en
Publication of JPH07273430A publication Critical patent/JPH07273430A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02WCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO WASTEWATER TREATMENT OR WASTE MANAGEMENT
    • Y02W30/00Technologies for solid waste management
    • Y02W30/50Reuse, recycling or recovery technologies
    • Y02W30/82Recycling of waste of electrical or electronic equipment [WEEE]

Landscapes

  • Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To locally heat an etching solution in the vicinity of a short-circuit part, accelerate etching, and selectively eliminate the short-circuit part defect, by applying a current to the short-circuit part, after etching solution of wiring material is brought into contact with the short-circuit defect part generated at the point of intersection between multilayered wirings formed via an insulating layer and in the gap between adjacent wirings. CONSTITUTION:On a substrate 4 composed of a cleaned blue plate glass, Cu and Au are deposited to have the respective specified thicknesses by a vacuum evaporation method, and then worked into a desired pattern by a photoetching method. Thus a row direction wiring 1 is formed. An interlayer insulating film 5 composed of SiO2 is deposited by an RF sputtering method, and worked into a desired pattern by a photoetching method. By a lift-off method, a Ti film and an Au film having the respective specified thicknesses are formed by a vacuum evaporation method, and an unnecessary film is eliminated. Thus a column direction wiring 2 is formed. A short-circuit part 6 between the wirings is detected, and thereon etching solution 7 is dripped. The short-circuit part 6 is etched and eliminated by applying a current across the wirings having short-circuit defect part 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電気配線基板の製造方
法、特に平面型画像表示装置等に用いられる電気配線基
板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electric wiring board, and more particularly to a method for manufacturing an electric wiring board used for a flat image display device or the like.

【0002】[0002]

【従来の技術】近年、情報機器や家庭用TV受像機の分
野において、薄型で、視認性の良い画像表示装置が求め
られている。従来、薄型の画像表示装置としては、例え
ば、液晶表示装置、EL表示装置、あるいはプラズマデ
ィスプレイ等が開発されているが、これらには視野角、
カラー化、輝度等に問題があり、市場の要求する性能を
十分満足しているとは言えない状況である。
2. Description of the Related Art In recent years, in the field of information equipment and home TV receivers, thin and highly visible image display devices have been demanded. Conventionally, as a thin image display device, for example, a liquid crystal display device, an EL display device, a plasma display, or the like has been developed.
There are problems in colorization and brightness, and it cannot be said that the performance required by the market is sufficiently satisfied.

【0003】そこで、平面型画像表示装置として、放出
電子により蛍光体を発光させ、画像を形成する蛍光体発
光型画像表示装置が期待されている。電子放出素子とし
ては電界放出型(以下FEと略す)、金属/絶縁層/金
属型(以下MIMと略す)や表面伝導型等がある。
Therefore, as a flat image display device, a fluorescent substance light emitting type image display device which emits a fluorescent substance by emitted electrons to form an image is expected. Examples of the electron-emitting device include field emission type (hereinafter abbreviated as FE), metal / insulating layer / metal type (hereinafter abbreviated as MIM), surface conduction type, and the like.

【0004】FE型の例としては、W.P.Dyke&
W.W.Dolan,“Fieldemissio
n”,Advance in Electron Ph
ysics,8,89(1956)等に記載のものが知
られている。
As an example of the FE type, W. P. Dyke &
W. W. Dolan, "Fielddemissio
n ", Advance in Electron Ph
Those described in ysics, 8, 89 (1956) and the like are known.

【0005】MIMの例としては、C.A.Mead,
“The tunnel−emission ampl
ifier”,J.Appl.Phys.,32,64
6(1961)やC.A.Spindt,“Physi
cal properties ofthin−fil
m field emission cathodes
with molybdenum cones”,
J.Appl.Phys.,47,5248(197
6)等に記載のものが知られている。
An example of MIM is C.I. A. Mead,
"The tunnel-emission ampl
ifer ", J. Appl. Phys., 32, 64.
6 (1961) and C.I. A. Spindt, "Physi
cal properties of thin-fil
m field emission cathodes
with mollybdenum cones ”,
J. Appl. Phys. , 47, 5248 (197)
Those described in 6) and the like are known.

【0006】表面伝導型電子放出素子型の例としては、
M.I.Elinson,Radio Eng.Ele
ctron Pys.,10,(1965)等に記載の
ものが知られている。
As an example of the surface conduction electron-emitting device type,
M. I. Elinson, Radio Eng. Ele
ctron Pys. , 10, (1965) and the like are known.

【0007】表面伝導型電子放出素子(SCE)は、基
板上に形成された小面積の薄膜に、膜面に平行に、電流
を流すことにより、電子放出が生じる現象を利用するも
のである。この表面伝導型電子放出素子としては、前記
エリンソン等によるSnO2薄膜を用いたもの、Au薄
膜によるもの〔G.Dittmer:“Thin So
lid Films”,9,317(1972)〕,I
23 /SnO2 薄膜によるもの〔M.Hartwe
ll and C.G.Fonstad:“IEEE
Trans.ED Conf.”519,(197
5)〕,カーボン薄膜によるもの〔荒木 久 他:真
空、第26巻、第1号、22頁(1983)〕等が報告
されている。
The surface conduction electron-emitting device (SCE) utilizes a phenomenon in which a thin film having a small area formed on a substrate causes electron emission by flowing an electric current in parallel with the film surface. As the surface conduction electron-emitting device, one using the SnO 2 thin film by the above-mentioned Erinson, one using the Au thin film [G. Dittmer: "Thin So
lid Films ", 9, 317 (1972)], I
n 2 O 3 / SnO 2 thin film [M. Hartwe
ll and C.I. G. Fonstad: “IEEE
Trans. ED Conf. "519, (197
5)], a carbon thin film [Hiraki Araki et al .: Vacuum, Vol. 26, No. 1, p. 22 (1983)] and the like have been reported.

【0008】これら表面伝導型電子放出素子の典型的な
製造方法は、2つの素子電極を隣接して配置し、その2
つの電極間隔に渡って薄膜を形成し、更にフォーミング
と呼ばれる、薄膜に電界を印加し、薄膜を局所的に破
壊、変形もしくは変質せしめ、電気的に高抵抗な状態に
する工程を通して電子放出部を形成している。このよう
にして製造した電子放出素子と蛍光体とを組み合わせて
描画する機能を付与することにより、画像表示装置が作
製される。これら蛍光体発光型画像表示装置は、具体的
には必要とする画面サイズに対応した大きさの2枚のガ
ラス基板間を用い、その一方をマトリックス状に配置し
た電子放出素子及び、各電子放出素子を駆動するための
行方向配線、列方向配線などの画像表示装置構成要素を
形成した素子基板とし、他方を蛍光体を形成しフェース
プレートとし、これらの基板を互に対向させて、フリッ
トガラスで封止することにより形成されている。
A typical method of manufacturing these surface conduction electron-emitting devices is to arrange two device electrodes adjacent to each other, and
A thin film is formed over the distance between two electrodes, and then an electric field is applied to the thin film, called forming, to locally destroy, deform, or alter the thin film, and through the process of making it into an electrically high resistance state, the electron emission part is formed. Is forming. An image display device is manufactured by adding a function of drawing by combining the electron-emitting device thus manufactured and the phosphor. These phosphor-emission-type image display devices specifically use an electron-emitting device in which two glass substrates having a size corresponding to a required screen size are used, and one of them is arranged in a matrix, and each electron-emitting device. A frit glass is used as an element substrate on which image display device components such as row-direction wiring and column-direction wiring for driving the elements are formed, and the other is formed as a face plate by forming a phosphor. It is formed by sealing with.

【0009】尚、電子放出素子には比較的大きな電流を
流す必要があることから、これらの配線材料にはエレク
トロマイグレーションを生じにくいAu,CuまたはA
gが用いられている。
Since it is necessary to pass a relatively large current through the electron-emitting device, Au, Cu or A which is less likely to cause electromigration in these wiring materials.
g is used.

【0010】これら平面型画像表示装置等の製造方法は
液晶表示装置の製造方法とほぼ同じ方法で作製されるた
め、高精細化、大面積化が進むにつれ、電極数が増大し
基板あたりの配線間の欠陥が増加するという問題があ
る。
Since the manufacturing method of these flat panel image display devices and the like is almost the same as the manufacturing method of liquid crystal display devices, the number of electrodes increases and the wiring per substrate increases with the progress of higher definition and larger area. There is a problem that the number of defects increases.

【0011】これら素子基板は製造単価が高いことか
ら、欠陥品を直ちに不良廃棄するよりも、少量の欠陥な
らば欠陥箇所の修正を行い良品とするほうが望ましい。
この欠陥の種類としては、断線による欠陥、及び短絡に
よる欠陥に大別できる。ここで断線による欠陥について
は、各配線の両端から駆動信号を供給することにより救
済できる可能性がある。これに対し水平方向、すなわち
同一面内に形成された隣り合う配線間の短絡欠陥(隣接
間ショート)及び垂直方向、すなわち絶縁層を介して積
層された2種類の配線間の交差部における短絡欠陥(層
間ショート)は線欠陥として画像上に現われるため、欠
陥の修正が必要である。
Since these element substrates have a high manufacturing unit price, it is desirable to correct defective parts and correct them to make them defective rather than immediately discarding defective products.
The types of defects can be roughly classified into defects due to disconnection and defects due to short circuit. Here, the defect due to the disconnection may be relieved by supplying the drive signal from both ends of each wiring. On the other hand, in the horizontal direction, that is, a short-circuit defect between adjacent wirings formed in the same plane (short-circuit between adjacent wirings) and in the vertical direction, that is, a short-circuit defect at an intersection between two types of wirings laminated via an insulating layer. Since (interlayer short-circuit) appears on the image as a line defect, it is necessary to correct the defect.

【0012】従来、液晶表示装置等の製造においては、
このような欠陥箇所の修正に、レーザ光(YAG:波長
1.06μm)を用い、図4に示すように、配線82b
と配線81bとの層間短絡箇所86の配線の両端を切断
して(切断部88a,88b)修正をしている。
Conventionally, in the manufacture of liquid crystal display devices and the like,
Laser light (YAG: wavelength 1.06 μm) is used to correct such defective portions, and wiring 82b is used as shown in FIG.
Both ends of the wiring at the inter-layer short-circuited portion 86 between the wiring 81b and the wiring 81b are cut (cutting portions 88a, 88b) for correction.

【0013】従来のレーザ光を用いた配線の切断方法は
液晶表示装置等に用いられる配線材料であるAl,C
r,ITO(Indium−Tin−Oxide)等の
金属材料には有効である。しかし、比較的電流をたくさ
ん流す必要がある電子放出素子を用いた画像表示装置は
配線材料としてAu,Cu又はAgを用いているが、こ
れらの材料を用いた配線のレーザ光による切断は難しか
った。また、従来のように配線を切断し短絡部を修正す
る方法では、同一ライン上に複数の欠陥が生じている場
合には、線欠陥となってしまう問題がある。
A conventional method of cutting a wiring using a laser beam is Al and C which are wiring materials used in a liquid crystal display device or the like.
It is effective for metal materials such as r and ITO (Indium-Tin-Oxide). However, although an image display device using an electron-emitting device that needs to flow a relatively large amount of current uses Au, Cu, or Ag as a wiring material, it is difficult to cut the wiring using these materials by laser light. . Further, the conventional method of cutting the wiring and correcting the short-circuited portion has a problem that a line defect occurs when a plurality of defects occur on the same line.

【0014】[0014]

【発明が解決しようとする課題】本発明者は上記問題を
解決するために種々検討した結果、短絡欠陥部は配線よ
りも高抵抗であるので、エッチング液と接触した状態で
電流を配線に流すと短絡欠陥部が選択的に発熱し、短絡
欠陥部のエッチング速度が高まって短絡欠陥部が選択的
にエッチングされ、除去されるのに対し、電線はほとん
ど発熱しないので、エッチング速度に変化がなく、従っ
て短絡欠陥部だけを選択的にエッチングして除去できる
ことに想到し、本発明を完成するに致ったもので、その
目的とする所は、上記問題を解決した電気配線基板の製
造方法を提供することにある。
As a result of various studies for solving the above problems, the present inventor has found that the short-circuit defect portion has a higher resistance than the wiring, so that a current is passed through the wiring in a state of being in contact with the etching solution. And the short-circuit defect part selectively heats up, the etching speed of the short-circuit defect part increases and the short-circuit defect part is selectively etched and removed, whereas the wire hardly heats up, so there is no change in the etching rate. Therefore, it was conceived that only the short-circuit defect portion can be selectively etched and removed, and the present invention was completed, and the purpose thereof is to provide a method for manufacturing an electric wiring board which solves the above problems. To provide.

【0015】[0015]

【課題を解決するための手段】上記目的を達成するため
に本発明は、基板に電気伝導材料を用いて相互に絶縁さ
れた複数のパターンよりなる電気配線を形成してなる電
気配線基板の製造方法において、前記複数のパターンよ
りなる電気配線の製造中の短絡欠陥部の修正工程として
前記電気伝導材料のエッチング液に前記配線の少なくと
も短絡欠陥部を接触させて少なくとも前記短絡欠陥部を
共有する電線間に電圧を印加して前記短絡欠陥部に電流
を流し前記短絡欠陥部を除去する工程を有することを特
徴とする電気配線基板の製造方法を提案するもので、短
絡欠陥部にエッチング液を滴下して接触させること、基
板をエッチング液に浸漬して接触させること、前記電気
配線が平面型画像表示装置に用いられる複数の列方向配
線と絶縁層を介して積層された複数の行方向配線からな
るマトリックス状の配線であること、前記短絡欠陥部が
同一面内に形成された複数の隣接する配線間に存在する
ものであること、前記短絡欠陥部が絶縁層を介して積層
された複数の配線パターンの交差部に存在するものであ
ること、前記エッチング液が、前記電気伝導材料を室温
で一秒間に1nm以下の速度でエッチングするものであ
ること、前記電気伝導材料が金、銅又は銀もしくはこれ
らを含む材料であることを含む。
In order to achieve the above object, the present invention is directed to manufacturing an electric wiring board in which electric wiring made of a plurality of patterns insulated from each other by using an electrically conductive material is formed on the board. In the method, an electric wire that shares at least the short-circuit defective portion by contacting at least the short-circuit defective portion of the wiring with an etching solution of the electrically conductive material as a step of correcting the short-circuit defective portion during manufacturing of the electric wiring including the plurality of patterns. It proposes a method for manufacturing an electric wiring board, characterized in that it comprises a step of applying a voltage between them to cause an electric current to flow through the short-circuit defective portion and removing the short-circuit defective portion. To make contact with each other by immersing the substrate in an etching solution so as to make contact with the electric wiring through a plurality of column-direction wirings and insulating layers used in a flat panel image display device. It is a matrix-shaped wiring composed of a plurality of stacked row-direction wirings, the short-circuit defective portion is present between a plurality of adjacent wirings formed in the same plane, and the short-circuit defective portion is insulated. That it exists at the intersection of a plurality of wiring patterns laminated via a layer, that the etching liquid etches the electrically conductive material at room temperature at a rate of 1 nm or less per second, and It includes that the electrically conductive material is gold, copper or silver or a material containing these.

【0016】[0016]

【作用】本発明の電気配線基板の製造方法によれば、絶
縁層を介して形成した積層配線間の交点及び、配線の隣
接間に生じた短絡欠陥部にすくなくとも該配線材料のエ
ッチング液を接触させた後、短絡部に通電を行うことに
より、短絡部近傍のエッチング液を局部的に加熱し、エ
ッチングを進行させ短絡欠陥部を選択的に除去するよう
にしたものである。すなわち短絡欠陥部に電流を流すこ
とにより、ジュール熱を生じること、及びエッチンググ
レートは温度により変化することを利用したものであ
り、短絡部を加熱し局部的にエッチングすることにより
短絡欠陥部の修正を行うものである。
According to the method for manufacturing an electric wiring board of the present invention, an etching solution for the wiring material is brought into contact with at least the intersection between the laminated wirings formed via the insulating layer and the short-circuit defect portion generated between the adjacent wirings. After that, the short-circuited portion is energized to locally heat the etching solution in the vicinity of the short-circuited portion to allow the etching to proceed to selectively remove the short-circuited defective portion. In other words, the fact that Joule heat is generated by passing an electric current through the short-circuit defect portion and that the etching grade changes with temperature are utilized, and the short-circuit defect portion is repaired by heating the short-circuit portion and locally etching it. Is to do.

【0017】以下、図面を参照して本発明を詳細に説明
する。
The present invention will be described in detail below with reference to the drawings.

【0018】まず、図1を用いて電気配線基板の一般的
な製造方法について説明する。
First, a general method for manufacturing an electric wiring board will be described with reference to FIG.

【0019】図1(a)において、4は基板で、絶縁物
又は半導体が用いられる。これらの具体例としては、石
英ガラス、Na等の不純物含有量を減少したガラス、青
板ガラス、青板ガラスにスパッタ法等により形成したS
iO2 を積層したガラス基板等及びアルミナ等のセラミ
ックス、及びシリコン、ガリウム砒素等がある。
In FIG. 1A, reference numeral 4 denotes a substrate, which is made of an insulator or a semiconductor. Specific examples of these include quartz glass, glass with a reduced content of impurities such as Na, soda-lime glass, and S formed by soaking on soda-lime glass.
Examples thereof include a glass substrate on which iO 2 is laminated, ceramics such as alumina, and silicon and gallium arsenide.

【0020】次に、基板4上に列方向配線1、層間絶縁
層5、行方向配線2を形成する。
Next, the column-direction wiring 1, the interlayer insulating layer 5, and the row-direction wiring 2 are formed on the substrate 4.

【0021】行方向配線2及び列方向配線1は真空蒸着
法、スパッタ法、メッキ法、印刷法等で形成する。配線
は所望のパターンの電気伝導材料からなり、多数の素子
にできるだけほぼ均等な電圧が供給されるように膜厚、
配線幅等を決定する。また材料としては低抵抗でエレク
トロマイグレーションの生じくにいAu,Cu及びAg
が好ましい。なお基板4が半導体基板の場合には表面に
絶縁層を形成し、その上に配線を形成する。これら複数
本の行方向配線2と複数本の列方向配線1との間には層
間絶縁層5が設置され、マトリックス配線を構成する。
The row wiring 2 and the column wiring 1 are formed by a vacuum evaporation method, a sputtering method, a plating method, a printing method, or the like. The wiring is made of an electrically conductive material with a desired pattern, and has a film thickness so that almost uniform voltage can be supplied to many elements,
Determine the wiring width, etc. As a material, Au, Cu and Ag are low in resistance and resistant to electromigration.
Is preferred. When the substrate 4 is a semiconductor substrate, an insulating layer is formed on the surface and wiring is formed thereon. An interlayer insulating layer 5 is provided between the plurality of row-direction wirings 2 and the plurality of column-direction wirings 1 to form a matrix wiring.

【0022】ここで、層間絶縁層5としては、蒸着法、
スパッタ法、印刷法等で形成したSiO2 等が好まし
く、列方向配線1を形成した基板4の全面あるいは一部
に所望の形状で形成され列方向配線1と行方向配線2と
を絶縁している。
Here, as the interlayer insulating layer 5, a vapor deposition method,
SiO 2 or the like formed by a sputtering method, a printing method, or the like is preferable, and is formed in a desired shape on the entire surface or a part of the substrate 4 on which the column-directional wiring 1 is formed to insulate the column-directional wiring 1 and the row-directional wiring 2. There is.

【0023】通常の製造工程においては、各配線間が絶
縁され、短絡欠陥部が存在しない電気配線基板が製造さ
れるものであるが、事故等の避け得ない原因で絶縁層の
一部が破損し、各配線間に短絡欠陥箇所が生じる場合が
ある。
In a normal manufacturing process, an electric wiring board in which each wiring is insulated and a short-circuit defect is not present is manufactured. However, a part of the insulating layer is damaged due to an unavoidable cause such as an accident. However, short-circuit defects may occur between the wirings.

【0024】図1(a)は上記短絡欠陥箇所が発生した
状態を示している。即ち、図1(a)中、6は短絡欠陥
部で、この欠陥部6はマトリックス配線を形成したとき
列方向配線1と行方向配線2との交差部の層間絶縁層5
に生じたピンホール20に起因して生じた短絡欠陥であ
り、これにより列方向配線1と行方向配線2が導通して
いる。
FIG. 1 (a) shows a state in which the short-circuit defect portion has occurred. That is, in FIG. 1A, 6 is a short-circuit defective portion, and this defective portion 6 is an interlayer insulating layer 5 at the intersection of the column-directional wiring 1 and the row-directional wiring 2 when matrix wiring is formed.
This is a short-circuit defect caused by the pinhole 20 caused in the column direction wiring 1 and the row direction wiring 2 are electrically connected.

【0025】本発明の製造方法は、このような短絡欠陥
部6を除去する工程を製造方法中に含むものである。
The manufacturing method of the present invention includes a step of removing such a short-circuit defect portion 6 in the manufacturing method.

【0026】まず図1(a)に示すように、短絡欠陥部
6の上部に配線材料のエッチング液7を滴下し、短絡欠
陥部にエッチング液7を接触させる。エッチング液は公
知のものが使用できる。
First, as shown in FIG. 1A, an etching liquid 7 of a wiring material is dropped on the short-circuit defective portion 6 and the etching liquid 7 is brought into contact with the short-circuit defective portion. A known etching liquid can be used.

【0027】使用するエッチング液は、室温で配線材料
を1nm/sec以下、より好ましくは0.1〜1nm
/secのエッチレートで加工するものが適当である。
The etchant used is a wiring material at room temperature of 1 nm / sec or less, more preferably 0.1 to 1 nm.
It is suitable to process at an etch rate of / sec.

【0028】続いて短絡部を有する列方向配線1と行方
向配線2に電界を印加し短絡欠陥部近傍を発熱させるこ
とにより、短絡欠陥部を選択的にエッチング除去でき
る。尚、このような化学的なエッチングでは10℃の温
度上昇により反応速度が約2倍になることから、温度を
70℃程度室温よりも上昇させることにより、室温時の
100倍程度の早さでエッチ可能である。このため短絡
部の配線を局部的に早くエッチング除去できることから
短絡欠陥を修正できる。短絡欠陥部6に印加する電圧は
配線の断面積、短絡欠陥部6の抵抗値によっても変化す
るので限定できないが、一般に1〜3Vが好ましい。こ
の電流を流すことにより(0.1〜0.5A)、短絡欠
陥部の温度が50〜200℃程度上昇するものである。
Subsequently, an electric field is applied to the column-direction wiring 1 and the row-direction wiring 2 having the short-circuited portion to generate heat near the short-circuited defective portion, whereby the short-circuited defective portion can be selectively removed by etching. In such a chemical etching, the reaction rate increases about twice as much as the temperature rises by 10 ° C. Therefore, by raising the temperature about 70 ° C. above room temperature, it is about 100 times faster than at room temperature. It can be etched. Therefore, the wiring of the short-circuited portion can be locally removed quickly by etching, so that the short-circuit defect can be corrected. The voltage applied to the short-circuit defect portion 6 cannot be limited because it varies depending on the cross-sectional area of the wiring and the resistance value of the short-circuit defect portion 6, but is generally preferably 1 to 3V. By flowing this current (0.1 to 0.5 A), the temperature of the short-circuit defect portion rises by about 50 to 200 ° C.

【0029】上記工程により、短絡欠陥部6がエッチン
グされ、図1(b)に示すように列方向配線1と行方向
配線2との間の短絡が除かれる。配線が微細な場合に
は、上記操作は顕微鏡観察下に行なうこともできる。
Through the above steps, the short-circuit defect portion 6 is etched, and the short circuit between the column-direction wiring 1 and the row-direction wiring 2 is removed as shown in FIG. 1 (b). When the wiring is fine, the above operation can be performed under a microscope.

【0030】なお、エッチング液と短絡欠陥部6との接
触方法は上記方法に限られず、例えば配線基板全体、又
は一部をエッチング液に浸漬して行なうこともできる。
この場合に、行及び列方向配線の全てに電圧を印加する
場合には、配線基板上に存在する短絡欠陥のすべてが一
度に除去できる。従って、この場合には予め欠陥の有無
及びどこに欠陥があるかを調べることなく短絡を除去で
き、作業性が良い。
The method of contacting the etching solution with the short-circuit defect portion 6 is not limited to the above method, and it is also possible to immerse the whole or a part of the wiring board in the etching solution.
In this case, when a voltage is applied to all the row-direction and column-direction wirings, all the short-circuit defects existing on the wiring board can be removed at once. Therefore, in this case, the short circuit can be removed without checking the presence or absence of a defect and where the defect is in advance, and the workability is good.

【0031】[0031]

【実施例】【Example】

実施例1 本発明の第1実施例を図1を参照しつつ説明する。 First Embodiment A first embodiment of the present invention will be described with reference to FIG.

【0032】まず、図1(a)に示すように清浄化した
青板ガラスからなる基板4上に、真空蒸着法により厚さ
10nmのCr、厚さ600nmのAuを堆積後フォト
エッチング法により所望のパターンに加工し列方向配線
1を形成した。続いて厚さ1000nmのSiO2 から
なる層間絶縁膜5をRFスパッタ法により堆積し、フォ
トエッチング法により所望のパターンに加工した。続い
てリフトオフ法により厚さ5nmのTi、厚さ500n
mのAuを真空蒸着法で成膜し、不要な膜を除去するこ
とにより行方向配線2を形成した。続いて、配線間の短
絡欠陥を検出し、短絡部6を検知した。
First, as shown in FIG. 1A, 10 nm thick Cr and 600 nm thick Au are deposited on the cleaned substrate 4 made of soda-lime glass by a vacuum vapor deposition method, and then a desired photoetching method is performed. It was processed into a pattern to form the column-direction wiring 1. Subsequently, an interlayer insulating film 5 made of SiO 2 and having a thickness of 1000 nm was deposited by RF sputtering and processed into a desired pattern by photoetching. Subsequently, a lift-off method is used to form Ti having a thickness of 5 nm and a thickness of 500 n.
m of Au was formed by a vacuum vapor deposition method, and an unnecessary film was removed to form the row wiring 2. Then, the short circuit defect between wirings was detected and the short circuit part 6 was detected.

【0033】次に図1(b)に示すように短絡部6上に
エッチング液7を0.01ml滴下した。エッチング液
はKI:I2 :H2 O=1:1:4(容量比)であっ
た。続いて短絡欠陥部6を有する配線間に電流を流すこ
とにより短絡部をエッチング除去した。このとき、短絡
部6は数秒でエッチングされ短絡箇所の消失とともにエ
ッチングが終了した。しかし、短絡部近傍がエッチング
除去されたが配線幅に対して小領域だったので配線が断
線することはなかった。
Next, as shown in FIG. 1 (b), 0.01 ml of the etching liquid 7 was dropped on the short circuit portion 6. The etching solution was KI: I 2 : H 2 O = 1: 1: 4 (volume ratio). Subsequently, the short-circuited portion was removed by etching by passing a current between the wirings having the short-circuited defective portion 6. At this time, the short-circuit portion 6 was etched in a few seconds, and the etching was completed when the short-circuit portion disappeared. However, although the vicinity of the short-circuited portion was removed by etching, it was a small region with respect to the wiring width, so the wiring did not break.

【0034】以上のような製造方法により配線間の短絡
を修正することにより欠陥のない配線基板が形成でき
た。 実施例2 本実施例では、実施例1と同様にして列方向配線1、層
間絶縁膜5、行方向配線2を形成した。続いて、取り出
し配線部をOリング及びシリコンシーラント等で保護し
た後、エッチング液7に基板を浸漬した。このときエッ
チング液7が配線取り出し部に接触しない様にした。な
お、エッチング液は実施例と同じものを用いた。
By correcting the short circuit between the wirings by the above manufacturing method, the wiring board having no defect could be formed. Example 2 In this example, the column-directional wiring 1, the interlayer insulating film 5, and the row-directional wiring 2 were formed in the same manner as in Example 1. Subsequently, the take-out wiring portion was protected with an O-ring and a silicone sealant, and then the substrate was immersed in the etching solution 7. At this time, the etching solution 7 was prevented from coming into contact with the wiring take-out portion. The same etching solution as that used in the example was used.

【0035】その後、全配線に電圧を印加することによ
り、短絡欠陥部6のエッチング除去を行い短絡欠陥を修
正した。この方法によれば短絡欠陥箇所の検査をしなく
ても、短絡箇所の発熱箇所のみがエッチング除去される
ため、検査工程を省略できるという効果がある。 実施例3 本実施例では、実施例1と同様にして列方向配線1、層
間絶縁膜5、行方向配線2を形成した。続いて、配線間
の短絡箇所を検査したところ、行方向配線2の隣接間で
短絡箇所を検知した。そこで、実施例1と同様にエッチ
ング液7を配線間の短絡箇所に滴下した後、短絡配線間
に電流を流すことにより短絡部のエッチング除去を行い
短絡欠陥を修正した。
Then, by applying a voltage to all the wirings, the short-circuit defect portion 6 was removed by etching to correct the short-circuit defect. According to this method, even if the short-circuit defective portion is not inspected, only the heat-generating portion of the short-circuited portion is removed by etching, so that the inspection step can be omitted. Example 3 In this example, the column-directional wiring 1, the interlayer insulating film 5, and the row-directional wiring 2 were formed in the same manner as in Example 1. Then, when a short-circuited portion between the wirings was inspected, a short-circuited portion was detected between adjacent row-direction wirings 2. Therefore, as in Example 1, after the etching liquid 7 was dropped on the short-circuited portion between the wirings, the short-circuited portion was removed by etching by applying a current between the short-circuited wirings to correct the short-circuit defect.

【0036】以上のような製造方法で隣接配線間の短絡
を修正することにより、欠陥のない電極配線が形成でき
た。 実施例4 続いて、本発明の第4実施例を説明する。
By correcting the short circuit between the adjacent wirings by the above manufacturing method, the electrode wiring having no defect could be formed. Fourth Embodiment Next, a fourth embodiment of the present invention will be described.

【0037】ここでは表面伝導型電子放出素子を用いた
平面型画像表示装置の素子基板の構成及びその製造方法
を図1乃至図3を用いて説明する。
Here, the structure of the element substrate of the flat image display device using the surface conduction electron-emitting device and the manufacturing method thereof will be described with reference to FIGS.

【0038】図2は平面型画像表示装置の一部等価回路
図である。
FIG. 2 is a partial equivalent circuit diagram of the flat panel image display device.

【0039】複数本の列方向配線1及びこれらの列方向
配線1に直交する複数本の行方向配線2の各交点に電子
放出素子3が接続され形成されている。ここで図には示
されていないが列方向配線1と行方向配線2の交差部に
は層間絶縁層が形成されており、列方向配線1と行方向
配線2との絶縁がとられている。ここで列方向配線1と
行方向配線2とを適当に選択し電界を印加することで電
子放出素子3から電子を放出することができる。
An electron-emitting device 3 is formed at each intersection of a plurality of column-direction wirings 1 and a plurality of row-direction wirings 2 orthogonal to these column-direction wirings 1. Although not shown in the drawing, an interlayer insulating layer is formed at the intersection of the column-directional wiring 1 and the row-directional wiring 2 to insulate the column-directional wiring 1 and the row-directional wiring 2. . Electrons can be emitted from the electron-emitting device 3 by appropriately selecting the column-direction wiring 1 and the row-direction wiring 2 and applying an electric field.

【0040】まず、図1(a)に示すように実施例1と
同様に清浄化した青板ガラス上に、厚さ10nmのC
r、厚さ600nmのCuからなる列方向配線1を形成
した。続いて厚さ1000nmのSiO2 からなる層間
絶縁膜5をRFスパッタ法により堆積し、フォトエッチ
ング法により所望のパターンに加工した。続いてリフト
オフ法により厚さ5nmのCr、厚さ500nmのCu
を真空蒸着法で成膜し、不要な膜を除去することにより
行方向配線2を形成した。続いて、配線間の短絡欠陥を
検出し、短絡部6を検知した。
First, as shown in FIG. 1A, a soda lime glass cleaned in the same manner as in Example 1 was coated with C having a thickness of 10 nm.
The column-direction wiring 1 made of Cu and having a thickness of 600 nm was formed. Subsequently, an interlayer insulating film 5 made of SiO 2 and having a thickness of 1000 nm was deposited by RF sputtering and processed into a desired pattern by photoetching. Subsequently, a lift-off method is used to form Cr having a thickness of 5 nm and Cu having a thickness of 500 nm.
Was formed by a vacuum evaporation method, and the unnecessary film was removed to form the row wiring 2. Then, the short circuit defect between wirings was detected and the short circuit part 6 was detected.

【0041】次に図1(b)に示すように短絡部6上に
エッチング液7を滴下した。エッチング液にはりん酸:
硝酸:酢酸:水=16:1:80:1(容量比)を用い
た。続いて短絡部6を有する配線間に電流を流すことに
短絡部をエッチング除去した。このとき、短絡部6は数
秒でエッチングされ短絡箇所の消失とともにエッチング
が終了した。しかし、短絡部近傍がエッチング除去され
たが配線幅に対して小領域だったので配線が断線するこ
とはなかった。
Next, as shown in FIG. 1B, the etching solution 7 was dropped on the short circuit portion 6. Phosphoric acid in the etching solution:
Nitric acid: acetic acid: water = 16: 1: 80: 1 (volume ratio) was used. Subsequently, the short-circuited portion was removed by etching by passing a current between the wirings having the short-circuited portion 6. At this time, the short-circuit portion 6 was etched in a few seconds, and the etching was completed when the short-circuit portion disappeared. However, although the vicinity of the short-circuited portion was removed by etching, it was a small region with respect to the wiring width, so the wiring did not break.

【0042】更に、図3に示すように表面伝導型電子放
出素子3を行方向配線2と列方向配線1に接続するよう
に形成した。なお、表面伝導型電子放出素子3は、図示
していないが対向した素子電極間に有機パラジウムを塗
布した後、加熱処理をして、酸化パラジウム微粒子から
なる微粒子膜を形成し、更に微粒子膜に電圧を印加し
(フォーミング処理)電子放出部を作製した。
Further, as shown in FIG. 3, the surface conduction electron-emitting device 3 was formed so as to be connected to the row directional wiring 2 and the column directional wiring 1. Although not shown, the surface conduction electron-emitting device 3 is formed by applying organic palladium between opposing device electrodes and then performing heat treatment to form a fine particle film made of palladium oxide fine particles. A voltage was applied (forming processing) to produce an electron emitting portion.

【0043】以上のような製造方法により、配線間に生
じた短絡欠陥を配線を断線させることなく修正すること
ができるため、同一ライン上に欠陥が多数生じても欠陥
のない平面型画像表示装置の素子基板が形成できる。
By the manufacturing method as described above, the short-circuit defect generated between the wirings can be corrected without disconnecting the wirings. Therefore, even if a large number of defects occur on the same line, the planar image display device has no defect. The element substrate can be formed.

【0044】[0044]

【発明の効果】以上説明したように、本発明の電極配線
の製造方法によれば、Au,Cu又はAgを用いた配線
でも短絡欠陥部の修正ができる。更に配線を切断するこ
となく、短絡部付近のみを除去し修正するため、同一ラ
イン上に短絡欠陥が生じても線欠陥とならない。このた
め画像表示装置等に本方法を応用した場合、製造時の歩
留りを大幅に向上できるという効果がある。
As described above, according to the method of manufacturing the electrode wiring of the present invention, the short circuit defect portion can be repaired even in the wiring using Au, Cu or Ag. Further, since only the short-circuited portion is removed and repaired without cutting the wiring, even if a short-circuiting defect occurs on the same line, it does not become a line defect. Therefore, when the present method is applied to an image display device or the like, there is an effect that the yield at the time of manufacturing can be greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る製造方法の一例を示す工程図であ
る。
FIG. 1 is a process drawing showing an example of a manufacturing method according to the present invention.

【図2】表面伝導型電子放出素子を用いた画像表示装置
の等価回路図である。
FIG. 2 is an equivalent circuit diagram of an image display device using a surface conduction electron-emitting device.

【図3】表面伝導型電子放出素子を用いた画像表示装置
の素子基板の一例を示す平面図である。
FIG. 3 is a plan view showing an example of an element substrate of an image display device using a surface conduction electron-emitting device.

【図4】従来例の短絡欠陥部の修正方法を示す平面図で
ある。
FIG. 4 is a plan view showing a method of repairing a short-circuit defect portion of a conventional example.

【符号の説明】[Explanation of symbols]

1 列方向配線 2 行方向配線 3 電子放出部 4 基板 5 層間絶縁層 6 短絡部 7 エッチング液 1 column direction wiring 2 row direction wiring 3 electron emission part 4 substrate 5 interlayer insulating layer 6 short circuit part 7 etching solution

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 基板に電気伝導材料を用いて相互に絶縁
された複数のパターンよりなる電気配線を形成してなる
電気配線基板の製造方法において、前記複数のパターン
よりなる電気配線の製造中の短絡欠陥部の修正工程とし
て前記電気伝導材料のエッチング液に前記配線の少なく
とも短絡欠陥部を接触させて少なくとも前記短絡欠陥部
を共有する電線間に電圧を印加して前記短絡欠陥部に電
流を流し前記短絡欠陥部を除去する工程を有することを
特徴とする電気配線基板の製造方法。
1. A method of manufacturing an electric wiring board, comprising: forming a plurality of patterns of electric wiring insulated from each other on a substrate using an electrically conductive material; As a step of correcting the short-circuit defective portion, at least the short-circuit defective portion of the wiring is brought into contact with the etching solution of the electrically conductive material, and a voltage is applied between the electric wires sharing at least the short-circuit defective portion to flow a current through the short-circuit defective portion. A method of manufacturing an electric wiring board, comprising a step of removing the short-circuit defect portion.
【請求項2】 短絡欠陥部にエッチング液を滴下して接
触させる請求項1に記載の電気配線基板の製造方法。
2. The method for manufacturing an electric wiring board according to claim 1, wherein an etching solution is dropped onto the short-circuit defect portion and brought into contact therewith.
【請求項3】 基板をエッチング液に浸漬して接触させ
る請求項1に記載の電気配線基板の製造方法。
3. The method of manufacturing an electric wiring board according to claim 1, wherein the board is immersed in an etching solution and brought into contact with the board.
【請求項4】 前記電気配線が平面型画像表示装置に用
いられる複数の列方向配線と絶縁層を介して積層された
複数の行方向配線からなるマトリックス状の配線である
請求項1乃至3のいずれかに記載の電気配線基板の製造
方法。
4. The electric wiring is a matrix wiring composed of a plurality of column-directional wirings used in a flat-panel image display device and a plurality of row-directional wirings laminated via an insulating layer. The method for manufacturing an electric wiring board according to any one of claims.
【請求項5】 前記短絡欠陥部が同一面内に形成された
複数の隣接する配線間に存在するものである請求項1乃
至3のいずれかに記載の電気配線基板の製造方法。
5. The method of manufacturing an electric wiring board according to claim 1, wherein the short-circuit defective portion is present between a plurality of adjacent wirings formed in the same plane.
【請求項6】 前記短絡欠陥部が絶縁層を介して積層さ
れた複数の配線パターンの交差部に存在するものである
請求項1乃至3のいずれかに記載の電気配線基板の製造
方法。
6. The method of manufacturing an electric wiring board according to claim 1, wherein the short-circuit defect portion is present at an intersection of a plurality of wiring patterns laminated with an insulating layer interposed therebetween.
【請求項7】 前記エッチング液が、前記電気伝導材料
を室温で一秒間に1nm以下の速度でエッチングする請
求項1乃至3のいずれかに記載の電気配線基板の製造方
法。
7. The method for manufacturing an electric wiring board according to claim 1, wherein the etching solution etches the electrically conductive material at room temperature at a rate of 1 nm or less per second.
【請求項8】 前記電気伝導材料が金、銅又は銀もしく
はこれらを含む材料である請求項1乃至3のいずれかに
記載の電気配線基板の製造方法。
8. The method of manufacturing an electric wiring board according to claim 1, wherein the electrically conductive material is gold, copper, silver, or a material containing these.
JP6308394A 1994-03-31 1994-03-31 Manufacture of electric wiring board Pending JPH07273430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6308394A JPH07273430A (en) 1994-03-31 1994-03-31 Manufacture of electric wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6308394A JPH07273430A (en) 1994-03-31 1994-03-31 Manufacture of electric wiring board

Publications (1)

Publication Number Publication Date
JPH07273430A true JPH07273430A (en) 1995-10-20

Family

ID=13219093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6308394A Pending JPH07273430A (en) 1994-03-31 1994-03-31 Manufacture of electric wiring board

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005251739A (en) * 2004-02-03 2005-09-15 Toray Ind Inc Repair method and repair tool
JP2005276693A (en) * 2004-03-25 2005-10-06 Matsushita Electric Works Ltd Electron source and its manufacturing method
JP2007026977A (en) * 2005-07-20 2007-02-01 Ulvac Japan Ltd Cathode substrate short-circuit removing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005251739A (en) * 2004-02-03 2005-09-15 Toray Ind Inc Repair method and repair tool
JP2005276693A (en) * 2004-03-25 2005-10-06 Matsushita Electric Works Ltd Electron source and its manufacturing method
JP2007026977A (en) * 2005-07-20 2007-02-01 Ulvac Japan Ltd Cathode substrate short-circuit removing method

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