JPH07273332A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH07273332A JPH07273332A JP5720594A JP5720594A JPH07273332A JP H07273332 A JPH07273332 A JP H07273332A JP 5720594 A JP5720594 A JP 5720594A JP 5720594 A JP5720594 A JP 5720594A JP H07273332 A JPH07273332 A JP H07273332A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- gate electrode
- gate
- insulating film
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は液晶表示素子等に用いら
れる薄膜トランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a liquid crystal display device or the like.
【0002】[0002]
【従来の技術】例えばアクティブマトリックス液晶表示
素子の能動素子として用いられる薄膜トランジスタは、
ガラス等からなる絶縁性の透明な基板の上にゲート電極
およびこのゲート電極を覆うゲート絶縁膜を形成し、さ
らにゲート絶縁膜の上にa−Si(アモルファスシリコ
ン)からなるi型半導体膜を形成するとともに、このi
型半導体膜の上に、不純物をドープしたa−Siからな
るn型半導体膜を介して、ソース電極およびドレイン電
極を形成した構造となっている。2. Description of the Related Art For example, a thin film transistor used as an active element of an active matrix liquid crystal display element is
A gate electrode and a gate insulating film covering the gate electrode are formed on an insulating transparent substrate made of glass or the like, and an i-type semiconductor film made of a-Si (amorphous silicon) is further formed on the gate insulating film. Do this i
A source electrode and a drain electrode are formed on the type semiconductor film via an n-type semiconductor film made of a-Si doped with impurities.
【0003】[0003]
【発明が解決しようとする課題】ところが、ガラス等か
らなる基板は、その表面が鏡面状の平滑状態にあり、こ
のためこの基板の表面と、この基板の表面に形成された
ゲート電極およびゲート絶縁膜との密着性が弱く、この
ため基板の表面からゲート電極やゲート絶縁膜が剥離し
易く、製造上の歩留りを低下させる原因となっている。However, the surface of the substrate made of glass or the like is in a mirror-like smooth state, so that the surface of this substrate and the gate electrode and gate insulation formed on the surface of this substrate are formed. Since the adhesion to the film is weak, the gate electrode and the gate insulating film are easily peeled off from the surface of the substrate, which causes a reduction in manufacturing yield.
【0004】本発明はこのような点に着目してなされた
もので、その目的とするところは、基板の表面と、この
基板の表面に形成されたゲート電極およびゲート絶縁膜
との密着性を高めてゲート電極およびゲート絶縁膜の剥
離を確実に防止することができる薄膜トランジスタを提
供することにある。The present invention has been made by paying attention to such a point, and its purpose is to improve the adhesion between the surface of the substrate and the gate electrode and the gate insulating film formed on the surface of the substrate. Another object of the present invention is to provide a thin film transistor which can surely prevent peeling of a gate electrode and a gate insulating film.
【0005】[0005]
【課題を解決するための手段】本発明は、このような目
的を達成するために、基板の上に、ゲート電極、ゲート
絶縁膜、半導体膜、ソースおよびドレイン電極が形成さ
れた薄膜トランジスタにおいて、前記基板の表面に粗面
化処理を施し、この基板の表面に前記ゲート電極および
ゲート絶縁膜を形成したものである。In order to achieve such an object, the present invention provides a thin film transistor in which a gate electrode, a gate insulating film, a semiconductor film, a source and a drain electrode are formed on a substrate. The surface of the substrate is roughened, and the gate electrode and the gate insulating film are formed on the surface of the substrate.
【0006】[0006]
【作用】このような薄膜トランジスタにおいては、基板
の表面が微細な凹凸状態にあるから、この表面に形成さ
れたゲート電極およびゲート絶縁膜と基板の表面との接
触面積が増大してゲート電極およびゲート絶縁膜の密着
性が向上し、その剥離が確実に防止される。In such a thin film transistor, since the surface of the substrate is in a finely concavo-convex state, the contact area between the gate electrode and the gate insulating film formed on the surface and the surface of the substrate is increased, so that the gate electrode and the gate are formed. Adhesion of the insulating film is improved, and its peeling is surely prevented.
【0007】[0007]
【実施例】以下、本発明の一実施例について図面を参照
して説明する。図1には薄膜トランジスタの断面構造を
示してある。符号1がガラス等からなる絶縁性の基板で
あり、この基板1の上に、ゲート電極2と、このゲート
電極2を覆うSiN(窒化シリコン)等からなるゲート
絶縁膜3と、このゲート絶縁膜3の上に前記ゲート電極
2に対向して配置するa−Si(アモルファスシリコ
ン)からなるi型半導体膜4と、このi型半導体膜4の
上に不純物をドープしたa−Siからなるn型半導体膜
5を介して形成したソース電極6およびドレイン電極7
とが形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional structure of a thin film transistor. Reference numeral 1 is an insulating substrate made of glass or the like, and a gate electrode 2, a gate insulating film 3 made of SiN (silicon nitride) or the like for covering the gate electrode 2, and the gate insulating film are provided on the substrate 1. 3, an i-type semiconductor film 4 made of a-Si (amorphous silicon) arranged to face the gate electrode 2, and an n-type made of a-Si doped with impurities on the i-type semiconductor film 4. Source electrode 6 and drain electrode 7 formed via the semiconductor film 5
And are formed.
【0008】なお、8はi型半導体膜4のチャンネル領
域をそのエッチング時に保護するブロッキング膜であ
る。基板1の表面には粗面化処理aが施され、この粗面
化処理aにより基板1の表面が微細な凹凸状態を呈して
おり、この基板1の表面にゲート電極2およびゲート絶
縁膜3が形成されている。A blocking film 8 protects the channel region of the i-type semiconductor film 4 during etching. The surface of the substrate 1 is subjected to a surface roughening treatment a, and the surface of the substrate 1 has fine irregularities by the surface roughening treatment a, and the gate electrode 2 and the gate insulating film 3 are formed on the surface of the substrate 1. Are formed.
【0009】基板1の表面の粗面化処理aは、例えばA
rプラズマエッチングによる方法、あるいは基板1の溶
解が可能な酸性液やアルカリ液を基板1の表面にシャワ
ー状に吹き付ける方法により行なう。The roughening treatment a of the surface of the substrate 1 is, for example, A
r Plasma etching or a method of spraying an acidic liquid or an alkaline liquid capable of dissolving the substrate 1 onto the surface of the substrate 1 in a shower shape.
【0010】このような構成の薄膜トランジスタにおい
ては、基板1の表面に微細な凹凸状態の粗面化処理aが
施されており、このためこの表面に形成されたゲート電
極2およびゲート絶縁膜3と基板1の表面との接触面積
が増大してゲート電極2およびゲート絶縁膜3が確実か
つ強固に基板1の表面に密着する。したがって基板1の
表面に対するゲート電極2およびゲート絶縁膜3の剥離
が確実に防止され、製造上の歩留りが向上する。In the thin film transistor having such a structure, the surface of the substrate 1 is subjected to a surface roughening treatment a in the form of fine irregularities, and therefore the gate electrode 2 and the gate insulating film 3 formed on the surface are treated. The contact area with the surface of the substrate 1 is increased, and the gate electrode 2 and the gate insulating film 3 are firmly and firmly attached to the surface of the substrate 1. Therefore, peeling of the gate electrode 2 and the gate insulating film 3 from the surface of the substrate 1 is reliably prevented, and the manufacturing yield is improved.
【0011】[0011]
【発明の効果】以上説明したように本発明によれば、基
板の表面に粗面化処理を施し、この基板の表面にゲート
電極およびゲート絶縁膜を形成するようにしたから、基
板の表面とゲート電極およびゲート絶縁膜との密着性を
高めて基板の表面に対するゲート電極およびゲート絶縁
膜の剥離を確実に防止して製造上の歩留りを向上させる
ことができる。As described above, according to the present invention, the surface of the substrate is roughened and the gate electrode and the gate insulating film are formed on the surface of the substrate. Adhesion with the gate electrode and the gate insulating film can be improved, and peeling of the gate electrode and the gate insulating film from the surface of the substrate can be reliably prevented, and the manufacturing yield can be improved.
【図1】本発明の一実施例を示す薄膜トランジスタの断
面図。FIG. 1 is a cross-sectional view of a thin film transistor showing an embodiment of the present invention.
1…基板 2…ゲート電極 3…ゲート絶縁膜 4…i型半導体膜 5…n型半導体膜 6…ソース電極 7…ドレイン電極 a…粗面化処理 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Gate electrode 3 ... Gate insulating film 4 ... i-type semiconductor film 5 ... N-type semiconductor film 6 ... Source electrode 7 ... Drain electrode a ... Roughening treatment
Claims (1)
半導体膜、ソースおよびドレイン電極が形成された薄膜
トランジスタにおいて、 前記基板の表面に粗面化処理を施し、この基板の表面に
前記ゲート電極およびゲート絶縁膜を形成してあること
を特徴とする特徴とする薄膜トランジスタ。1. A gate electrode, a gate insulating film, and
In a thin film transistor having a semiconductor film, source and drain electrodes formed, the surface of the substrate is subjected to a surface roughening treatment, and the gate electrode and the gate insulating film are formed on the surface of the substrate. Thin film transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5720594A JPH07273332A (en) | 1994-03-28 | 1994-03-28 | Thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5720594A JPH07273332A (en) | 1994-03-28 | 1994-03-28 | Thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07273332A true JPH07273332A (en) | 1995-10-20 |
Family
ID=13049008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5720594A Pending JPH07273332A (en) | 1994-03-28 | 1994-03-28 | Thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07273332A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007241295A (en) * | 2006-03-10 | 2007-09-20 | Samsung Electronics Co Ltd | Display device and method of manufacturing the same |
-
1994
- 1994-03-28 JP JP5720594A patent/JPH07273332A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007241295A (en) * | 2006-03-10 | 2007-09-20 | Samsung Electronics Co Ltd | Display device and method of manufacturing the same |
US8143621B2 (en) | 2006-03-10 | 2012-03-27 | Samsung Electronics Co., Ltd. | Active type display device |
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