JPH07273294A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide an analog/digital mixed semiconductor device which reduces a chip size and which can reduce production costs. CONSTITUTION:In a semiconductor device for communication, a prescaler 11 which handles a digital signal and an amplifier circuit 15 which handles an analog signal are formed on a semiconductor substrate 10. The prescaler 11 and the amplifier circuit 15 are separated at a prescribed interval, and a region between the prescaler 11 and the amplifier circuit 15 is used as a pattern region 18. Various patterns which have nothing to do with the prescaler 11 and the amplifier circuit 15 in terms of a circuit and which are required to amnufacture the semiconductor device are formed in the pattern region 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital mixed type semiconductor device in which a digital circuit section and an analog circuit section are formed together on the same semiconductor circuit board.

In recent years, analog / digital mixed type semiconductor integrated circuits have begun to be used in consumer semiconductor devices due to the demand for multifunction and miniaturization. This analog /
In a mixed digital semiconductor integrated circuit, an analog circuit section such as an amplifier circuit that handles a linear signal, an analog filter, and a voltage controlled oscillator circuit, and a digital circuit section including a logic circuit are mixed on the same semiconductor substrate.

Therefore, since the analog semiconductor device and the digital semiconductor device, which are conventionally separately configured, are integrated, an extremely small-sized semiconductor device having multiple functions can be provided. However, since the analog circuit part and the digital circuit part are formed on the same substrate,
Switching noise generated in the digital circuit section may affect the analog circuit section. Therefore, it is required to reduce the influence of this noise.

[0004]

2. Description of the Related Art FIG. 16 shows a conventional analog / digital mixed type semiconductor device. On a semiconductor substrate 80 of this semiconductor device, a digital circuit portion 81 and an analog circuit portion 82 are arranged with a separation region 84 having a predetermined space therebetween. The width of the separation region 84 is set to about 100 μm. The separation region 84 prevents mutual interference between the digital circuit unit 81 and the analog circuit unit 82, and can reduce the influence of switching noise generated in the digital circuit unit 81 on the analog circuit unit 82.

[0005]

However, the semiconductor substrate 50 is further provided with a pattern region 83 having a pattern required for the manufacturing process such as a mask alignment pattern, a characteristic check monitor pattern, a diffusion monitor pattern, an etching monitor pattern, and the like. It is provided. In addition to the pattern area 83, the digital circuit section 81 and the analog circuit section 82 are separated from each other, so that the chip size must be increased in the analog / digital mixed type semiconductor device. Therefore, an increase in chip size causes a decrease in yield and an increase in cost of the semiconductor device.

The present invention has been made to solve the above problems, and an object thereof is to reduce the chip size, improve the yield, and reduce the manufacturing cost.
It is to provide a digital mixed type semiconductor device.

[0007]

FIG. 1 is a diagram for explaining the principle of the present invention. On a semiconductor substrate 1, a digital circuit section 2 that handles digital signals and an analog circuit section 3 that handles analog signals are provided at a predetermined interval. A pattern area 4 is provided between the digital circuit section 2 and the analog circuit section 3. The pattern area 4 has no circuit relationship with the digital circuit section 2 and the analog circuit section 3,
Various patterns necessary for manufacturing a semiconductor device are arranged.

[0008]

According to the configuration of the present invention, since the digital circuit section 2 and the analog circuit section 3 are provided with the pattern area 4 interposed therebetween, the influence of noise generated in the digital circuit section 2 on the analog circuit section 3 is affected. Is reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in a semiconductor device for communication equipment will be described below with reference to FIGS.

As shown in FIG. 2, a prescaler 11 serving as a digital circuit portion and an amplifier circuit 15 serving as an analog circuit portion are formed on the N-type semiconductor substrate 10 at a predetermined interval, and the prescaler 11 and the amplifier circuit are provided. The area between 15 is a pattern area 18.

The prescaler 11 sets the frequency of the input signal to 1
It is configured by connecting in series two frequency dividing circuits 12 that divide the frequency by 1/2. The prescaler 11 divides the frequency of the clock signal, which is a digital signal input via the input terminal 13, into quarters and outputs the divided signal via the output terminal 14. Further, power supply terminals 40 and 41 are provided on the periphery of the semiconductor substrate 10. Terminal 4 for semiconductor devices
The operating power supplies Vcc and GND are externally supplied via 0 and 41.

The amplifier circuit 15 is a bipolar transistor 1
5a and 15b are connected by Darlington connection. Amplifier circuit 1
5 is an input terminal 16, an output terminal 17 and a ground terminal GND
It is connected to the.

In the pattern region 18, as shown in FIGS. 3 to 9, various patterns which are irrelevant to the operation of the semiconductor device and which are necessary only in the manufacturing process are formed.

FIG. 3 shows patterns of the element characteristic monitor element and the pad for probing measurement. The element characteristic monitor element 18a includes a PMOS transistor 19 and an NMO.
It is composed of an S transistor 21.

The PMOS transistor 19 has a P-type diffusion portion 19a formed in a square shape on the N-type semiconductor substrate 10,
19b and a gate portion 2 made of polysilicon and disposed so as to pass above the intermediate portion between the diffusion portions 19a and 19b.
It consists of 2.

The NMOS transistor 21 has N-type diffusion portions 21a and 21b in the P-well 20 formed on the N-type semiconductor substrate 10 and the gate portion which passes above an intermediate portion between the N-type diffusion portions 21a and 21b. And 22.

A plurality of probing measurement pads 23 are formed adjacent to the element characteristic monitor element 18a. The pad 23 is formed by the aluminum wiring 24, and the P type diffusion portions 19a and 19b and the N type diffusion portions 21a and 2
1b and the gate portion 22 are respectively connected.

In this embodiment, the overall size of the pattern including the pad 23 and the element characteristic monitor element 18a is set to about 200 microns in the vertical direction in which the pads 23 are arranged and about 100 microns in the horizontal direction. There is.

The element characteristic monitor element 18a is used as a diffusion monitor for checking the diffusion state in the wafer forming process. For example, after the completion of the wafer, the probe of the tester is brought into contact with the pad 23, and the P / N
The breakdown voltage of the junction or the current amplification factor (h _FE ) of the transistors 19 and 21 is measured. The state of the wafer is checked based on the measurement result. As described above, the element characteristic monitor element 18a is used only for characteristic management, and is not used during normal operation of the semiconductor device.

FIG. 4 shows the ring oscillator circuit 25.
The ring oscillator circuit 25 includes an odd number of inverters 25a.
Are connected in series, and the oscillation frequency is determined by the delay time of each inverter 25a. An inverter 25b that stabilizes the oscillation of the ring oscillator circuit 25 is connected to the output side of the final stage inverter 25a.

Each of the inverters 25a and 25b is a PMO.
It is composed of PMOS and NMOS transistors similar to the S transistor 19 and the NMOS transistor 21. Then, by detecting the oscillation frequency of the oscillation circuit 25,
The gate switching speed of the element forming the prescaler 11 formed on the substrate 10 can be detected, and the high frequency characteristic is evaluated.

FIG. 5 shows a mask alignment pattern 26, which is used when aligning the position of a photomask used in a wafer manufacturing process with a wafer. The mask alignment pattern 26 has about 10
The size is 0 micron square, and about 2 to 10 pieces are arranged according to the number of masks used.

An etching monitor pattern 27 is shown in FIG. The etching monitor pattern 27 is one in which an electrode window portion (having a size of about 50 μm square) 29 is formed on the diffusion resistance portion 28, and several are arranged according to the etching process. The monitor pattern 29 is used for detecting the end point when etching the electrode window.

FIG. 7 shows an exposure size measuring pattern 30. This pattern 30 is 10, 20, 40
Micron width polysilicon electrode 31 for MOS gate
a, 31b, 31c. Each electrode 31a, 31b,
31c are formed so as to be separated from each other by 10 microns. Then, during the resist etching, the electrodes 31a, 31b, 31c are over-etched due to the swelling of the etching side, as shown by the chain double-dashed line. This pattern 30 measures the resist remaining width,
It is used to adjust the etching time and the like.

FIG. 8 shows the marking pad 32. The pattern 32 is formed of aluminum wiring into a substantially square shape having a side of about 100 microns. The pad 32 is scratched with a needle or the like to identify a defective chip during a wafer test.

FIG. 9 shows a mask number identification character pattern 33. The size of the character pattern 33 is about 20 μm in length and width. Since an exposure mask called a reticle is set by a machine, it is checked whether it is a correct mask by comparing the character pattern 33 with the mask number of the mask.

In the above structure, the output terminal 14 of the prescaler 11 and the input terminal 16 of the amplifier circuit 15 are connected by external wiring, for example, wiring on the mounting substrate. Then, for example, 1 GH is applied to the input terminal 13 of the prescaler 11.
When the z clock signal is input, the output terminal 14 outputs a 1/4 frequency-divided 250 MHz signal.

This output signal is input to the amplifier circuit 15 through the external wiring through the input terminal 16 and is amplified.
For example, it is sent from the output terminal 17 to a PLL or the like. At this time, noise generated in the prescaler 11 at the time of frequency division is attenuated by the interval of 100 μm between the prescaler 11 and the amplifier circuit 15, and does not affect the signal of the amplifier circuit 15.

As described in detail above, in this embodiment, the pattern region 18 is provided between the prescaler 11 and the amplifier circuit 15.
Then, various patterns which are irrelevant to the operation of the semiconductor device and which are necessary for manufacturing the semiconductor device are formed in the pattern region 18. Therefore, the size of the semiconductor substrate 10 can be reduced, the yield can be improved, and the manufacturing cost can be reduced.

Further, since the prescaler 11 and the amplifier circuit 15 are arranged with the pattern region 18 interposed therebetween, the influence of the amplifier circuit 15 on the switching noise generated by the frequency dividing operation of the prescaler 11 can be reduced.

Next, another embodiment in which the present invention is embodied in a PLL synthesizer will be described with reference to FIGS.
In the following description, the same components as those of the above-described embodiment will be designated by the same reference numerals in the drawings, and the description thereof will be partially omitted.

As shown in FIG. 15, the PLL synthesizer includes a reference oscillator 46, a reference frequency divider 47, and a phase comparator 4.
8, charge pump 49, low-pass filter (hereinafter simply referred to as LPF) 50, voltage controlled oscillator (hereinafter simply referred to as V
It is configured by including a CO, 51, an amplifier circuit 15, a mixer 52, a prescaler 11, and a comparison frequency divider 53.

The crystal oscillator 46a and the reference oscillator 46 output an oscillation signal of a predetermined frequency with an accurate cycle.
This oscillation signal is divided into a reference frequency by the reference frequency divider 47 and output to the phase comparator 48 as a reference signal.

On the other hand, the output frequency signal output from the VCO 51 is input to the prescaler 11 via the amplifier circuit 15. The frequency of this frequency signal is the prescaler 11
Is normally divided by 1 / (M + 1) and output as a divided signal. Note that M is a natural number. The divided signal is
The comparison frequency divider 53 further divides the frequency based on the set frequency and outputs it as a comparison signal.

The phases of the reference signal and the comparison signal are compared by the phase comparator 48, and the phase difference signal based on the comparison result is output to the charge pump 49. The charge pump 49 is charged and discharged based on this phase difference signal, and its output is smoothed by the LPF 50 and output to the VCO 51 as a control voltage signal.

Then, a frequency signal having a frequency corresponding to the voltage value of the control voltage signal of the LPF 50 is output from the VCO 51, and this frequency signal is fed back to the prescaler 11.
By repeatedly performing such an operation, the VC
The O51 frequency signal is finally locked to a multiplication of the frequency of the reference signal.

As shown in FIG. 10, an N-type semiconductor substrate 10
A prescaler 11 as a digital circuit portion is formed on the substrate 10 on the left side of FIG. Prescaler 1
1 is configured by connecting two frequency dividing circuits 12 in series. A Vcc-side power supply pad 40 and a Vss-side power supply pad 40a are formed on the end portion of the substrate 10.

The power supply pads 40 and 40a are connected to the frequency dividing circuit 12 via pattern wiring.
Further, an input terminal pad 13a and an output terminal pad 14a of the prescaler 11 are formed, and the frequency dividing circuit 1
2 through the pattern wiring.

On the other hand, on the right side of the substrate 10, a VCO (voltage controlled oscillator) is provided as an analog circuit portion on the substrate 10.
An amplifier circuit 15 for amplifying the oscillation signal of is formed.

Other than the prescaler 11 and the amplifier circuit 15, a reference oscillator 46, a reference frequency divider 47, and a phase comparator 4
8, the charge pump 49, the LPF 50, the VCO 51, the mixer 52, and the comparison frequency divider 53 are arranged in another semiconductor device or substrate (not shown).

As shown in FIG. 11, the amplifier circuit 15 has two
It is composed of individual bipolar transistors 15a and 15b. Each transistor 15a, 15b
Is an N-type collector region 43, 43a separated by isolations 42, 42a, and the same collector region 43, 43
It is composed of P-type base regions 44, 44a formed in a and N-type emitter regions 45, 45a formed in the base regions 44, 44a.

The base 44 of the transistor 15a is the substrate 1
It is connected to the input terminal pad 16a located at the lower right end of 0. The emitter 45a of the transistor 15b is connected to the ground terminal pad 41a located at the upper right end.

The collectors 43, 43a of the transistors 15a, 15b are connected to the output terminal pad 17a adjacent to the ground terminal pad 41a, and the transistors 15a, 15b are Darlington connected.

The prescaler 11 and the amplifier circuit 15 are provided at a predetermined interval (300 μm in this embodiment), and a region between them is a pattern region 18.
The input terminal pad 1 is provided at the lower end of the pattern area 18.
Adjacent to 6a, three probing measurement pads 23
Are formed in rows. Further, another probing measurement pad 23 is formed adjacent to the transistor 15a.

An element characteristic monitor element 18a is formed close to these probing measurement pads 23.
As shown in FIG. 13, the element characteristic monitor element 18a includes a PMOS transistor 19 and an NMOS transistor 2.
It consists of 1.

The PMOS transistor 19 has a P-type diffusion portion 19a formed in a square shape on the N-type semiconductor substrate 10,
19b and a gate portion 2 made of polysilicon and disposed so as to pass above the intermediate portion between the diffusion portions 19a and 19b.
It consists of 2.

On the other hand, the NMOS transistor 21 is
N type diffusion parts 21a and 21b in the P well 20 formed on the type semiconductor substrate 10 and both N type diffusion parts 21a and 21b.
And the gate portion 22 passing above the intermediate portion.

P-type diffusion portions 19a and 19b, N-type diffusion portion 2
1a, 21b and the gate portion 22 are aluminum wiring 24
Are connected to the pads 23, respectively.
In this embodiment, the length of the three pads 23 in a line is about 300 μm.

Further, as shown in FIG. 10, in the pattern region 18, three pads 45a to 45c are formed adjacent to the output terminal pads 17a on the substrate 10. A ring oscillator circuit 25 for high frequency characteristic evaluation is formed near these pads 45a to 45c.

As shown in FIG. 14, this ring oscillation circuit 25 is formed by connecting an odd number of inverters 25a in series, and the oscillation frequency is determined by the delay time of each inverter 25a. An inverter 25b that stabilizes the oscillation of the ring oscillator circuit 25 is connected to the output side of the final stage inverter 25a.

Each of the inverters 25a and 25b has the PMO.
It is composed of PMOS and NMOS transistors similar to the S transistor 19 and the NMOS transistor 21. The power source Vcc is supplied from the pad 45a to the source of the PMOS transistor of each of the inverters 25a and 25b by the aluminum wiring.

The power source GND is supplied from the pad 45b to the source of the NMOS transistor of each of the inverters 25a and 25b by the aluminum wiring. Inverter 25
The output terminal of b is a pad 45c by aluminum wiring.
It is connected to the.

Further, an etching monitor pattern 27 is formed below the pads 45a to 45c so as to be adjacent to the pads 45a to 45c. The pad 2
An exposure size measurement pattern 30 is formed above 3 to be adjacent to the pad 23. Further, a mask number identification character pattern 33 is formed in the area between the ring oscillator circuit 25 and the element characteristic monitor element 18a.

As shown in FIG. 14, the etching monitor pattern 27 has an electrode window portion (about 5 mm) on the diffusion resistance portion 28.
0 micron square size 29 is formed, and four are arranged in this embodiment according to the etching process.

As shown in FIG. 13, the exposure size measuring pattern 30 is composed of nine kinds of MOS gate polysilicon electrodes 31a to 31i. Electrodes 31a, 31d, 31
The width of g is 10 microns, and the electrodes 31b, 31e, 3
The width of 1h is 20 microns, and the electrodes 31c,
The width of 31f and 31i is 40 microns.

The height of the electrodes 31a, 31b, 31c is 40.
The height of the electrodes 31d, 31e, 31f is 20 microns, and the electrodes 31g, 31h, 3 are
The height of 1i is 10 microns. Each electrode 31a-31
i is formed so as to be separated from the adjacent electrodes by 10 microns.

A character pattern 33 is formed on the right side of the exposure size measuring pattern 30, and the size thereof is about 20 μm in length and width. The marking pad 32 is shown adjacent to the pad 45a. 12
As shown in, the pattern 32 is formed of aluminum in a substantially square shape with one side of about 100 microns.
A mask alignment pattern 26 is formed below the pad 32 so as to be adjacent to the pad 32.

The mask alignment pattern 26 has a size of about 60 microns square, and a number (six in this embodiment) of patterns corresponding to the number of masks used in the manufacturing process are arranged in a vertical line. .

As described above, since the PLL synthesizer of this embodiment has the layout described above, the semiconductor substrate 1
The size of 0 can be reduced, the yield can be improved, and the manufacturing cost can be reduced.

Further, since the prescaler 11 and the amplifier circuit 15 are arranged so as to sandwich the pattern region 18, it is possible to reduce the influence on the amplifier circuit 15 due to the switching noise generated by the frequency dividing operation of the prescaler 11.

The present invention is not limited to the above-described embodiment, but may be implemented as follows with a part of the configuration appropriately changed without departing from the spirit of the present invention. (1) In the above embodiment, in addition to the prescaler, the reference frequency divider 47, the comparison frequency divider 53, the phase comparator 48, the charge pump 49, etc. may be arranged on the substrate 10 as a digital circuit section. .

(2) In the above-described embodiment, the reference oscillator 4 is provided on the substrate 10 as the analog circuit part in addition to the amplifier circuit 15.
6, LPF 50, VCO 51, mixer 52, etc. may be arranged.

The technical ideas other than the claims that can be understood from the above embodiments will be described below along with their effects. 7. The semiconductor device according to claim 6, wherein (i) the mask alignment pattern is located substantially in the center of the substrate. With this configuration, the accuracy of alignment can be improved.

Analog circuit: In this specification,
The analog circuit means a circuit that processes a linear value continuous in time, and includes not only an amplifier such as a differential amplifier and an operational amplifier but also a modulation circuit, a demodulation circuit, and the like.

Digital circuit: In this specification,
A digital circuit means a circuit that processes a digital signal composed of two values of “0” and “1”, a logic circuit,
An arithmetic circuit, a flip-flop circuit, and the like are included.

[0066]

As described above in detail, according to the present invention, since the pattern required for manufacturing the semiconductor device is arranged between the digital circuit section and the analog circuit section, the size of the semiconductor chip is reduced and the yield is reduced. It is possible to improve and reduce the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a layout diagram of an embodiment embodying the present invention.

FIG. 3 is a pattern diagram of an element characteristic monitor element and a probing measurement pad.

FIG. 4 is a circuit diagram of a ring oscillator circuit.

FIG. 5 is a pattern diagram of a mask alignment pattern.

FIG. 6 is a pattern diagram of an etching monitor pattern.

FIG. 7 is a pattern diagram of an exposure size measurement pattern.

FIG. 8 is a pattern diagram of a marking pad.

FIG. 9 is a pattern diagram of mask recognition characters.

FIG. 10 is a layout diagram of another embodiment embodying the present invention.

11 is an enlarged view showing the amplifier circuit of FIG. 10 in an enlarged manner.

12 is an enlarged view showing the mask alignment pattern of FIG. 10 in an enlarged manner.

13 is an enlarged view showing the device characteristic monitor device and the probing measurement pad of FIG. 10 in an enlarged manner.

FIG. 14 is an enlarged view showing the ring oscillator circuit of FIG. 10 in an enlarged manner.

FIG. 15 is a block diagram showing a PLL synthesizer embodying the present invention.

FIG. 16 is a layout diagram of a conventional analog / digital mixed type semiconductor device.

[Explanation of symbols]

 1 semiconductor substrate 2 digital circuit section 3 analog circuit section 4 pattern area 11 prescaler as digital circuit section 15 amplification circuit as analog circuit section 18a element characteristic monitor element as pattern 25 ring oscillation circuit as pattern 26 mask position as pattern Alignment pattern 27 Etching monitor pattern as pattern 30 Exposure size measurement pattern as pattern 23 Probing measurement pad as pattern 32 Marking pad as pattern 33 Mask recognition character pattern as pattern 33

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/06 H03L 7/18 H03L 7/18 Z

Claims (11)

[Claims] 1. A semiconductor device in which a digital circuit section (2) for handling a digital signal and an analog circuit section (3) for handling an analog signal are provided on a semiconductor substrate (1) at predetermined intervals, the semiconductor device comprising: Between the digital circuit section (2) and the analog circuit section (3), the digital circuit section (2) and the analog circuit section (3) are irrelevant to each other in terms of circuit, and are necessary for manufacturing a semiconductor device. Pattern area with various patterns (4)
Semiconductor device provided with. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a PLL synthesizer including a prescaler (11) as the digital circuit unit and an amplifier circuit (15) for amplifying an oscillation signal as the analog circuit unit. apparatus. 3. The PLL synthesizer further comprises a phase comparator (48) and a charge pump (49) as the digital circuit section, and a voltage controlled oscillator (51) and a mixer for outputting the oscillation signal as the analog circuit section. The semiconductor device according to claim 2, further comprising (52). 4. The semiconductor device according to claim 1, wherein the pattern includes at least an element characteristic monitor element (18a). 5. The semiconductor device according to claim 1, wherein the pattern includes at least a ring oscillator circuit (25). 6. The semiconductor device according to claim 1, wherein the pattern includes at least a mask alignment pattern (26). 7. The semiconductor device according to claim 1, wherein the pattern includes at least an etching monitor pattern (27). 8. The semiconductor device according to claim 1, wherein the pattern includes at least an exposure size measurement pattern (30). 9. The semiconductor device according to claim 1, wherein the pattern includes a probing measurement pad (23). 10. The semiconductor device according to claim 1, wherein the pattern includes at least a marking pad (32). 11. The semiconductor device according to claim 1, wherein the pattern includes at least a mask recognition character pattern (33).