JPH07273112A - Semiconductor device having multilayer wiring structure and its fabrication - Google Patents

Abstract

PURPOSE:To remove an antireflection film without causing corrosion of a lower layer Al metallization. CONSTITUTION:An underlying insulating film 20 and an Al alloy film 31 are deposited, at first, on an Si substrate 10 and an antireflection film, i.e., an Al2O3 film 33, is deposited on the film 31. The Al2O,3 film 33 and the Al allay film 31 are then patterned by photolithographic process to form a lower layer metallization 30. Subsequently, a layer insulating film 40 is deposited and a via hole 50 is made through the layer insulating film 40 by RIE using a fluorine based gas. Thereafter, the Al2O3 film 33 is removed from the bottom of the via hole 50 by plasma etching using a chlorine based gas. Finally, Al is deposited selectively in the via hole 50 by CVD thus forming a via plug 51.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multi-layer wiring structure, which is provided with an antireflection film for reducing reflection of exposure light in a photolithography process, and a semiconductor device having the multi-layer wiring structure. It is a thing.

[0002]

2. Description of the Related Art When an Al wiring is formed on a semiconductor substrate, the formed Al layer is usually patterned by photolithography. At this time, the line width is 1μ
When forming a fine wiring pattern of m or less, Al
It is necessary to form a film (antireflection film) having a lower reflectance than the Al film on the film. TiN is generally widely used as the material of the antireflection film.

Further, an interlayer insulating film is formed on the lower layer wiring thus formed, and a via hole is formed in the formed interlayer insulating film. Then, Al is deposited in the via hole to form a via plug.

[0004]

However, when Al is deposited in the via hole formed in the interlayer insulating film, the lower wiring and the Al deposited in the via hole are directly bonded without interposing a different material interface. Therefore, it is necessary to remove the antireflection film exposed at the bottom after the via opening by performing RIE with a chlorine-based gas. In this RIE, TiN forming the antireflection film has a lower etching rate than the Al film located in the lower layer. Therefore, when TiN is completely removed in the final stage of RIE, the Al in the lower layer is removed. There was a problem that the erosion of was rapidly progressing.

The present invention has been made to solve such a problem, and an object thereof is to provide a multilayer wiring structure capable of removing an antireflection film without eroding an underlying metal wiring layer containing Al. It is to provide a manufacturing method of a semiconductor device having the same and a semiconductor device having a multilayer wiring structure.

[0006]

Therefore, a method of manufacturing a semiconductor device having a multilayer wiring structure according to the present invention is as follows.
As a first step, a metal wiring layer containing Al is formed on the semiconductor substrate. Next, as a second step, at least one of an oxide film, a nitride film, and a boride film of Al or Al alloy is formed on the surface of the metal wiring layer, and an antireflection film is formed on the metal wiring layer. Form. At this time, as the film to be formed, it is sufficient to form at least one of an Al oxide film, a nitride film and a boride film. Therefore, two kinds are selected from oxidation, nitridation and boride. It includes a film formed of nitride, oxyborido, or oxyboride, or a film formed of Al oxyboride by selecting all three types.

Next, in a third step, the antireflection film and the metal wiring layer below it are patterned to form a lower metal wiring. Next, as a fourth step, an interlayer insulating film is formed on the surface of the semiconductor substrate including the lower metal wiring, and as a fifth step, the interlayer insulating film is formed by reactive ion etching using a fluorine-based gas. Drill a via hole,
The antireflection film is exposed at the bottom of the via hole. Next, the sixth
In the step, the antireflection film at the bottom of the via hole is removed by reactive ion etching using chlorine gas, and the surface of the metal wiring layer is exposed at the bottom of the via hole. And
As a seventh step, a plug metal is selectively deposited in the via hole by the chemical vapor deposition method.

The antireflection film formed in the second step is
An oxide of Al or the like may be deposited on the metal wiring layer, or the surface of the metal wiring layer may be formed by irradiating plasma excited in a reaction gas atmosphere such as oxygen.

Further, a semiconductor device having a multilayer wiring structure according to the present invention includes a metal wiring layer formed of Al or an Al alloy on a semiconductor substrate, and an exposure light in a photolithography process formed on the metal wiring layer. Is provided with an antireflection film having a lower reflectance with respect to the metal wiring layer. The antireflection film is formed of Al or A.
It is formed by including at least one of an oxide, a nitride and a boride of the 1-alloy.

The antireflection film may be formed by depositing an oxide of Al or the like on the metal wiring layer, and the surface of the metal wiring layer may be exposed to a reaction gas atmosphere such as oxygen. It may be formed by irradiating plasma excited in the inside.

Further, the antireflection film thus formed is preferably formed to have a film thickness of 80 to 1000 angstrom.

[0012]

In the method of manufacturing a semiconductor device having a multilayer wiring structure, the antireflection film formed in the second step is made of a material containing at least one of Al, Al alloy oxide, nitride and boride. To do. As a characteristic of these materials, the reflectance of the photolithography performed in the third step with respect to the exposure light is lower than that of the metal wiring layer containing Al, which is the lower layer, and thus can function as an antireflection film in the photolithography step. .

In the fifth step, when a via hole is formed in the upper interlayer insulating film by fluorine-based RIE, the etching rate of the lower antireflection film is lower than that of the interlayer insulating film. It is a sufficiently low value compared to.

Further, in the sixth step, when the antireflection film exposed at the bottom after opening the via hole is removed by chlorine-based RIE, by selecting the RIE condition, the Al located on the lower layer is selected. -The etching rate of the metal wiring layer is a value sufficiently lower than that of the antireflection film.

Further, in the semiconductor device having the multi-layer wiring structure, the antireflection film is formed of a material containing at least an oxide, a nitride or a boride of Al or an Al alloy. To be done.

Since this antireflection film basically does not contribute to the conductivity, it is desirable to make it thin. However, if it is made too thin, the antireflection function will deteriorate, so about 80 to 1000 angstroms. Is desirable.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in the order of steps based on the flow chart shown in FIG. 1 and the process drawings of FIGS.

First, the base insulating film 20 is formed on the Si substrate 10, and the base insulating film 20 is sputtered on the base insulating film 20.
An Al alloy film containing 0.5 wt% of Cu is deposited to a film thickness of 500 nm to form an Al alloy film 3 as a metal wiring layer containing Al.
1 is formed (# 101, FIG. 2A).

Next, as shown in FIG. 2B, Al ₂ O ₃ is deposited to a thickness of 30 nm on the Al alloy film 31 by a reactive sputtering method to form an Al ₂ O ₃ film 33 ( # 10
2, FIG. 2 (b)). The reflectance of the Al ₂ O ₃ film 33 with respect to the exposure light is 4 times the reflectance of the underlying Al alloy film 31.
It is about 5%, and can sufficiently function as an antireflection film.
In order to function as an antireflection film, the reflectance is preferably about 70% or less of the reflectance of the underlying wiring film. Further, the thickness of the antireflection film is preferably made thin because the antireflection film itself basically does not contribute to conductivity, but if it is too thin, the antireflection effect is reduced, so that the thickness is 80 to 1000 angstroms. It is desirable to form the film to a film thickness of the order.

Next, by a photolithography process,
The Al ₂ O ₃ film 33 and the Al alloy film 31 immediately thereunder are processed into a predetermined wiring pattern to form the lower metal wiring 30 (# 103). The wiring pattern is formed by forming a resist pattern using an exposure device and then performing RIE using a chlorine-based gas. At this time, the Al ₂ O ₃ film 3
The reflectance for the exposure light of No. 3 is 45 of the underlying metal wiring 30.
%, Reflected light was suppressed, and a fine resist pattern could be formed well.

Next, the lower metal wiring 30 and the base insulating film 2
An inter-layer insulating film 40 is formed on the surface of 0 (FIG. 2 (c),
# 104). The interlayer insulating film 40 is formed, for example, by depositing a SiO ₂ film on the surface of these by a plasma CVD method, further forming an SOG coating film on this, and then etching back.

Next, after forming a photoresist film on the interlayer insulating film 40, RIE is performed using a fluorine-based gas, and the diameter of the interlayer insulating film 40 is 0.8 μm at a predetermined position.
m via hole 50 is formed (FIG. 2D, # 10).
5). At this time, the Al ₂ O ₃ film 33 at the bottom of the via hole 50 is formed.
Indicates that the lower Al alloy film 31 is sufficiently covered. This is because the etching rate of the Al ₂ O ₃ film 33 in the RIE of the fluorine-based gas is about 5% of that of the interlayer insulating film 40, and the Al ₂ O ₃ film 33 rapidly increases immediately after the via hole is formed. There is no concern that it will be removed, and the via hole can be sufficiently formed to the bottom. In this case, the Al ₂ O ₃ film 33 with respect to the RIE of the fluorine-based gas is used.
And the etching rate of the interlayer insulating film 40 is Al
The etching rate of the ₂ O ₃ film 33 is preferably 10% or less of that of the interlayer insulating film 40. If it is 10% or less, the interlayer insulating film 40 can be efficiently etched, and further, the erosion of the Al ₂ O ₃ film 33 located at the bottom of the via opening can be sufficiently suppressed. If 10%
When the via hole 50 is formed, the Al ₂ O ₃ film 33 is etched and thinned when the via hole 50 is formed, and in a remarkable case, the Al alloy film 31 under the Al ₂ O ₃ film is partially exposed to damage this part. May be given. On the other hand, this Al alloy film 3
In order to prevent the damage of No. 1, if the via hole is refrained from, the hole will not be sufficiently opened to the bottom, and problems such as an increase in resistance value and step lines due to poor connection with the lower metal wiring will occur.

Next, the Al ₂ O exposed at the bottom of the via hole 50 is subjected to plasma etching using a chlorine-based gas.
_{3 The} film 33 is removed (FIG. 3E, # 106). Under this etching condition, the etching rate of the Al ₂ O ₃ film 33 is about 95% of the etching rate of the Al alloy film 31 located thereunder. Therefore, Al ₂ O ₃
Damage to the Al alloy film 31 can be minimized after the film 33 is completely removed. In this case, Al ₂
It is desirable that the etching rate of the O ₃ film 33 is about 80% or more of the etching rate of the Al alloy film 31 located thereunder. This is because if the value is lower than 80%, the erosion of the underlying Al alloy film 31 will rapidly proceed immediately after the Al ₂ O ₃ film 33 is completely removed in the final stage of RIE. Is.

Next, the Si substrate 1 which has been subjected to such treatment
CVD reactor (not shown) without exposing 0 to the atmosphere
And then DMAH (dimethylaluminum hydride) and hydrogen gas were introduced into the reaction vessel,
Al is selectively deposited in the via hole 50 by the chemical vapor deposition method to form the via plug 51 (FIG. 3).
(F), # 107).

Next, Al or an Al alloy is deposited to a film thickness of 400 to 1000 nm by a sputtering method in the same manner as in the case of forming the lower layer metal wiring 30 described above to form an Al alloy film 61 ( FIG. 4 (g)). After that, the Al alloy film 61 is processed into a predetermined pattern to form the upper metal wiring 60 (FIG. 4 (h), # 108), and the semiconductor device having the multilayer wiring structure is manufactured. The formed upper layer metal wiring 60 and lower layer metal wiring 30 are connected to the via plug 5
It is in a state of being electrically connected by 1.

The Al alloy used in this case may be an alloy of the same component as the metal used for the upper layer metal wiring 60 and a metal used for the lower layer metal wiring 30, or an alloy of different components. Is also good.

The inside and the surface of the Si substrate 10 are
Structures necessary for a semiconductor device such as a diffusion layer and a gate electrode are formed. At the required position of the lower insulating film 20,
There is a contact hole, and a contact structure for connecting the lower relative wiring 30 and the diffusion layer or the gate electrode or other structure is formed.

In this embodiment, an example in which an oxide of Al is formed as the antireflection film is shown. However, in addition to this, a nitride, a boride, an oxynitride, an oxyboride of Al or an Al alloy, It can also be formed of a material containing either nitroboride or oxynitride boride. In addition, these substances are
Regarding the reflectance and the etching rate, under the same conditions, the Al ₂ O ₃ film has substantially the same characteristics.

Another embodiment will be shown. Here, the case where the Al ₂ O ₃ film as the antireflection film is formed by another method will be described.

First, a base insulating film 20 is formed on the Si substrate 10 (FIG. 5A), and an Al alloy containing 0.5% by weight of Cu is deposited on the base insulating film 20 by a sputtering method. An Al alloy film 31 is formed (FIG. 5B).

Next, the Si substrate 10 on which the Al alloy film 31 is formed is placed in a reaction gas atmosphere containing oxygen, for example, and plasma is excited therein. Then, by exposing the surface of the Al alloy film 31 to the plasma, the Al ₂ O ₃ film 33 is formed on the surface (FIG. 5).
(C)). The film thickness of this Al ₂ O ₃ film 33 is also 80 to 10
It is desirable to form the film with a thickness of 00 angstrom. The subsequent steps are the same as the steps shown in FIG.

In this example, the antireflection film is formed by exposing the surface of the Al alloy film 31 to plasma excited in a reaction gas atmosphere containing oxygen. By exciting plasma in a reaction gas atmosphere containing at least one of nitrogen and boron and irradiating the surface of the Al alloy film with this plasma,
An antireflection film made of a material containing any one of Al nitride, boride, oxynitride, oxyboride, nitriding boride, or oxynitriding boride may be formed on the surface of the Al alloy film.

[0033]

As described above, according to the method of manufacturing a semiconductor device having a multilayer wiring structure according to the present invention, the antireflection film formed in the second step is formed of Al or Al.
At least one of the oxide film, the nitride film, and the boride film of the alloy is included. Therefore, as a characteristic of these substances, the reflectance with respect to the exposure light of photolithography is lower than that of the underlying metal wiring layer containing Al, so that it can be applied as an antireflection film in the photolithography process.

Further, in the subsequent fifth step, RIE of a fluorine-based gas is applied to the interlayer insulating film formed on the upper layer.
When the via hole is formed by, the etching rate of the antireflection film located below this is sufficiently lower than that of the interlayer insulating film, so that the interlayer insulating film can be efficiently etched and Erosion of the barrier film can be minimized.

Further, in the sixth step, the antireflection film exposed at the bottom after opening the via hole is formed by RIE of chlorine gas.
When removed by, the etching rate of the antireflection film with respect to the underlying metal wiring layer becomes a low value. Therefore, immediately after the antireflection film is completely removed in the final stage of RIE, there is no possibility that the underlying metal wiring layer will be rapidly eroded.

Further, in the semiconductor device having the multilayer wiring structure according to the present invention, the antireflection film is formed of a substance containing at least an oxide, a nitride or a boride of Al or an Al alloy. It is possible to provide a semiconductor device having the above effects.

[Brief description of drawings]

FIG. 1 is a flowchart showing a manufacturing process of a semiconductor device according to this embodiment.

2A to 2C are cross-sectional views of the semiconductor device in the order of manufacturing steps.

3 (d) to 3 (f) are cross-sectional views of the semiconductor device in the order of manufacturing steps.

4 (g) to 4 (h) are cross-sectional views of the semiconductor device in the order of manufacturing steps.

5A to 5C are cross-sectional views of a semiconductor device showing another method of forming an antireflection film in the order of steps.

[Explanation of symbols]

10 ... Si substrate, 20 ... Base insulating film, 31 ... Al alloy film (metal wiring layer), 33 ... Al ₂ O ₃ film (antireflection film).

Front page continuation (72) Inventor Eiichi Kondo 1 Kawasaki-cho, Chuo-ku, Chiba, Chiba Prefecture, Kawasaki Steel Corporation Technical Research Division (72) Inventor Hiroshi Yamamoto 2-3 2-3 Uchisaiwai-cho, Chiyoda-ku, Tokyo Saki Steel Co., Ltd. Tokyo Head Office (72) Inventor Yoyo Ota 1 Kawasaki-cho, Chuo-ku, Chiba-shi, Chiba Kawasaki Steel Co., Ltd.

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device having a multilayer wiring structure, wherein a metal wiring layer containing Al is formed on a semiconductor substrate.
A step of forming an antireflection film on the metal wiring layer by forming at least one of an oxide film, a nitride film and a boride film of Al or Al alloy on the surface of the metal wiring layer; 2 steps, a third step of forming a lower layer metal wiring by patterning the antireflection film and the lower layer metal wiring layer by photolithography, and an interlayer on the surface of the semiconductor substrate including the lower layer metal wiring. A fourth step of forming an insulating film and a reactive ion etching using a fluorine-based gas to form a via hole in the interlayer insulating film, and expose the antireflection film at the bottom of the via hole. The fifth step and reactive ion etching using a chlorine-based gas remove the antireflection film at the bottom of the via hole, exposing the surface of the metal wiring layer at the bottom of the via hole. 6 and step by chemical vapor deposition, a method of manufacturing a semiconductor device having a multilayer wiring structure and having a seventh step of selectively depositing a metal plug, to the via hole to. 2. In the second step, on the metal wiring layer,
2. The multilayer wiring according to claim 1, wherein the antireflection film is formed on the metal wiring layer by depositing at least one of an oxide, a nitride, and a boride of Al or an Al alloy. Method for manufacturing a semiconductor device having a structure. 3. In the second step, plasma is excited in a reaction gas atmosphere containing at least one of oxygen, nitrogen, and boron, and the surface of the metal wiring layer is irradiated with the plasma. The method of manufacturing a semiconductor device having a multilayer wiring structure according to claim 1, wherein the antireflection film is formed on the metal wiring layer. 4. A metal wiring layer containing Al formed on a semiconductor substrate; and a reflectance of the metal wiring layer formed on the metal wiring layer for exposure light of photolithography, which is lower than that of the metal wiring layer. An anti-reflection film, wherein the anti-reflection film is formed by including at least one of oxides, nitrides and borides of Al or Al alloy. A semiconductor device having. 5. The antireflection film is formed on the metal wiring layer,
5. The semiconductor device having a multilayer wiring structure according to claim 4, wherein the semiconductor device is formed by depositing a substance containing at least one of an oxide, a nitride and a boride of Al or an Al alloy. 6. The antireflection film is formed by subjecting the surface of the metal wiring layer to at least one of oxidation, nitridation, and boration. A semiconductor device having a multilayer wiring structure of. 7. The semiconductor device having a multilayer wiring structure according to claim 4, wherein the antireflection film is formed to have a film thickness of 80 to 1000 angstroms.