JPH07271968A - Image information transfer device - Google Patents

Abstract

PURPOSE:To transfer reference information to an image processing part without using a line memory by successively reading the image information of each line from a memory based on the address designation of each picture element of each line of reference image information. CONSTITUTION:When the leading address set by a conversion leading address setting part 12 is supplied to an adder 14a when a high image quality processing is performed by defining image information of 4 picture elements X 8 lines, for instance, as reference image information, the set data of a one-line byte number setting part 13 is successively supplied to adders 14b to 14h. A selector 18 selects counters 15a to 15h, the image information of the first byte, the second byte ... of a 8-line from a page memory 11 is successively latched in latch circuits 19a to 19h, the information is converted into serial data in parallel/ serial converters 20a to 20h, further, the data is converted into parallel data in serial/parallel converters 21a to 21h, and the data is inputted in a high image quality processing circuit 22. Thus, the device becomes possible to be miniaturized without using a line memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information transfer device for transferring image information stored in a memory to an image processing section for performing resolution conversion and smoothing processing, for example.

[0002]

2. Description of the Related Art For example, 200 dpi facsimile data is temporarily stored in a page memory, then read out and transferred to an image processing section, and resolution conversion and smoothing processing are performed in order to print the image with a 300 dpi laser printer. After going, it outputs to the laser printer.

The image processing unit for performing such image processing is
Image processing such as resolution conversion and smoothing processing is performed by referring to image information units of n pixels × m lines (where n ≧ 2 and m ≧ 2).

A conventional image information transfer device for transferring image information from a page memory to such an image processing unit in image information units of n pixels × m lines is shown in FIG.

That is, a conversion head address setting unit 2 for setting the head address of reference image information in the page memory 1 is provided, and the head address set in the setting unit 2 is set in a counter 3, and the counter 3 sets the page memory 1 in place. Of the reference image information to the latch circuit 4 by specifying the address of
Latch at the timing of ATCK.

On the other hand, a line memory selection unit 5 is provided, and the line memory selection unit 5 selects, for example, eight line memories 7a to 7h via the decoder 6.

The image information latched by the latch circuit 4 is converted into serial data by a parallel / serial converter (P / S) 8 at a predetermined timing by a clock PSCK and a signal PSLD, and the line data among the line memories 7a to 7h is converted. The memory is stored in the line memory selected by the memory selection unit 5. Then, the page memories 1 to 1 are added to the selected line memories by counting up the counter 3 with the clock CLK.
Stores image information for lines. By performing this for 8 lines, image information for 8 lines is stored in each of the line memories 7a to 7h.

The image information stored in each of the line memories 7a to 7h is converted into parallel data by the serial / parallel converters (S / P) 9a to 9h at the timing of the clock CKOUT, and an image quality improving processing circuit which is an image processing unit. Supplied to 10.

The high image quality processing circuit 10 performs image processing such as resolution conversion and smoothing processing by referring to input image information in image information units of, for example, 4 pixels × 8 lines.

FIG. 9 is a timing chart showing the write operation to the line memory of this conventional device. That is, the counter 3 sets the address of the first line to 0000H, 0001H, 0002H, ...
Data of the first line are sequentially read from the page memory 1 as 1L-1, 1L-2, 1L-3, ... And are latched in the latch circuit 4 at the timing of the signal LATCK to perform parallel / serial conversion. The converter (P / S) 8 converts the data into serial data at a predetermined timing by the clock PSCK and the signal PSLD. Then, serial data is sequentially stored in the line memory 7a at the timing of the clock CK0. In this way, the serial data 1L-1, 1L-2, 1L-3, ... Of the first line are written in the line memory 7a.

When the image information of one line is written in each of the line memories 7a to 7h, each of the line memories 7a to 7h.
Image information of 7h is serial / parallel converter (S / P) sequentially at the timing shown in FIG. 10 by the clock CKOUT.
It is converted into parallel data at 9a to 9h and supplied to the image quality improvement processing circuit 10.

[0012]

In the conventional device having such a structure, the line memory for storing the serial data for one line is required for the number of lines of the reference image information, and therefore, it is necessary when the number of lines to be referred is large. There is a problem that the number of line memories increases and the capacity of the line memory increases as the amount of image information per line increases. For example, when the line memory is assembled by a gate array, the mounting area of the circuit board is increased. Has a problem that it becomes large and large, and the cost becomes high. A line memory for storing image information of A4 size is usually 2,0
A device that can store 00 pixels is required.

Therefore, according to the present invention, the reference image information can be transferred to the image processing section without using a line memory. Therefore, the mounting area can be reduced, the size can be reduced, and the cost can be reduced. Provide a device.

[0014]

According to the present invention, image information stored in a memory is represented by n pixels × m lines (where n ≧ 2.
In an image information transfer apparatus that refers to each image information unit of m ≧ 2) and transfers each pixel to an image processing unit that sequentially performs image processing, a unit for setting a start address of reference image information in a memory and an image of one line. Means to set the length of information,
Of the image information stored in the memory based on the start address set in each setting means and the length of the image information of one line, the address of each pixel of each line of the reference image information of n pixels × m lines is set. Means for sequentially designating and means for sequentially reading out the image information of each pixel of the m line from the memory based on the address designation by the address designating means and transferring it to the image processing unit are provided.

[0015]

In the present invention having such a configuration, among the image information stored in the memory based on the set start address and the length of the image information of one line, the reference image information of n pixels × m lines is stored. Specify the address of each pixel on each line in sequence,
Based on the address designation, the image information of each pixel on the m line is sequentially read from the memory and transferred to the image processing unit.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is a page memory storing image information for one page, 12 is a conversion start address setting unit for setting the start address of reference image information to be converted in the page memory 11, and 13 is an image for one line. This is a 1-line byte number setting unit that sets the length of information, that is, the number of bytes, for example, 216 bytes (00D8H).

The set address of the conversion start address setting unit 12 is supplied to the adder 14a. This adder 14
Also, 0 data is supplied to a.

The setting data of the 1-line byte number setting unit 13 is supplied to the adders 14b to 14h, respectively.

The output of the adder 14a is a counter (CN
0) 15a and the adder 14b. The output of the adder 14b is a counter (CN1)
15b and the adder 14c. The output of the adder 14c is the counter (CN2) 15
It is also supplied to the adder 14d.
The output of the adder 14d is supplied to a counter (CN3) 15d and also to the adder 14e. The output of the adder 14e is supplied to the counter (CN4) 15e and also to the adder 14f. The output of the adder 14f is supplied to the counter (CN5) 15f and also to the adder 14g. The adder 1
The output of 4 g is supplied to the counter (CN6) 15g and the adder 14h. The adder 14h
Is supplied to the counter (CN7) 15h.

The clock is counted by the counter 16 and supplied to the decoder 17. The count data of the counter 16 is supplied to the terminals A, B, C of the selector 18 and the decoder 17.

The decoder 17 includes the counters 15a.
15h to 15h are supplied with the clocks CK0 to CK7, and the latch circuits 19a to 19h are supplied with the clocks CKA to CKH, respectively.

The selector 18 uses the counters 15a to 15d based on the count data input to the terminals A, B and C.
Control to selectively input the count data of 15h to the addressing terminal of the page memory 11 is performed.

The adders 14a to 14h and the counter 15
a to 15h, 16, the decoder 17 and the selector 18 are
It constitutes a means for sequentially designating the address of each pixel of each line of the reference image information.

Each of the latch circuits 19a to 19h latches image information read from the page memory 11 at timings of clocks CKA to CKH, and the latched image information is respectively parallel / serial converter (P / S). It is supplied to 20a to 20h.

Each of the parallel / serial converters (P /
S) 20a to 20h are clock PSCK and signal PS
Each of the latch circuits 19a is set by the LD at a predetermined timing.
19h to 19h are converted into serial data and supplied to the serial / parallel converters (S / P) 21a to 21h, respectively.

Each of the serial / parallel converters (S /
P) 21a to 21h are connected to the parallel / serial converters (P /
S) The serial data from 20a to 20h is converted into parallel data and supplied to the high image quality processing circuit 22 which is an image processing unit.

The latch circuits 19a to 19h, the parallel / serial converters (P / S) 20a to 20h, and the serial / parallel converters (S / P) 21a to 21h.
Constitutes a means for sequentially reading out image information of each pixel of 8 lines from the page memory 11 and transferring it to the high image quality processing circuit 22.

The high image quality processing circuit 22 takes in image information from the serial / parallel converters (S / P) 21a to 21h, and performs resolution conversion and smoothing, for example, using image information of 4 pixels × 8 lines as reference image information. Alternatively, high image quality processing such as graphic recognition is performed.

The page memory 11 stores image information for one page as 216 bytes per line as shown in FIG.

In such a configuration, the start address set in the conversion start address setting unit 12 is "000H".
Then, the image information of one line set in the one line byte number setting unit 13 is "00D8H", and therefore each counter 15
The data initially set in a to 15h is "000.
"H""00D8H""01B0H""0288H""0
360H ”“ 0438H ”“ 0510H ”“ 05E8 ”
H ”.

The count value of the counter 16 is initially C =
0, B = 0, A = 0, and 001, 0 depending on the clock
10,011,100,101,110,111,00
It changes to 0, ...

As a result, the selector 18 causes each counter 15 to
The counter data of a to 15h are sequentially selected.

That is, the count data input to the addressing terminal of the page memory 11 by the selector 18 is "000H""00D8H""01B0H""02".
88H "" 0360H "" 0438H "" 0510H "
It changes to "05E8H", which causes page memory 11
1st byte image information of each line from "1L-1""2L
-1 "" 3L-1 "" 4L-1 "" 5L-1 "" 6L- "
1 "," 7L-1 ", and" 8L-1 "are sequentially read and latched by the latch circuits 19a to 19h at the timings of the clocks CKA to CKH.

Each of the counters 15a to 15h has image information "1L-1""2L-1""3L-1""4L-".
1 "," 5L-1, "" 6L-1, "" 7L-1, "" 8L-
"1" is incremented by 1 each time it is latched by each of the latch circuits 19a to 19h.

Therefore, when the image information "1L-1" of the first byte of the first line is latched by the latch circuit 19a, the counter (CN0) 15a becomes "001H", and the image of the first byte of the second line is displayed. Information "2L-1" is the latch circuit 1
When it is latched by 9b, the counter (CN1) 15b becomes "00D9H", and when the image information "3L-1" of the first byte of the third line is latched by the latch circuit 19c,
The counter (CN2) 15c becomes "01B1H", and when the 1st byte image information "4L-1" of the fourth line is latched by the latch circuit 19d, the counter (CN3) 15d.
Becomes “0289H”.

When the image information "5L-1" of the first byte of the fifth line is latched by the latch circuit 19e, the counter (CN4) 15e becomes "0361H", and the sixth
When the image information "6L-1" of the first byte of the line is latched by the latch circuit 19f, the counter (CN5) 15f becomes "0439H", and the image information "7L-1" of the first byte of the seventh line is changed. When latched by the latch circuit 19g,
The counter (CN6) 15g becomes "0511H", and when the first byte image information "8L-1" of the eighth line is latched by the latch circuit 19h, the counter (CN7) 15h.
Is "05E9H".

FIG. 3 shows the above operation timing.

The image information latched by the latch circuits 19a to 19h is once converted into serial data by the parallel / serial converters 20a to 20h, and then converted into parallel data by the serial / parallel converters 21a to 21h. It is input to the image quality improvement processing circuit 22.

In this way, when the image information of the 1st byte of 8 lines is input to the image quality improvement processing circuit 22, the selector 18 again selects the count data of the counter 15a.

Thus, the selector 18 has the counters 15a ...
The selection of 15h is repeated, whereby the page memory 11
From the 8th line, the image information of the 2nd byte, 3rd byte, 4th byte, ... Of 8 lines is sequentially latched by the latch circuits 19a to 19h, converted into serial data by the parallel / serial converters 20a to 20h, and further serial / serial. It is converted into parallel data by the parallel converters 21a to 21h and input to the image quality improvement processing circuit 22.

Serial / parallel converters 21a to 21h
4 shows the timing of the image information input to the image quality improvement processing circuit 22.

The high image quality processing circuit 22 performs high image quality processing with image information of 8 lines × 4 pixels. For example, 200 dp
When the resolution of the image information of i is converted into the image information of 300 dpi, the image information of 200 lines of 8 lines × 4 pixels as shown in (a) of FIG. Converted to 300 dpi image information of line × 6 pixels. At this time, if the image information indicates a shaded portion, smoothing processing is performed to smooth the shaded line.

The high image quality processing circuit 22 also performs noise elimination processing. For example, in the case of a facsimile, when reading an image with a reading unit, noise pixels are generated in places due to dust, dirt on an original, or the like. Moreover, since black pixels occur in the middle of the white line, the amount of code data increases and the transmission time becomes long. In order to solve such a problem, the image quality improvement processing circuit 22 performs noise elimination processing.

For example, if a reference area of 5 lines × 5 pixels is used, and if there is a fixed amount of white pixel groups in which two or more pixels are connected to the periphery of the pixel of interest a as reference pixels, it is determined to be noise and white data is obtained. Convert.

For example, in the case shown in FIG.
As shown in FIG. 6B, it is determined that there are only five white pixel groups connected to each other, and in this case, the target pixel a is determined to be a black pixel.

Further, for example, in the case shown in FIG. 7A, it is judged that there are eight white pixel groups in which two or more pixels are connected in the periphery as shown in FIG. 7B, and in this case, attention is paid. The pixel a is determined to be a white pixel.

For each of the eight lines, the image information for one line is output from the page memory 11 to the high-quality image processing circuit 22.
When the transfer to the end is completed, the conversion start address setting unit 12 sets the start address of the first one line for the next eight lines.

Then, the same processing as that described above is performed to transfer the image information for one line for each of the next eight lines from the page memory 11 to the image quality improvement processing circuit 22.

In this way, the sequential transfer is repeated every eight lines,
When the transfer of the image information for one page stored in the page memory 11 is completed, the processing ends.

This processing is restarted when the image information for the next one page is stored in the page memory 11.

As described above, the eight adders 14a to 14h and the eight counters 15 are used without using the line memory at all.
a to 15h, eight latch circuits 19a to 19h, and eight parallel / serial converters 20a to 20h, the image information can be transferred from the page memory 11 to the high image quality processing circuit 22. The configuration can be made smaller than that when a line memory is used, and the mounting area can be made smaller when mounted on a circuit board, and the size can be reduced. Further, cost reduction can be sufficiently achieved.

In the above embodiment, the image quality improvement processing circuit 22 is used.
As described above, the one in which the resolution processing and the smoothing processing are performed by referring to the image information of 8 lines × 4 pixels has been described, but it goes without saying that the present invention is not necessarily limited to this. In particular, if the number of lines is different, the number of adders, counters, latch circuits, parallel / serial converters, and serial / parallel converters to be used will also match the number of lines.

Although the page memory for storing the image information for one page is used as the memory in the above embodiment, it is needless to say that the page memory is not necessarily limited to this.

[0055]

As described above, according to the present invention, the reference image information can be transferred to the image processing section without using the line memory,
Therefore, it is possible to provide an image information transfer device that can reduce the mounting area, realize a miniaturization, and sufficiently reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a storage state of image information in the page memory of the embodiment.

FIG. 3 is a diagram showing an operation timing of each unit when image information of the page memory of the embodiment is read to a latch circuit.

FIG. 4 is a diagram showing the timing of image information input from the serial / parallel converter of the embodiment to the image quality improvement processing circuit.

FIG. 5 is a diagram for explaining resolution conversion and smoothing processing of the high image quality processing circuit of the embodiment.

FIG. 6 is a diagram for explaining noise elimination processing of the image quality improvement processing circuit of the embodiment.

FIG. 7 is a diagram for explaining noise elimination processing of the image quality improvement processing circuit of the embodiment.

FIG. 8 is a block diagram showing a conventional example.

FIG. 9 is a view showing a timing when image information of a page memory of the conventional example is written in a line memory.

FIG. 10 is a diagram showing timings of line memory output and serial / parallel converter output in the conventional example.

[Explanation of symbols]

 11 ... Page memory 12 ... Conversion start address setting unit 13 ... 1 line byte number setting unit 14a-14h ... Adder 15a-15h ... Counter 16 ... Counter 17 ... Decoder 18 ... Selector 19a-19h ... Latch circuit 20a-20h ... Parallel / Serial converters 21a to 21h ... Serial / parallel converter 22 ... Image quality improvement processing circuit

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H04N 1/21

Claims (1)

[Claims] 1. An image processing unit for sequentially performing image processing on a pixel-by-pixel basis with reference to image information stored in a memory in image information units of n pixels × m lines (where n ≧ 2 and m ≧ 2). In the image information transfer device for transferring to, the means for setting the start address of the reference image information in the memory, the means for setting the length of the image information of one line,
Of the image information stored in the memory based on the start address set in each setting means and the length of the image information of one line, the address of each pixel of each line of the reference image information of n pixels × m lines And means for sequentially designating from the memory based on the addressing by the addressing means.
An image information transfer apparatus comprising means for sequentially reading out image information of each pixel of a line and transferring the image information to the image processing unit.